soc/ux500/ux500_msp_dai.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) ST-Ericsson SA 2012
0004  *
0005  * Author: Ola Lilja <ola.o.lilja@stericsson.com>,
0006  *         Roger Nilsson <roger.xr.nilsson@stericsson.com>
0007  *         for ST-Ericsson.
0008  */
0009
0010 #ifndef UX500_msp_dai_H
0011 #define UX500_msp_dai_H
0012
0013 #include <linux/types.h>
0014 #include <linux/spinlock.h>
0015
0016 #include "ux500_msp_i2s.h"
0017
0018 #define UX500_NBR_OF_DAI    4
0019
0020 #define UX500_I2S_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |   \
0021             SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
0022
0023 #define UX500_I2S_FORMATS (SNDRV_PCM_FMTBIT_S16_LE)
0024
0025 #define FRAME_PER_SINGLE_SLOT_8_KHZ     31
0026 #define FRAME_PER_SINGLE_SLOT_16_KHZ    124
0027 #define FRAME_PER_SINGLE_SLOT_44_1_KHZ  63
0028 #define FRAME_PER_SINGLE_SLOT_48_KHZ    49
0029 #define FRAME_PER_2_SLOTS               31
0030 #define FRAME_PER_8_SLOTS               138
0031 #define FRAME_PER_16_SLOTS              277
0032
0033 #define UX500_MSP_INTERNAL_CLOCK_FREQ  40000000
0034 #define UX500_MSP1_INTERNAL_CLOCK_FREQ UX500_MSP_INTERNAL_CLOCK_FREQ
0035
0036 #define UX500_MSP_MIN_CHANNELS      1
0037 #define UX500_MSP_MAX_CHANNELS      8
0038
0039 #define PLAYBACK_CONFIGURED     1
0040 #define CAPTURE_CONFIGURED      2
0041
0042 enum ux500_msp_clock_id {
0043     UX500_MSP_MASTER_CLOCK,
0044 };
0045
0046 struct ux500_msp_i2s_drvdata {
0047     struct ux500_msp *msp;
0048     struct regulator *reg_vape;
0049     unsigned int fmt;
0050     unsigned int tx_mask;
0051     unsigned int rx_mask;
0052     int slots;
0053     int slot_width;
0054
0055     /* Clocks */
0056     unsigned int master_clk;
0057     struct clk *clk;
0058     struct clk *pclk;
0059
0060     /* Regulators */
0061     int vape_opp_constraint;
0062 };
0063
0064 int ux500_msp_dai_set_data_delay(struct snd_soc_dai *dai, int delay);
0065
0066 #endif