soc/ti/omap-mcpdm.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * omap-mcpdm.h
0004  *
0005  * Copyright (C) 2009 - 2011 Texas Instruments
0006  *
0007  * Contact: Misael Lopez Cruz <misael.lopez@ti.com>
0008  */
0009
0010 #ifndef __OMAP_MCPDM_H__
0011 #define __OMAP_MCPDM_H__
0012
0013 #define MCPDM_REG_REVISION      0x00
0014 #define MCPDM_REG_SYSCONFIG     0x10
0015 #define MCPDM_REG_IRQSTATUS_RAW     0x24
0016 #define MCPDM_REG_IRQSTATUS     0x28
0017 #define MCPDM_REG_IRQENABLE_SET     0x2C
0018 #define MCPDM_REG_IRQENABLE_CLR     0x30
0019 #define MCPDM_REG_IRQWAKE_EN        0x34
0020 #define MCPDM_REG_DMAENABLE_SET     0x38
0021 #define MCPDM_REG_DMAENABLE_CLR     0x3C
0022 #define MCPDM_REG_DMAWAKEEN     0x40
0023 #define MCPDM_REG_CTRL          0x44
0024 #define MCPDM_REG_DN_DATA       0x48
0025 #define MCPDM_REG_UP_DATA       0x4C
0026 #define MCPDM_REG_FIFO_CTRL_DN      0x50
0027 #define MCPDM_REG_FIFO_CTRL_UP      0x54
0028 #define MCPDM_REG_DN_OFFSET     0x58
0029
0030 /*
0031  * MCPDM_IRQ bit fields
0032  * IRQSTATUS_RAW, IRQSTATUS, IRQENABLE_SET, IRQENABLE_CLR
0033  */
0034
0035 #define MCPDM_DN_IRQ            (1 << 0)
0036 #define MCPDM_DN_IRQ_EMPTY      (1 << 1)
0037 #define MCPDM_DN_IRQ_ALMST_EMPTY    (1 << 2)
0038 #define MCPDM_DN_IRQ_FULL       (1 << 3)
0039
0040 #define MCPDM_UP_IRQ            (1 << 8)
0041 #define MCPDM_UP_IRQ_EMPTY      (1 << 9)
0042 #define MCPDM_UP_IRQ_ALMST_FULL     (1 << 10)
0043 #define MCPDM_UP_IRQ_FULL       (1 << 11)
0044
0045 #define MCPDM_DOWNLINK_IRQ_MASK     0x00F
0046 #define MCPDM_UPLINK_IRQ_MASK       0xF00
0047
0048 /*
0049  * MCPDM_DMAENABLE bit fields
0050  */
0051
0052 #define MCPDM_DMA_DN_ENABLE     (1 << 0)
0053 #define MCPDM_DMA_UP_ENABLE     (1 << 1)
0054
0055 /*
0056  * MCPDM_CTRL bit fields
0057  */
0058
0059 #define MCPDM_PDM_UPLINK_EN(x)      (1 << (x - 1)) /* ch1 is at bit 0 */
0060 #define MCPDM_PDM_DOWNLINK_EN(x)    (1 << (x + 2)) /* ch1 is at bit 3 */
0061 #define MCPDM_PDMOUTFORMAT      (1 << 8)
0062 #define MCPDM_CMD_INT           (1 << 9)
0063 #define MCPDM_STATUS_INT        (1 << 10)
0064 #define MCPDM_SW_UP_RST         (1 << 11)
0065 #define MCPDM_SW_DN_RST         (1 << 12)
0066 #define MCPDM_WD_EN         (1 << 14)
0067 #define MCPDM_PDM_UP_MASK       0x7
0068 #define MCPDM_PDM_DN_MASK       (0x1f << 3)
0069
0070
0071 #define MCPDM_PDMOUTFORMAT_LJUST    (0 << 8)
0072 #define MCPDM_PDMOUTFORMAT_RJUST    (1 << 8)
0073
0074 /*
0075  * MCPDM_FIFO_CTRL bit fields
0076  */
0077
0078 #define MCPDM_UP_THRES_MAX      0xF
0079 #define MCPDM_DN_THRES_MAX      0xF
0080
0081 /*
0082  * MCPDM_DN_OFFSET bit fields
0083  */
0084
0085 #define MCPDM_DN_OFST_RX1_EN        (1 << 0)
0086 #define MCPDM_DNOFST_RX1(x)     ((x & 0x1f) << 1)
0087 #define MCPDM_DN_OFST_RX2_EN        (1 << 8)
0088 #define MCPDM_DNOFST_RX2(x)     ((x & 0x1f) << 9)
0089
0090 void omap_mcpdm_configure_dn_offsets(struct snd_soc_pcm_runtime *rtd,
0091                     u8 rx1, u8 rx2);
0092
0093 #endif  /* End of __OMAP_MCPDM_H__ */