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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * omap-mcbsp.c  --  OMAP ALSA SoC DAI driver using McBSP port
0004  *
0005  * Copyright (C) 2008 Nokia Corporation
0006  *
0007  * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
0008  *          Peter Ujfalusi <peter.ujfalusi@ti.com>
0009  */
0010 
0011 #include <linux/init.h>
0012 #include <linux/module.h>
0013 #include <linux/device.h>
0014 #include <linux/pm_runtime.h>
0015 #include <linux/of.h>
0016 #include <linux/of_device.h>
0017 #include <sound/core.h>
0018 #include <sound/pcm.h>
0019 #include <sound/pcm_params.h>
0020 #include <sound/initval.h>
0021 #include <sound/soc.h>
0022 #include <sound/dmaengine_pcm.h>
0023 
0024 #include "omap-mcbsp-priv.h"
0025 #include "omap-mcbsp.h"
0026 #include "sdma-pcm.h"
0027 
0028 #define OMAP_MCBSP_RATES    (SNDRV_PCM_RATE_8000_96000)
0029 
0030 enum {
0031     OMAP_MCBSP_WORD_8 = 0,
0032     OMAP_MCBSP_WORD_12,
0033     OMAP_MCBSP_WORD_16,
0034     OMAP_MCBSP_WORD_20,
0035     OMAP_MCBSP_WORD_24,
0036     OMAP_MCBSP_WORD_32,
0037 };
0038 
0039 static void omap_mcbsp_dump_reg(struct omap_mcbsp *mcbsp)
0040 {
0041     dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
0042     dev_dbg(mcbsp->dev, "DRR2:  0x%04x\n", MCBSP_READ(mcbsp, DRR2));
0043     dev_dbg(mcbsp->dev, "DRR1:  0x%04x\n", MCBSP_READ(mcbsp, DRR1));
0044     dev_dbg(mcbsp->dev, "DXR2:  0x%04x\n", MCBSP_READ(mcbsp, DXR2));
0045     dev_dbg(mcbsp->dev, "DXR1:  0x%04x\n", MCBSP_READ(mcbsp, DXR1));
0046     dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n", MCBSP_READ(mcbsp, SPCR2));
0047     dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n", MCBSP_READ(mcbsp, SPCR1));
0048     dev_dbg(mcbsp->dev, "RCR2:  0x%04x\n", MCBSP_READ(mcbsp, RCR2));
0049     dev_dbg(mcbsp->dev, "RCR1:  0x%04x\n", MCBSP_READ(mcbsp, RCR1));
0050     dev_dbg(mcbsp->dev, "XCR2:  0x%04x\n", MCBSP_READ(mcbsp, XCR2));
0051     dev_dbg(mcbsp->dev, "XCR1:  0x%04x\n", MCBSP_READ(mcbsp, XCR1));
0052     dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n", MCBSP_READ(mcbsp, SRGR2));
0053     dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n", MCBSP_READ(mcbsp, SRGR1));
0054     dev_dbg(mcbsp->dev, "PCR0:  0x%04x\n", MCBSP_READ(mcbsp, PCR0));
0055     dev_dbg(mcbsp->dev, "***********************\n");
0056 }
0057 
0058 static int omap2_mcbsp_set_clks_src(struct omap_mcbsp *mcbsp, u8 fck_src_id)
0059 {
0060     struct clk *fck_src;
0061     const char *src;
0062     int r;
0063 
0064     if (fck_src_id == MCBSP_CLKS_PAD_SRC)
0065         src = "pad_fck";
0066     else if (fck_src_id == MCBSP_CLKS_PRCM_SRC)
0067         src = "prcm_fck";
0068     else
0069         return -EINVAL;
0070 
0071     fck_src = clk_get(mcbsp->dev, src);
0072     if (IS_ERR(fck_src)) {
0073         dev_err(mcbsp->dev, "CLKS: could not clk_get() %s\n", src);
0074         return -EINVAL;
0075     }
0076 
0077     pm_runtime_put_sync(mcbsp->dev);
0078 
0079     r = clk_set_parent(mcbsp->fclk, fck_src);
0080     if (r)
0081         dev_err(mcbsp->dev, "CLKS: could not clk_set_parent() to %s\n",
0082             src);
0083 
0084     pm_runtime_get_sync(mcbsp->dev);
0085 
0086     clk_put(fck_src);
0087 
0088     return r;
0089 }
0090 
0091 static irqreturn_t omap_mcbsp_irq_handler(int irq, void *data)
0092 {
0093     struct omap_mcbsp *mcbsp = data;
0094     u16 irqst;
0095 
0096     irqst = MCBSP_READ(mcbsp, IRQST);
0097     dev_dbg(mcbsp->dev, "IRQ callback : 0x%x\n", irqst);
0098 
0099     if (irqst & RSYNCERREN)
0100         dev_err(mcbsp->dev, "RX Frame Sync Error!\n");
0101     if (irqst & RFSREN)
0102         dev_dbg(mcbsp->dev, "RX Frame Sync\n");
0103     if (irqst & REOFEN)
0104         dev_dbg(mcbsp->dev, "RX End Of Frame\n");
0105     if (irqst & RRDYEN)
0106         dev_dbg(mcbsp->dev, "RX Buffer Threshold Reached\n");
0107     if (irqst & RUNDFLEN)
0108         dev_err(mcbsp->dev, "RX Buffer Underflow!\n");
0109     if (irqst & ROVFLEN)
0110         dev_err(mcbsp->dev, "RX Buffer Overflow!\n");
0111 
0112     if (irqst & XSYNCERREN)
0113         dev_err(mcbsp->dev, "TX Frame Sync Error!\n");
0114     if (irqst & XFSXEN)
0115         dev_dbg(mcbsp->dev, "TX Frame Sync\n");
0116     if (irqst & XEOFEN)
0117         dev_dbg(mcbsp->dev, "TX End Of Frame\n");
0118     if (irqst & XRDYEN)
0119         dev_dbg(mcbsp->dev, "TX Buffer threshold Reached\n");
0120     if (irqst & XUNDFLEN)
0121         dev_err(mcbsp->dev, "TX Buffer Underflow!\n");
0122     if (irqst & XOVFLEN)
0123         dev_err(mcbsp->dev, "TX Buffer Overflow!\n");
0124     if (irqst & XEMPTYEOFEN)
0125         dev_dbg(mcbsp->dev, "TX Buffer empty at end of frame\n");
0126 
0127     MCBSP_WRITE(mcbsp, IRQST, irqst);
0128 
0129     return IRQ_HANDLED;
0130 }
0131 
0132 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *data)
0133 {
0134     struct omap_mcbsp *mcbsp = data;
0135     u16 irqst_spcr2;
0136 
0137     irqst_spcr2 = MCBSP_READ(mcbsp, SPCR2);
0138     dev_dbg(mcbsp->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
0139 
0140     if (irqst_spcr2 & XSYNC_ERR) {
0141         dev_err(mcbsp->dev, "TX Frame Sync Error! : 0x%x\n",
0142             irqst_spcr2);
0143         /* Writing zero to XSYNC_ERR clears the IRQ */
0144         MCBSP_WRITE(mcbsp, SPCR2, MCBSP_READ_CACHE(mcbsp, SPCR2));
0145     }
0146 
0147     return IRQ_HANDLED;
0148 }
0149 
0150 static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *data)
0151 {
0152     struct omap_mcbsp *mcbsp = data;
0153     u16 irqst_spcr1;
0154 
0155     irqst_spcr1 = MCBSP_READ(mcbsp, SPCR1);
0156     dev_dbg(mcbsp->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
0157 
0158     if (irqst_spcr1 & RSYNC_ERR) {
0159         dev_err(mcbsp->dev, "RX Frame Sync Error! : 0x%x\n",
0160             irqst_spcr1);
0161         /* Writing zero to RSYNC_ERR clears the IRQ */
0162         MCBSP_WRITE(mcbsp, SPCR1, MCBSP_READ_CACHE(mcbsp, SPCR1));
0163     }
0164 
0165     return IRQ_HANDLED;
0166 }
0167 
0168 /*
0169  * omap_mcbsp_config simply write a config to the
0170  * appropriate McBSP.
0171  * You either call this function or set the McBSP registers
0172  * by yourself before calling omap_mcbsp_start().
0173  */
0174 static void omap_mcbsp_config(struct omap_mcbsp *mcbsp,
0175                   const struct omap_mcbsp_reg_cfg *config)
0176 {
0177     dev_dbg(mcbsp->dev, "Configuring McBSP%d  phys_base: 0x%08lx\n",
0178         mcbsp->id, mcbsp->phys_base);
0179 
0180     /* We write the given config */
0181     MCBSP_WRITE(mcbsp, SPCR2, config->spcr2);
0182     MCBSP_WRITE(mcbsp, SPCR1, config->spcr1);
0183     MCBSP_WRITE(mcbsp, RCR2, config->rcr2);
0184     MCBSP_WRITE(mcbsp, RCR1, config->rcr1);
0185     MCBSP_WRITE(mcbsp, XCR2, config->xcr2);
0186     MCBSP_WRITE(mcbsp, XCR1, config->xcr1);
0187     MCBSP_WRITE(mcbsp, SRGR2, config->srgr2);
0188     MCBSP_WRITE(mcbsp, SRGR1, config->srgr1);
0189     MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
0190     MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
0191     MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
0192     if (mcbsp->pdata->has_ccr) {
0193         MCBSP_WRITE(mcbsp, XCCR, config->xccr);
0194         MCBSP_WRITE(mcbsp, RCCR, config->rccr);
0195     }
0196     /* Enable wakeup behavior */
0197     if (mcbsp->pdata->has_wakeup)
0198         MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
0199 
0200     /* Enable TX/RX sync error interrupts by default */
0201     if (mcbsp->irq)
0202         MCBSP_WRITE(mcbsp, IRQEN, RSYNCERREN | XSYNCERREN |
0203                 RUNDFLEN | ROVFLEN | XUNDFLEN | XOVFLEN);
0204 }
0205 
0206 /**
0207  * omap_mcbsp_dma_reg_params - returns the address of mcbsp data register
0208  * @mcbsp: omap_mcbsp struct for the McBSP instance
0209  * @stream: Stream direction (playback/capture)
0210  *
0211  * Returns the address of mcbsp data transmit register or data receive register
0212  * to be used by DMA for transferring/receiving data
0213  */
0214 static int omap_mcbsp_dma_reg_params(struct omap_mcbsp *mcbsp,
0215                      unsigned int stream)
0216 {
0217     int data_reg;
0218 
0219     if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
0220         if (mcbsp->pdata->reg_size == 2)
0221             data_reg = OMAP_MCBSP_REG_DXR1;
0222         else
0223             data_reg = OMAP_MCBSP_REG_DXR;
0224     } else {
0225         if (mcbsp->pdata->reg_size == 2)
0226             data_reg = OMAP_MCBSP_REG_DRR1;
0227         else
0228             data_reg = OMAP_MCBSP_REG_DRR;
0229     }
0230 
0231     return mcbsp->phys_dma_base + data_reg * mcbsp->pdata->reg_step;
0232 }
0233 
0234 /*
0235  * omap_mcbsp_set_rx_threshold configures the transmit threshold in words.
0236  * The threshold parameter is 1 based, and it is converted (threshold - 1)
0237  * for the THRSH2 register.
0238  */
0239 static void omap_mcbsp_set_tx_threshold(struct omap_mcbsp *mcbsp, u16 threshold)
0240 {
0241     if (threshold && threshold <= mcbsp->max_tx_thres)
0242         MCBSP_WRITE(mcbsp, THRSH2, threshold - 1);
0243 }
0244 
0245 /*
0246  * omap_mcbsp_set_rx_threshold configures the receive threshold in words.
0247  * The threshold parameter is 1 based, and it is converted (threshold - 1)
0248  * for the THRSH1 register.
0249  */
0250 static void omap_mcbsp_set_rx_threshold(struct omap_mcbsp *mcbsp, u16 threshold)
0251 {
0252     if (threshold && threshold <= mcbsp->max_rx_thres)
0253         MCBSP_WRITE(mcbsp, THRSH1, threshold - 1);
0254 }
0255 
0256 /*
0257  * omap_mcbsp_get_tx_delay returns the number of used slots in the McBSP FIFO
0258  */
0259 static u16 omap_mcbsp_get_tx_delay(struct omap_mcbsp *mcbsp)
0260 {
0261     u16 buffstat;
0262 
0263     /* Returns the number of free locations in the buffer */
0264     buffstat = MCBSP_READ(mcbsp, XBUFFSTAT);
0265 
0266     /* Number of slots are different in McBSP ports */
0267     return mcbsp->pdata->buffer_size - buffstat;
0268 }
0269 
0270 /*
0271  * omap_mcbsp_get_rx_delay returns the number of free slots in the McBSP FIFO
0272  * to reach the threshold value (when the DMA will be triggered to read it)
0273  */
0274 static u16 omap_mcbsp_get_rx_delay(struct omap_mcbsp *mcbsp)
0275 {
0276     u16 buffstat, threshold;
0277 
0278     /* Returns the number of used locations in the buffer */
0279     buffstat = MCBSP_READ(mcbsp, RBUFFSTAT);
0280     /* RX threshold */
0281     threshold = MCBSP_READ(mcbsp, THRSH1);
0282 
0283     /* Return the number of location till we reach the threshold limit */
0284     if (threshold <= buffstat)
0285         return 0;
0286     else
0287         return threshold - buffstat;
0288 }
0289 
0290 static int omap_mcbsp_request(struct omap_mcbsp *mcbsp)
0291 {
0292     void *reg_cache;
0293     int err;
0294 
0295     reg_cache = kzalloc(mcbsp->reg_cache_size, GFP_KERNEL);
0296     if (!reg_cache)
0297         return -ENOMEM;
0298 
0299     spin_lock(&mcbsp->lock);
0300     if (!mcbsp->free) {
0301         dev_err(mcbsp->dev, "McBSP%d is currently in use\n", mcbsp->id);
0302         err = -EBUSY;
0303         goto err_kfree;
0304     }
0305 
0306     mcbsp->free = false;
0307     mcbsp->reg_cache = reg_cache;
0308     spin_unlock(&mcbsp->lock);
0309 
0310     if(mcbsp->pdata->ops && mcbsp->pdata->ops->request)
0311         mcbsp->pdata->ops->request(mcbsp->id - 1);
0312 
0313     /*
0314      * Make sure that transmitter, receiver and sample-rate generator are
0315      * not running before activating IRQs.
0316      */
0317     MCBSP_WRITE(mcbsp, SPCR1, 0);
0318     MCBSP_WRITE(mcbsp, SPCR2, 0);
0319 
0320     if (mcbsp->irq) {
0321         err = request_irq(mcbsp->irq, omap_mcbsp_irq_handler, 0,
0322                   "McBSP", (void *)mcbsp);
0323         if (err != 0) {
0324             dev_err(mcbsp->dev, "Unable to request IRQ\n");
0325             goto err_clk_disable;
0326         }
0327     } else {
0328         err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler, 0,
0329                   "McBSP TX", (void *)mcbsp);
0330         if (err != 0) {
0331             dev_err(mcbsp->dev, "Unable to request TX IRQ\n");
0332             goto err_clk_disable;
0333         }
0334 
0335         err = request_irq(mcbsp->rx_irq, omap_mcbsp_rx_irq_handler, 0,
0336                   "McBSP RX", (void *)mcbsp);
0337         if (err != 0) {
0338             dev_err(mcbsp->dev, "Unable to request RX IRQ\n");
0339             goto err_free_irq;
0340         }
0341     }
0342 
0343     return 0;
0344 err_free_irq:
0345     free_irq(mcbsp->tx_irq, (void *)mcbsp);
0346 err_clk_disable:
0347     if(mcbsp->pdata->ops && mcbsp->pdata->ops->free)
0348         mcbsp->pdata->ops->free(mcbsp->id - 1);
0349 
0350     /* Disable wakeup behavior */
0351     if (mcbsp->pdata->has_wakeup)
0352         MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
0353 
0354     spin_lock(&mcbsp->lock);
0355     mcbsp->free = true;
0356     mcbsp->reg_cache = NULL;
0357 err_kfree:
0358     spin_unlock(&mcbsp->lock);
0359     kfree(reg_cache);
0360 
0361     return err;
0362 }
0363 
0364 static void omap_mcbsp_free(struct omap_mcbsp *mcbsp)
0365 {
0366     void *reg_cache;
0367 
0368     if(mcbsp->pdata->ops && mcbsp->pdata->ops->free)
0369         mcbsp->pdata->ops->free(mcbsp->id - 1);
0370 
0371     /* Disable wakeup behavior */
0372     if (mcbsp->pdata->has_wakeup)
0373         MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
0374 
0375     /* Disable interrupt requests */
0376     if (mcbsp->irq) {
0377         MCBSP_WRITE(mcbsp, IRQEN, 0);
0378 
0379         free_irq(mcbsp->irq, (void *)mcbsp);
0380     } else {
0381         free_irq(mcbsp->rx_irq, (void *)mcbsp);
0382         free_irq(mcbsp->tx_irq, (void *)mcbsp);
0383     }
0384 
0385     reg_cache = mcbsp->reg_cache;
0386 
0387     /*
0388      * Select CLKS source from internal source unconditionally before
0389      * marking the McBSP port as free.
0390      * If the external clock source via MCBSP_CLKS pin has been selected the
0391      * system will refuse to enter idle if the CLKS pin source is not reset
0392      * back to internal source.
0393      */
0394     if (!mcbsp_omap1())
0395         omap2_mcbsp_set_clks_src(mcbsp, MCBSP_CLKS_PRCM_SRC);
0396 
0397     spin_lock(&mcbsp->lock);
0398     if (mcbsp->free)
0399         dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
0400     else
0401         mcbsp->free = true;
0402     mcbsp->reg_cache = NULL;
0403     spin_unlock(&mcbsp->lock);
0404 
0405     kfree(reg_cache);
0406 }
0407 
0408 /*
0409  * Here we start the McBSP, by enabling transmitter, receiver or both.
0410  * If no transmitter or receiver is active prior calling, then sample-rate
0411  * generator and frame sync are started.
0412  */
0413 static void omap_mcbsp_start(struct omap_mcbsp *mcbsp, int stream)
0414 {
0415     int tx = (stream == SNDRV_PCM_STREAM_PLAYBACK);
0416     int rx = !tx;
0417     int enable_srg = 0;
0418     u16 w;
0419 
0420     if (mcbsp->st_data)
0421         omap_mcbsp_st_start(mcbsp);
0422 
0423     /* Only enable SRG, if McBSP is master */
0424     w = MCBSP_READ_CACHE(mcbsp, PCR0);
0425     if (w & (FSXM | FSRM | CLKXM | CLKRM))
0426         enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
0427                 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
0428 
0429     if (enable_srg) {
0430         /* Start the sample generator */
0431         w = MCBSP_READ_CACHE(mcbsp, SPCR2);
0432         MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
0433     }
0434 
0435     /* Enable transmitter and receiver */
0436     tx &= 1;
0437     w = MCBSP_READ_CACHE(mcbsp, SPCR2);
0438     MCBSP_WRITE(mcbsp, SPCR2, w | tx);
0439 
0440     rx &= 1;
0441     w = MCBSP_READ_CACHE(mcbsp, SPCR1);
0442     MCBSP_WRITE(mcbsp, SPCR1, w | rx);
0443 
0444     /*
0445      * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
0446      * REVISIT: 100us may give enough time for two CLKSRG, however
0447      * due to some unknown PM related, clock gating etc. reason it
0448      * is now at 500us.
0449      */
0450     udelay(500);
0451 
0452     if (enable_srg) {
0453         /* Start frame sync */
0454         w = MCBSP_READ_CACHE(mcbsp, SPCR2);
0455         MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
0456     }
0457 
0458     if (mcbsp->pdata->has_ccr) {
0459         /* Release the transmitter and receiver */
0460         w = MCBSP_READ_CACHE(mcbsp, XCCR);
0461         w &= ~(tx ? XDISABLE : 0);
0462         MCBSP_WRITE(mcbsp, XCCR, w);
0463         w = MCBSP_READ_CACHE(mcbsp, RCCR);
0464         w &= ~(rx ? RDISABLE : 0);
0465         MCBSP_WRITE(mcbsp, RCCR, w);
0466     }
0467 
0468     /* Dump McBSP Regs */
0469     omap_mcbsp_dump_reg(mcbsp);
0470 }
0471 
0472 static void omap_mcbsp_stop(struct omap_mcbsp *mcbsp, int stream)
0473 {
0474     int tx = (stream == SNDRV_PCM_STREAM_PLAYBACK);
0475     int rx = !tx;
0476     int idle;
0477     u16 w;
0478 
0479     /* Reset transmitter */
0480     tx &= 1;
0481     if (mcbsp->pdata->has_ccr) {
0482         w = MCBSP_READ_CACHE(mcbsp, XCCR);
0483         w |= (tx ? XDISABLE : 0);
0484         MCBSP_WRITE(mcbsp, XCCR, w);
0485     }
0486     w = MCBSP_READ_CACHE(mcbsp, SPCR2);
0487     MCBSP_WRITE(mcbsp, SPCR2, w & ~tx);
0488 
0489     /* Reset receiver */
0490     rx &= 1;
0491     if (mcbsp->pdata->has_ccr) {
0492         w = MCBSP_READ_CACHE(mcbsp, RCCR);
0493         w |= (rx ? RDISABLE : 0);
0494         MCBSP_WRITE(mcbsp, RCCR, w);
0495     }
0496     w = MCBSP_READ_CACHE(mcbsp, SPCR1);
0497     MCBSP_WRITE(mcbsp, SPCR1, w & ~rx);
0498 
0499     idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
0500             MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
0501 
0502     if (idle) {
0503         /* Reset the sample rate generator */
0504         w = MCBSP_READ_CACHE(mcbsp, SPCR2);
0505         MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
0506     }
0507 
0508     if (mcbsp->st_data)
0509         omap_mcbsp_st_stop(mcbsp);
0510 }
0511 
0512 #define max_thres(m)            (mcbsp->pdata->buffer_size)
0513 #define valid_threshold(m, val)     ((val) <= max_thres(m))
0514 #define THRESHOLD_PROP_BUILDER(prop)                    \
0515 static ssize_t prop##_show(struct device *dev,              \
0516             struct device_attribute *attr, char *buf)   \
0517 {                                   \
0518     struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);        \
0519                                     \
0520     return sprintf(buf, "%u\n", mcbsp->prop);           \
0521 }                                   \
0522                                     \
0523 static ssize_t prop##_store(struct device *dev,             \
0524                 struct device_attribute *attr,      \
0525                 const char *buf, size_t size)       \
0526 {                                   \
0527     struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);        \
0528     unsigned long val;                      \
0529     int status;                         \
0530                                     \
0531     status = kstrtoul(buf, 0, &val);                \
0532     if (status)                         \
0533         return status;                      \
0534                                     \
0535     if (!valid_threshold(mcbsp, val))               \
0536         return -EDOM;                       \
0537                                     \
0538     mcbsp->prop = val;                      \
0539     return size;                            \
0540 }                                   \
0541                                     \
0542 static DEVICE_ATTR_RW(prop)
0543 
0544 THRESHOLD_PROP_BUILDER(max_tx_thres);
0545 THRESHOLD_PROP_BUILDER(max_rx_thres);
0546 
0547 static const char * const dma_op_modes[] = {
0548     "element", "threshold",
0549 };
0550 
0551 static ssize_t dma_op_mode_show(struct device *dev,
0552                 struct device_attribute *attr, char *buf)
0553 {
0554     struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
0555     int dma_op_mode, i = 0;
0556     ssize_t len = 0;
0557     const char * const *s;
0558 
0559     dma_op_mode = mcbsp->dma_op_mode;
0560 
0561     for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
0562         if (dma_op_mode == i)
0563             len += sprintf(buf + len, "[%s] ", *s);
0564         else
0565             len += sprintf(buf + len, "%s ", *s);
0566     }
0567     len += sprintf(buf + len, "\n");
0568 
0569     return len;
0570 }
0571 
0572 static ssize_t dma_op_mode_store(struct device *dev,
0573                  struct device_attribute *attr, const char *buf,
0574                  size_t size)
0575 {
0576     struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
0577     int i;
0578 
0579     i = sysfs_match_string(dma_op_modes, buf);
0580     if (i < 0)
0581         return i;
0582 
0583     spin_lock_irq(&mcbsp->lock);
0584     if (!mcbsp->free) {
0585         size = -EBUSY;
0586         goto unlock;
0587     }
0588     mcbsp->dma_op_mode = i;
0589 
0590 unlock:
0591     spin_unlock_irq(&mcbsp->lock);
0592 
0593     return size;
0594 }
0595 
0596 static DEVICE_ATTR_RW(dma_op_mode);
0597 
0598 static const struct attribute *additional_attrs[] = {
0599     &dev_attr_max_tx_thres.attr,
0600     &dev_attr_max_rx_thres.attr,
0601     &dev_attr_dma_op_mode.attr,
0602     NULL,
0603 };
0604 
0605 static const struct attribute_group additional_attr_group = {
0606     .attrs = (struct attribute **)additional_attrs,
0607 };
0608 
0609 /*
0610  * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
0611  * 730 has only 2 McBSP, and both of them are MPU peripherals.
0612  */
0613 static int omap_mcbsp_init(struct platform_device *pdev)
0614 {
0615     struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
0616     struct resource *res;
0617     int ret = 0;
0618 
0619     spin_lock_init(&mcbsp->lock);
0620     mcbsp->free = true;
0621 
0622     res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
0623     if (!res)
0624         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0625 
0626     mcbsp->io_base = devm_ioremap_resource(&pdev->dev, res);
0627     if (IS_ERR(mcbsp->io_base))
0628         return PTR_ERR(mcbsp->io_base);
0629 
0630     mcbsp->phys_base = res->start;
0631     mcbsp->reg_cache_size = resource_size(res);
0632 
0633     res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
0634     if (!res)
0635         mcbsp->phys_dma_base = mcbsp->phys_base;
0636     else
0637         mcbsp->phys_dma_base = res->start;
0638 
0639     /*
0640      * OMAP1, 2 uses two interrupt lines: TX, RX
0641      * OMAP2430, OMAP3 SoC have combined IRQ line as well.
0642      * OMAP4 and newer SoC only have the combined IRQ line.
0643      * Use the combined IRQ if available since it gives better debugging
0644      * possibilities.
0645      */
0646     mcbsp->irq = platform_get_irq_byname(pdev, "common");
0647     if (mcbsp->irq == -ENXIO) {
0648         mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx");
0649 
0650         if (mcbsp->tx_irq == -ENXIO) {
0651             mcbsp->irq = platform_get_irq(pdev, 0);
0652             mcbsp->tx_irq = 0;
0653         } else {
0654             mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx");
0655             mcbsp->irq = 0;
0656         }
0657     }
0658 
0659     if (!pdev->dev.of_node) {
0660         res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
0661         if (!res) {
0662             dev_err(&pdev->dev, "invalid tx DMA channel\n");
0663             return -ENODEV;
0664         }
0665         mcbsp->dma_req[0] = res->start;
0666         mcbsp->dma_data[0].filter_data = &mcbsp->dma_req[0];
0667 
0668         res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
0669         if (!res) {
0670             dev_err(&pdev->dev, "invalid rx DMA channel\n");
0671             return -ENODEV;
0672         }
0673         mcbsp->dma_req[1] = res->start;
0674         mcbsp->dma_data[1].filter_data = &mcbsp->dma_req[1];
0675     } else {
0676         mcbsp->dma_data[0].filter_data = "tx";
0677         mcbsp->dma_data[1].filter_data = "rx";
0678     }
0679 
0680     mcbsp->dma_data[0].addr = omap_mcbsp_dma_reg_params(mcbsp,
0681                         SNDRV_PCM_STREAM_PLAYBACK);
0682     mcbsp->dma_data[1].addr = omap_mcbsp_dma_reg_params(mcbsp,
0683                         SNDRV_PCM_STREAM_CAPTURE);
0684 
0685     mcbsp->fclk = devm_clk_get(&pdev->dev, "fck");
0686     if (IS_ERR(mcbsp->fclk)) {
0687         ret = PTR_ERR(mcbsp->fclk);
0688         dev_err(mcbsp->dev, "unable to get fck: %d\n", ret);
0689         return ret;
0690     }
0691 
0692     mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
0693     if (mcbsp->pdata->buffer_size) {
0694         /*
0695          * Initially configure the maximum thresholds to a safe value.
0696          * The McBSP FIFO usage with these values should not go under
0697          * 16 locations.
0698          * If the whole FIFO without safety buffer is used, than there
0699          * is a possibility that the DMA will be not able to push the
0700          * new data on time, causing channel shifts in runtime.
0701          */
0702         mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10;
0703         mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10;
0704 
0705         ret = devm_device_add_group(mcbsp->dev, &additional_attr_group);
0706         if (ret) {
0707             dev_err(mcbsp->dev,
0708                 "Unable to create additional controls\n");
0709             return ret;
0710         }
0711     }
0712 
0713     return omap_mcbsp_st_init(pdev);
0714 }
0715 
0716 /*
0717  * Stream DMA parameters. DMA request line and port address are set runtime
0718  * since they are different between OMAP1 and later OMAPs
0719  */
0720 static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream,
0721         unsigned int packet_size)
0722 {
0723     struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
0724     struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
0725     struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
0726     int words;
0727 
0728     /* No need to proceed further if McBSP does not have FIFO */
0729     if (mcbsp->pdata->buffer_size == 0)
0730         return;
0731 
0732     /*
0733      * Configure McBSP threshold based on either:
0734      * packet_size, when the sDMA is in packet mode, or based on the
0735      * period size in THRESHOLD mode, otherwise use McBSP threshold = 1
0736      * for mono streams.
0737      */
0738     if (packet_size)
0739         words = packet_size;
0740     else
0741         words = 1;
0742 
0743     /* Configure McBSP internal buffer usage */
0744     if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
0745         omap_mcbsp_set_tx_threshold(mcbsp, words);
0746     else
0747         omap_mcbsp_set_rx_threshold(mcbsp, words);
0748 }
0749 
0750 static int omap_mcbsp_hwrule_min_buffersize(struct snd_pcm_hw_params *params,
0751                     struct snd_pcm_hw_rule *rule)
0752 {
0753     struct snd_interval *buffer_size = hw_param_interval(params,
0754                     SNDRV_PCM_HW_PARAM_BUFFER_SIZE);
0755     struct snd_interval *channels = hw_param_interval(params,
0756                     SNDRV_PCM_HW_PARAM_CHANNELS);
0757     struct omap_mcbsp *mcbsp = rule->private;
0758     struct snd_interval frames;
0759     int size;
0760 
0761     snd_interval_any(&frames);
0762     size = mcbsp->pdata->buffer_size;
0763 
0764     frames.min = size / channels->min;
0765     frames.integer = 1;
0766     return snd_interval_refine(buffer_size, &frames);
0767 }
0768 
0769 static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
0770                   struct snd_soc_dai *cpu_dai)
0771 {
0772     struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
0773     int err = 0;
0774 
0775     if (!snd_soc_dai_active(cpu_dai))
0776         err = omap_mcbsp_request(mcbsp);
0777 
0778     /*
0779      * OMAP3 McBSP FIFO is word structured.
0780      * McBSP2 has 1024 + 256 = 1280 word long buffer,
0781      * McBSP1,3,4,5 has 128 word long buffer
0782      * This means that the size of the FIFO depends on the sample format.
0783      * For example on McBSP3:
0784      * 16bit samples: size is 128 * 2 = 256 bytes
0785      * 32bit samples: size is 128 * 4 = 512 bytes
0786      * It is simpler to place constraint for buffer and period based on
0787      * channels.
0788      * McBSP3 as example again (16 or 32 bit samples):
0789      * 1 channel (mono): size is 128 frames (128 words)
0790      * 2 channels (stereo): size is 128 / 2 = 64 frames (2 * 64 words)
0791      * 4 channels: size is 128 / 4 = 32 frames (4 * 32 words)
0792      */
0793     if (mcbsp->pdata->buffer_size) {
0794         /*
0795         * Rule for the buffer size. We should not allow
0796         * smaller buffer than the FIFO size to avoid underruns.
0797         * This applies only for the playback stream.
0798         */
0799         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
0800             snd_pcm_hw_rule_add(substream->runtime, 0,
0801                         SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
0802                         omap_mcbsp_hwrule_min_buffersize,
0803                         mcbsp,
0804                         SNDRV_PCM_HW_PARAM_CHANNELS, -1);
0805 
0806         /* Make sure, that the period size is always even */
0807         snd_pcm_hw_constraint_step(substream->runtime, 0,
0808                        SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
0809     }
0810 
0811     return err;
0812 }
0813 
0814 static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
0815                     struct snd_soc_dai *cpu_dai)
0816 {
0817     struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
0818     int tx = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
0819     int stream1 = tx ? SNDRV_PCM_STREAM_PLAYBACK : SNDRV_PCM_STREAM_CAPTURE;
0820     int stream2 = tx ? SNDRV_PCM_STREAM_CAPTURE : SNDRV_PCM_STREAM_PLAYBACK;
0821 
0822     if (mcbsp->latency[stream2])
0823         cpu_latency_qos_update_request(&mcbsp->pm_qos_req,
0824                            mcbsp->latency[stream2]);
0825     else if (mcbsp->latency[stream1])
0826         cpu_latency_qos_remove_request(&mcbsp->pm_qos_req);
0827 
0828     mcbsp->latency[stream1] = 0;
0829 
0830     if (!snd_soc_dai_active(cpu_dai)) {
0831         omap_mcbsp_free(mcbsp);
0832         mcbsp->configured = 0;
0833     }
0834 }
0835 
0836 static int omap_mcbsp_dai_prepare(struct snd_pcm_substream *substream,
0837                   struct snd_soc_dai *cpu_dai)
0838 {
0839     struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
0840     struct pm_qos_request *pm_qos_req = &mcbsp->pm_qos_req;
0841     int tx = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
0842     int stream1 = tx ? SNDRV_PCM_STREAM_PLAYBACK : SNDRV_PCM_STREAM_CAPTURE;
0843     int stream2 = tx ? SNDRV_PCM_STREAM_CAPTURE : SNDRV_PCM_STREAM_PLAYBACK;
0844     int latency = mcbsp->latency[stream2];
0845 
0846     /* Prevent omap hardware from hitting off between FIFO fills */
0847     if (!latency || mcbsp->latency[stream1] < latency)
0848         latency = mcbsp->latency[stream1];
0849 
0850     if (cpu_latency_qos_request_active(pm_qos_req))
0851         cpu_latency_qos_update_request(pm_qos_req, latency);
0852     else if (latency)
0853         cpu_latency_qos_add_request(pm_qos_req, latency);
0854 
0855     return 0;
0856 }
0857 
0858 static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
0859                   struct snd_soc_dai *cpu_dai)
0860 {
0861     struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
0862 
0863     switch (cmd) {
0864     case SNDRV_PCM_TRIGGER_START:
0865     case SNDRV_PCM_TRIGGER_RESUME:
0866     case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
0867         mcbsp->active++;
0868         omap_mcbsp_start(mcbsp, substream->stream);
0869         break;
0870 
0871     case SNDRV_PCM_TRIGGER_STOP:
0872     case SNDRV_PCM_TRIGGER_SUSPEND:
0873     case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
0874         omap_mcbsp_stop(mcbsp, substream->stream);
0875         mcbsp->active--;
0876         break;
0877     default:
0878         return -EINVAL;
0879     }
0880 
0881     return 0;
0882 }
0883 
0884 static snd_pcm_sframes_t omap_mcbsp_dai_delay(
0885             struct snd_pcm_substream *substream,
0886             struct snd_soc_dai *dai)
0887 {
0888     struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
0889     struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
0890     struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
0891     u16 fifo_use;
0892     snd_pcm_sframes_t delay;
0893 
0894     /* No need to proceed further if McBSP does not have FIFO */
0895     if (mcbsp->pdata->buffer_size == 0)
0896         return 0;
0897 
0898     if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
0899         fifo_use = omap_mcbsp_get_tx_delay(mcbsp);
0900     else
0901         fifo_use = omap_mcbsp_get_rx_delay(mcbsp);
0902 
0903     /*
0904      * Divide the used locations with the channel count to get the
0905      * FIFO usage in samples (don't care about partial samples in the
0906      * buffer).
0907      */
0908     delay = fifo_use / substream->runtime->channels;
0909 
0910     return delay;
0911 }
0912 
0913 static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
0914                     struct snd_pcm_hw_params *params,
0915                     struct snd_soc_dai *cpu_dai)
0916 {
0917     struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
0918     struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
0919     struct snd_dmaengine_dai_dma_data *dma_data;
0920     int wlen, channels, wpf;
0921     int pkt_size = 0;
0922     unsigned int format, div, framesize, master;
0923     unsigned int buffer_size = mcbsp->pdata->buffer_size;
0924 
0925     dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream);
0926     channels = params_channels(params);
0927 
0928     switch (params_format(params)) {
0929     case SNDRV_PCM_FORMAT_S16_LE:
0930         wlen = 16;
0931         break;
0932     case SNDRV_PCM_FORMAT_S32_LE:
0933         wlen = 32;
0934         break;
0935     default:
0936         return -EINVAL;
0937     }
0938     if (buffer_size) {
0939         int latency;
0940 
0941         if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
0942             int period_words, max_thrsh;
0943             int divider = 0;
0944 
0945             period_words = params_period_bytes(params) / (wlen / 8);
0946             if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
0947                 max_thrsh = mcbsp->max_tx_thres;
0948             else
0949                 max_thrsh = mcbsp->max_rx_thres;
0950             /*
0951              * Use sDMA packet mode if McBSP is in threshold mode:
0952              * If period words less than the FIFO size the packet
0953              * size is set to the number of period words, otherwise
0954              * Look for the biggest threshold value which divides
0955              * the period size evenly.
0956              */
0957             divider = period_words / max_thrsh;
0958             if (period_words % max_thrsh)
0959                 divider++;
0960             while (period_words % divider &&
0961                 divider < period_words)
0962                 divider++;
0963             if (divider == period_words)
0964                 return -EINVAL;
0965 
0966             pkt_size = period_words / divider;
0967         } else if (channels > 1) {
0968             /* Use packet mode for non mono streams */
0969             pkt_size = channels;
0970         }
0971 
0972         latency = (buffer_size - pkt_size) / channels;
0973         latency = latency * USEC_PER_SEC /
0974               (params->rate_num / params->rate_den);
0975         mcbsp->latency[substream->stream] = latency;
0976 
0977         omap_mcbsp_set_threshold(substream, pkt_size);
0978     }
0979 
0980     dma_data->maxburst = pkt_size;
0981 
0982     if (mcbsp->configured) {
0983         /* McBSP already configured by another stream */
0984         return 0;
0985     }
0986 
0987     regs->rcr2  &= ~(RPHASE | RFRLEN2(0x7f) | RWDLEN2(7));
0988     regs->xcr2  &= ~(RPHASE | XFRLEN2(0x7f) | XWDLEN2(7));
0989     regs->rcr1  &= ~(RFRLEN1(0x7f) | RWDLEN1(7));
0990     regs->xcr1  &= ~(XFRLEN1(0x7f) | XWDLEN1(7));
0991     format = mcbsp->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
0992     wpf = channels;
0993     if (channels == 2 && (format == SND_SOC_DAIFMT_I2S ||
0994                   format == SND_SOC_DAIFMT_LEFT_J)) {
0995         /* Use dual-phase frames */
0996         regs->rcr2  |= RPHASE;
0997         regs->xcr2  |= XPHASE;
0998         /* Set 1 word per (McBSP) frame for phase1 and phase2 */
0999         wpf--;
1000         regs->rcr2  |= RFRLEN2(wpf - 1);
1001         regs->xcr2  |= XFRLEN2(wpf - 1);
1002     }
1003 
1004     regs->rcr1  |= RFRLEN1(wpf - 1);
1005     regs->xcr1  |= XFRLEN1(wpf - 1);
1006 
1007     switch (params_format(params)) {
1008     case SNDRV_PCM_FORMAT_S16_LE:
1009         /* Set word lengths */
1010         regs->rcr2  |= RWDLEN2(OMAP_MCBSP_WORD_16);
1011         regs->rcr1  |= RWDLEN1(OMAP_MCBSP_WORD_16);
1012         regs->xcr2  |= XWDLEN2(OMAP_MCBSP_WORD_16);
1013         regs->xcr1  |= XWDLEN1(OMAP_MCBSP_WORD_16);
1014         break;
1015     case SNDRV_PCM_FORMAT_S32_LE:
1016         /* Set word lengths */
1017         regs->rcr2  |= RWDLEN2(OMAP_MCBSP_WORD_32);
1018         regs->rcr1  |= RWDLEN1(OMAP_MCBSP_WORD_32);
1019         regs->xcr2  |= XWDLEN2(OMAP_MCBSP_WORD_32);
1020         regs->xcr1  |= XWDLEN1(OMAP_MCBSP_WORD_32);
1021         break;
1022     default:
1023         /* Unsupported PCM format */
1024         return -EINVAL;
1025     }
1026 
1027     /* In McBSP master modes, FRAME (i.e. sample rate) is generated
1028      * by _counting_ BCLKs. Calculate frame size in BCLKs */
1029     master = mcbsp->fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK;
1030     if (master == SND_SOC_DAIFMT_BP_FP) {
1031         div = mcbsp->clk_div ? mcbsp->clk_div : 1;
1032         framesize = (mcbsp->in_freq / div) / params_rate(params);
1033 
1034         if (framesize < wlen * channels) {
1035             printk(KERN_ERR "%s: not enough bandwidth for desired rate and "
1036                     "channels\n", __func__);
1037             return -EINVAL;
1038         }
1039     } else
1040         framesize = wlen * channels;
1041 
1042     /* Set FS period and length in terms of bit clock periods */
1043     regs->srgr2 &= ~FPER(0xfff);
1044     regs->srgr1 &= ~FWID(0xff);
1045     switch (format) {
1046     case SND_SOC_DAIFMT_I2S:
1047     case SND_SOC_DAIFMT_LEFT_J:
1048         regs->srgr2 |= FPER(framesize - 1);
1049         regs->srgr1 |= FWID((framesize >> 1) - 1);
1050         break;
1051     case SND_SOC_DAIFMT_DSP_A:
1052     case SND_SOC_DAIFMT_DSP_B:
1053         regs->srgr2 |= FPER(framesize - 1);
1054         regs->srgr1 |= FWID(0);
1055         break;
1056     }
1057 
1058     omap_mcbsp_config(mcbsp, &mcbsp->cfg_regs);
1059     mcbsp->wlen = wlen;
1060     mcbsp->configured = 1;
1061 
1062     return 0;
1063 }
1064 
1065 /*
1066  * This must be called before _set_clkdiv and _set_sysclk since McBSP register
1067  * cache is initialized here
1068  */
1069 static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
1070                       unsigned int fmt)
1071 {
1072     struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
1073     struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
1074     bool inv_fs = false;
1075 
1076     if (mcbsp->configured)
1077         return 0;
1078 
1079     mcbsp->fmt = fmt;
1080     memset(regs, 0, sizeof(*regs));
1081     /* Generic McBSP register settings */
1082     regs->spcr2 |= XINTM(3) | FREE;
1083     regs->spcr1 |= RINTM(3);
1084     /* RFIG and XFIG are not defined in 2430 and on OMAP3+ */
1085     if (!mcbsp->pdata->has_ccr) {
1086         regs->rcr2  |= RFIG;
1087         regs->xcr2  |= XFIG;
1088     }
1089 
1090     /* Configure XCCR/RCCR only for revisions which have ccr registers */
1091     if (mcbsp->pdata->has_ccr) {
1092         regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE;
1093         regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE;
1094     }
1095 
1096     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1097     case SND_SOC_DAIFMT_I2S:
1098         /* 1-bit data delay */
1099         regs->rcr2  |= RDATDLY(1);
1100         regs->xcr2  |= XDATDLY(1);
1101         break;
1102     case SND_SOC_DAIFMT_LEFT_J:
1103         /* 0-bit data delay */
1104         regs->rcr2  |= RDATDLY(0);
1105         regs->xcr2  |= XDATDLY(0);
1106         regs->spcr1 |= RJUST(2);
1107         /* Invert FS polarity configuration */
1108         inv_fs = true;
1109         break;
1110     case SND_SOC_DAIFMT_DSP_A:
1111         /* 1-bit data delay */
1112         regs->rcr2      |= RDATDLY(1);
1113         regs->xcr2      |= XDATDLY(1);
1114         /* Invert FS polarity configuration */
1115         inv_fs = true;
1116         break;
1117     case SND_SOC_DAIFMT_DSP_B:
1118         /* 0-bit data delay */
1119         regs->rcr2      |= RDATDLY(0);
1120         regs->xcr2      |= XDATDLY(0);
1121         /* Invert FS polarity configuration */
1122         inv_fs = true;
1123         break;
1124     default:
1125         /* Unsupported data format */
1126         return -EINVAL;
1127     }
1128 
1129     switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
1130     case SND_SOC_DAIFMT_BP_FP:
1131         /* McBSP master. Set FS and bit clocks as outputs */
1132         regs->pcr0  |= FSXM | FSRM |
1133                    CLKXM | CLKRM;
1134         /* Sample rate generator drives the FS */
1135         regs->srgr2 |= FSGM;
1136         break;
1137     case SND_SOC_DAIFMT_BC_FP:
1138         /* McBSP slave. FS clock as output */
1139         regs->srgr2 |= FSGM;
1140         regs->pcr0  |= FSXM | FSRM;
1141         break;
1142     case SND_SOC_DAIFMT_BC_FC:
1143         /* McBSP slave */
1144         break;
1145     default:
1146         /* Unsupported master/slave configuration */
1147         return -EINVAL;
1148     }
1149 
1150     /* Set bit clock (CLKX/CLKR) and FS polarities */
1151     switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1152     case SND_SOC_DAIFMT_NB_NF:
1153         /*
1154          * Normal BCLK + FS.
1155          * FS active low. TX data driven on falling edge of bit clock
1156          * and RX data sampled on rising edge of bit clock.
1157          */
1158         regs->pcr0  |= FSXP | FSRP |
1159                    CLKXP | CLKRP;
1160         break;
1161     case SND_SOC_DAIFMT_NB_IF:
1162         regs->pcr0  |= CLKXP | CLKRP;
1163         break;
1164     case SND_SOC_DAIFMT_IB_NF:
1165         regs->pcr0  |= FSXP | FSRP;
1166         break;
1167     case SND_SOC_DAIFMT_IB_IF:
1168         break;
1169     default:
1170         return -EINVAL;
1171     }
1172     if (inv_fs)
1173         regs->pcr0 ^= FSXP | FSRP;
1174 
1175     return 0;
1176 }
1177 
1178 static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
1179                      int div_id, int div)
1180 {
1181     struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
1182     struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
1183 
1184     if (div_id != OMAP_MCBSP_CLKGDV)
1185         return -ENODEV;
1186 
1187     mcbsp->clk_div = div;
1188     regs->srgr1 &= ~CLKGDV(0xff);
1189     regs->srgr1 |= CLKGDV(div - 1);
1190 
1191     return 0;
1192 }
1193 
1194 static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
1195                      int clk_id, unsigned int freq,
1196                      int dir)
1197 {
1198     struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
1199     struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
1200     int err = 0;
1201 
1202     if (mcbsp->active) {
1203         if (freq == mcbsp->in_freq)
1204             return 0;
1205         else
1206             return -EBUSY;
1207     }
1208 
1209     mcbsp->in_freq = freq;
1210     regs->srgr2 &= ~CLKSM;
1211     regs->pcr0 &= ~SCLKME;
1212 
1213     switch (clk_id) {
1214     case OMAP_MCBSP_SYSCLK_CLK:
1215         regs->srgr2 |= CLKSM;
1216         break;
1217     case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
1218         if (mcbsp_omap1()) {
1219             err = -EINVAL;
1220             break;
1221         }
1222         err = omap2_mcbsp_set_clks_src(mcbsp,
1223                            MCBSP_CLKS_PRCM_SRC);
1224         break;
1225     case OMAP_MCBSP_SYSCLK_CLKS_EXT:
1226         if (mcbsp_omap1()) {
1227             err = 0;
1228             break;
1229         }
1230         err = omap2_mcbsp_set_clks_src(mcbsp,
1231                            MCBSP_CLKS_PAD_SRC);
1232         break;
1233 
1234     case OMAP_MCBSP_SYSCLK_CLKX_EXT:
1235         regs->srgr2 |= CLKSM;
1236         regs->pcr0  |= SCLKME;
1237         /*
1238          * If McBSP is master but yet the CLKX/CLKR pin drives the SRG,
1239          * disable output on those pins. This enables to inject the
1240          * reference clock through CLKX/CLKR. For this to work
1241          * set_dai_sysclk() _needs_ to be called after set_dai_fmt().
1242          */
1243         regs->pcr0  &= ~CLKXM;
1244         break;
1245     case OMAP_MCBSP_SYSCLK_CLKR_EXT:
1246         regs->pcr0  |= SCLKME;
1247         /* Disable ouput on CLKR pin in master mode */
1248         regs->pcr0  &= ~CLKRM;
1249         break;
1250     default:
1251         err = -ENODEV;
1252     }
1253 
1254     return err;
1255 }
1256 
1257 static const struct snd_soc_dai_ops mcbsp_dai_ops = {
1258     .startup    = omap_mcbsp_dai_startup,
1259     .shutdown   = omap_mcbsp_dai_shutdown,
1260     .prepare    = omap_mcbsp_dai_prepare,
1261     .trigger    = omap_mcbsp_dai_trigger,
1262     .delay      = omap_mcbsp_dai_delay,
1263     .hw_params  = omap_mcbsp_dai_hw_params,
1264     .set_fmt    = omap_mcbsp_dai_set_dai_fmt,
1265     .set_clkdiv = omap_mcbsp_dai_set_clkdiv,
1266     .set_sysclk = omap_mcbsp_dai_set_dai_sysclk,
1267 };
1268 
1269 static int omap_mcbsp_probe(struct snd_soc_dai *dai)
1270 {
1271     struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai);
1272 
1273     pm_runtime_enable(mcbsp->dev);
1274 
1275     snd_soc_dai_init_dma_data(dai,
1276                   &mcbsp->dma_data[SNDRV_PCM_STREAM_PLAYBACK],
1277                   &mcbsp->dma_data[SNDRV_PCM_STREAM_CAPTURE]);
1278 
1279     return 0;
1280 }
1281 
1282 static int omap_mcbsp_remove(struct snd_soc_dai *dai)
1283 {
1284     struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai);
1285 
1286     pm_runtime_disable(mcbsp->dev);
1287 
1288     return 0;
1289 }
1290 
1291 static struct snd_soc_dai_driver omap_mcbsp_dai = {
1292     .probe = omap_mcbsp_probe,
1293     .remove = omap_mcbsp_remove,
1294     .playback = {
1295         .channels_min = 1,
1296         .channels_max = 16,
1297         .rates = OMAP_MCBSP_RATES,
1298         .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
1299     },
1300     .capture = {
1301         .channels_min = 1,
1302         .channels_max = 16,
1303         .rates = OMAP_MCBSP_RATES,
1304         .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
1305     },
1306     .ops = &mcbsp_dai_ops,
1307 };
1308 
1309 static const struct snd_soc_component_driver omap_mcbsp_component = {
1310     .name           = "omap-mcbsp",
1311     .legacy_dai_naming  = 1,
1312 };
1313 
1314 static struct omap_mcbsp_platform_data omap2420_pdata = {
1315     .reg_step = 4,
1316     .reg_size = 2,
1317 };
1318 
1319 static struct omap_mcbsp_platform_data omap2430_pdata = {
1320     .reg_step = 4,
1321     .reg_size = 4,
1322     .has_ccr = true,
1323 };
1324 
1325 static struct omap_mcbsp_platform_data omap3_pdata = {
1326     .reg_step = 4,
1327     .reg_size = 4,
1328     .has_ccr = true,
1329     .has_wakeup = true,
1330 };
1331 
1332 static struct omap_mcbsp_platform_data omap4_pdata = {
1333     .reg_step = 4,
1334     .reg_size = 4,
1335     .has_ccr = true,
1336     .has_wakeup = true,
1337 };
1338 
1339 static const struct of_device_id omap_mcbsp_of_match[] = {
1340     {
1341         .compatible = "ti,omap2420-mcbsp",
1342         .data = &omap2420_pdata,
1343     },
1344     {
1345         .compatible = "ti,omap2430-mcbsp",
1346         .data = &omap2430_pdata,
1347     },
1348     {
1349         .compatible = "ti,omap3-mcbsp",
1350         .data = &omap3_pdata,
1351     },
1352     {
1353         .compatible = "ti,omap4-mcbsp",
1354         .data = &omap4_pdata,
1355     },
1356     { },
1357 };
1358 MODULE_DEVICE_TABLE(of, omap_mcbsp_of_match);
1359 
1360 static int asoc_mcbsp_probe(struct platform_device *pdev)
1361 {
1362     struct omap_mcbsp_platform_data *pdata = dev_get_platdata(&pdev->dev);
1363     struct omap_mcbsp *mcbsp;
1364     const struct of_device_id *match;
1365     int ret;
1366 
1367     match = of_match_device(omap_mcbsp_of_match, &pdev->dev);
1368     if (match) {
1369         struct device_node *node = pdev->dev.of_node;
1370         struct omap_mcbsp_platform_data *pdata_quirk = pdata;
1371         int buffer_size;
1372 
1373         pdata = devm_kzalloc(&pdev->dev,
1374                      sizeof(struct omap_mcbsp_platform_data),
1375                      GFP_KERNEL);
1376         if (!pdata)
1377             return -ENOMEM;
1378 
1379         memcpy(pdata, match->data, sizeof(*pdata));
1380         if (!of_property_read_u32(node, "ti,buffer-size", &buffer_size))
1381             pdata->buffer_size = buffer_size;
1382         if (pdata_quirk)
1383             pdata->force_ick_on = pdata_quirk->force_ick_on;
1384     } else if (!pdata) {
1385         dev_err(&pdev->dev, "missing platform data.\n");
1386         return -EINVAL;
1387     }
1388     mcbsp = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcbsp), GFP_KERNEL);
1389     if (!mcbsp)
1390         return -ENOMEM;
1391 
1392     mcbsp->id = pdev->id;
1393     mcbsp->pdata = pdata;
1394     mcbsp->dev = &pdev->dev;
1395     platform_set_drvdata(pdev, mcbsp);
1396 
1397     ret = omap_mcbsp_init(pdev);
1398     if (ret)
1399         return ret;
1400 
1401     if (mcbsp->pdata->reg_size == 2) {
1402         omap_mcbsp_dai.playback.formats = SNDRV_PCM_FMTBIT_S16_LE;
1403         omap_mcbsp_dai.capture.formats = SNDRV_PCM_FMTBIT_S16_LE;
1404     }
1405 
1406     ret = devm_snd_soc_register_component(&pdev->dev,
1407                           &omap_mcbsp_component,
1408                           &omap_mcbsp_dai, 1);
1409     if (ret)
1410         return ret;
1411 
1412     return sdma_pcm_platform_register(&pdev->dev, "tx", "rx");
1413 }
1414 
1415 static int asoc_mcbsp_remove(struct platform_device *pdev)
1416 {
1417     struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
1418 
1419     if (mcbsp->pdata->ops && mcbsp->pdata->ops->free)
1420         mcbsp->pdata->ops->free(mcbsp->id);
1421 
1422     if (cpu_latency_qos_request_active(&mcbsp->pm_qos_req))
1423         cpu_latency_qos_remove_request(&mcbsp->pm_qos_req);
1424 
1425     return 0;
1426 }
1427 
1428 static struct platform_driver asoc_mcbsp_driver = {
1429     .driver = {
1430             .name = "omap-mcbsp",
1431             .of_match_table = omap_mcbsp_of_match,
1432     },
1433 
1434     .probe = asoc_mcbsp_probe,
1435     .remove = asoc_mcbsp_remove,
1436 };
1437 
1438 module_platform_driver(asoc_mcbsp_driver);
1439 
1440 MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@bitmer.com>");
1441 MODULE_DESCRIPTION("OMAP I2S SoC Interface");
1442 MODULE_LICENSE("GPL");
1443 MODULE_ALIAS("platform:omap-mcbsp");
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