soc/ti/omap-mcbsp-priv.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * OMAP Multi-Channel Buffered Serial Port
0004  *
0005  * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
0006  *          Peter Ujfalusi <peter.ujfalusi@ti.com>
0007  */
0008
0009 #ifndef __OMAP_MCBSP_PRIV_H__
0010 #define __OMAP_MCBSP_PRIV_H__
0011
0012 #include <linux/platform_data/asoc-ti-mcbsp.h>
0013
0014 #ifdef CONFIG_ARCH_OMAP1
0015 #define mcbsp_omap1()   1
0016 #else
0017 #define mcbsp_omap1()   0
0018 #endif
0019
0020 /* McBSP register numbers. Register address offset = num * reg_step */
0021 enum {
0022     /* Common registers */
0023     OMAP_MCBSP_REG_SPCR2 = 4,
0024     OMAP_MCBSP_REG_SPCR1,
0025     OMAP_MCBSP_REG_RCR2,
0026     OMAP_MCBSP_REG_RCR1,
0027     OMAP_MCBSP_REG_XCR2,
0028     OMAP_MCBSP_REG_XCR1,
0029     OMAP_MCBSP_REG_SRGR2,
0030     OMAP_MCBSP_REG_SRGR1,
0031     OMAP_MCBSP_REG_MCR2,
0032     OMAP_MCBSP_REG_MCR1,
0033     OMAP_MCBSP_REG_RCERA,
0034     OMAP_MCBSP_REG_RCERB,
0035     OMAP_MCBSP_REG_XCERA,
0036     OMAP_MCBSP_REG_XCERB,
0037     OMAP_MCBSP_REG_PCR0,
0038     OMAP_MCBSP_REG_RCERC,
0039     OMAP_MCBSP_REG_RCERD,
0040     OMAP_MCBSP_REG_XCERC,
0041     OMAP_MCBSP_REG_XCERD,
0042     OMAP_MCBSP_REG_RCERE,
0043     OMAP_MCBSP_REG_RCERF,
0044     OMAP_MCBSP_REG_XCERE,
0045     OMAP_MCBSP_REG_XCERF,
0046     OMAP_MCBSP_REG_RCERG,
0047     OMAP_MCBSP_REG_RCERH,
0048     OMAP_MCBSP_REG_XCERG,
0049     OMAP_MCBSP_REG_XCERH,
0050
0051     /* OMAP1-OMAP2420 registers */
0052     OMAP_MCBSP_REG_DRR2 = 0,
0053     OMAP_MCBSP_REG_DRR1,
0054     OMAP_MCBSP_REG_DXR2,
0055     OMAP_MCBSP_REG_DXR1,
0056
0057     /* OMAP2430 and onwards */
0058     OMAP_MCBSP_REG_DRR = 0,
0059     OMAP_MCBSP_REG_DXR = 2,
0060     OMAP_MCBSP_REG_SYSCON = 35,
0061     OMAP_MCBSP_REG_THRSH2,
0062     OMAP_MCBSP_REG_THRSH1,
0063     OMAP_MCBSP_REG_IRQST = 40,
0064     OMAP_MCBSP_REG_IRQEN,
0065     OMAP_MCBSP_REG_WAKEUPEN,
0066     OMAP_MCBSP_REG_XCCR,
0067     OMAP_MCBSP_REG_RCCR,
0068     OMAP_MCBSP_REG_XBUFFSTAT,
0069     OMAP_MCBSP_REG_RBUFFSTAT,
0070     OMAP_MCBSP_REG_SSELCR,
0071 };
0072
0073 /************************** McBSP SPCR1 bit definitions ***********************/
0074 #define RRST            BIT(0)
0075 #define RRDY            BIT(1)
0076 #define RFULL           BIT(2)
0077 #define RSYNC_ERR       BIT(3)
0078 #define RINTM(value)        (((value) & 0x3) << 4)  /* bits 4:5 */
0079 #define ABIS            BIT(6)
0080 #define DXENA           BIT(7)
0081 #define CLKSTP(value)       (((value) & 0x3) << 11) /* bits 11:12 */
0082 #define RJUST(value)        (((value) & 0x3) << 13) /* bits 13:14 */
0083 #define ALB         BIT(15)
0084 #define DLB         BIT(15)
0085
0086 /************************** McBSP SPCR2 bit definitions ***********************/
0087 #define XRST            BIT(0)
0088 #define XRDY            BIT(1)
0089 #define XEMPTY          BIT(2)
0090 #define XSYNC_ERR       BIT(3)
0091 #define XINTM(value)        (((value) & 0x3) << 4)  /* bits 4:5 */
0092 #define GRST            BIT(6)
0093 #define FRST            BIT(7)
0094 #define SOFT            BIT(8)
0095 #define FREE            BIT(9)
0096
0097 /************************** McBSP PCR bit definitions *************************/
0098 #define CLKRP           BIT(0)
0099 #define CLKXP           BIT(1)
0100 #define FSRP            BIT(2)
0101 #define FSXP            BIT(3)
0102 #define DR_STAT         BIT(4)
0103 #define DX_STAT         BIT(5)
0104 #define CLKS_STAT       BIT(6)
0105 #define SCLKME          BIT(7)
0106 #define CLKRM           BIT(8)
0107 #define CLKXM           BIT(9)
0108 #define FSRM            BIT(10)
0109 #define FSXM            BIT(11)
0110 #define RIOEN           BIT(12)
0111 #define XIOEN           BIT(13)
0112 #define IDLE_EN         BIT(14)
0113
0114 /************************** McBSP RCR1 bit definitions ************************/
0115 #define RWDLEN1(value)      (((value) & 0x7) << 5)  /* Bits 5:7 */
0116 #define RFRLEN1(value)      (((value) & 0x7f) << 8) /* Bits 8:14 */
0117
0118 /************************** McBSP XCR1 bit definitions ************************/
0119 #define XWDLEN1(value)      (((value) & 0x7) << 5)  /* Bits 5:7 */
0120 #define XFRLEN1(value)      (((value) & 0x7f) << 8) /* Bits 8:14 */
0121
0122 /*************************** McBSP RCR2 bit definitions ***********************/
0123 #define RDATDLY(value)      ((value) & 0x3)     /* Bits 0:1 */
0124 #define RFIG            BIT(2)
0125 #define RCOMPAND(value)     (((value) & 0x3) << 3)  /* Bits 3:4 */
0126 #define RWDLEN2(value)      (((value) & 0x7) << 5)  /* Bits 5:7 */
0127 #define RFRLEN2(value)      (((value) & 0x7f) << 8) /* Bits 8:14 */
0128 #define RPHASE          BIT(15)
0129
0130 /*************************** McBSP XCR2 bit definitions ***********************/
0131 #define XDATDLY(value)      ((value) & 0x3)     /* Bits 0:1 */
0132 #define XFIG            BIT(2)
0133 #define XCOMPAND(value)     (((value) & 0x3) << 3)  /* Bits 3:4 */
0134 #define XWDLEN2(value)      (((value) & 0x7) << 5)  /* Bits 5:7 */
0135 #define XFRLEN2(value)      (((value) & 0x7f) << 8) /* Bits 8:14 */
0136 #define XPHASE          BIT(15)
0137
0138 /************************* McBSP SRGR1 bit definitions ************************/
0139 #define CLKGDV(value)       ((value) & 0x7f)        /* Bits 0:7 */
0140 #define FWID(value)     (((value) & 0xff) << 8) /* Bits 8:15 */
0141
0142 /************************* McBSP SRGR2 bit definitions ************************/
0143 #define FPER(value)     ((value) & 0x0fff)  /* Bits 0:11 */
0144 #define FSGM            BIT(12)
0145 #define CLKSM           BIT(13)
0146 #define CLKSP           BIT(14)
0147 #define GSYNC           BIT(15)
0148
0149 /************************* McBSP MCR1 bit definitions *************************/
0150 #define RMCM            BIT(0)
0151 #define RCBLK(value)        (((value) & 0x7) << 2)  /* Bits 2:4 */
0152 #define RPABLK(value)       (((value) & 0x3) << 5)  /* Bits 5:6 */
0153 #define RPBBLK(value)       (((value) & 0x3) << 7)  /* Bits 7:8 */
0154
0155 /************************* McBSP MCR2 bit definitions *************************/
0156 #define XMCM(value)     ((value) & 0x3)     /* Bits 0:1 */
0157 #define XCBLK(value)        (((value) & 0x7) << 2)  /* Bits 2:4 */
0158 #define XPABLK(value)       (((value) & 0x3) << 5)  /* Bits 5:6 */
0159 #define XPBBLK(value)       (((value) & 0x3) << 7)  /* Bits 7:8 */
0160
0161 /*********************** McBSP XCCR bit definitions *************************/
0162 #define XDISABLE        BIT(0)
0163 #define XDMAEN          BIT(3)
0164 #define DILB            BIT(5)
0165 #define XFULL_CYCLE     BIT(11)
0166 #define DXENDLY(value)      (((value) & 0x3) << 12) /* Bits 12:13 */
0167 #define PPCONNECT       BIT(14)
0168 #define EXTCLKGATE      BIT(15)
0169
0170 /********************** McBSP RCCR bit definitions *************************/
0171 #define RDISABLE        BIT(0)
0172 #define RDMAEN          BIT(3)
0173 #define RFULL_CYCLE     BIT(11)
0174
0175 /********************** McBSP SYSCONFIG bit definitions ********************/
0176 #define SOFTRST         BIT(1)
0177 #define ENAWAKEUP       BIT(2)
0178 #define SIDLEMODE(value)    (((value) & 0x3) << 3)
0179 #define CLOCKACTIVITY(value)    (((value) & 0x3) << 8)
0180
0181 /********************** McBSP DMA operating modes **************************/
0182 #define MCBSP_DMA_MODE_ELEMENT      0
0183 #define MCBSP_DMA_MODE_THRESHOLD    1
0184
0185 /********************** McBSP WAKEUPEN/IRQST/IRQEN bit definitions *********/
0186 #define RSYNCERREN      BIT(0)
0187 #define RFSREN          BIT(1)
0188 #define REOFEN          BIT(2)
0189 #define RRDYEN          BIT(3)
0190 #define RUNDFLEN        BIT(4)
0191 #define ROVFLEN         BIT(5)
0192 #define XSYNCERREN      BIT(7)
0193 #define XFSXEN          BIT(8)
0194 #define XEOFEN          BIT(9)
0195 #define XRDYEN          BIT(10)
0196 #define XUNDFLEN        BIT(11)
0197 #define XOVFLEN         BIT(12)
0198 #define XEMPTYEOFEN     BIT(14)
0199
0200 /* Clock signal muxing options */
0201 #define CLKR_SRC_CLKR       0 /* CLKR signal is from the CLKR pin */
0202 #define CLKR_SRC_CLKX       1 /* CLKR signal is from the CLKX pin */
0203 #define FSR_SRC_FSR     2 /* FSR signal is from the FSR pin */
0204 #define FSR_SRC_FSX     3 /* FSR signal is from the FSX pin */
0205
0206 /* McBSP functional clock sources */
0207 #define MCBSP_CLKS_PRCM_SRC 0
0208 #define MCBSP_CLKS_PAD_SRC  1
0209
0210 /* we don't do multichannel for now */
0211 struct omap_mcbsp_reg_cfg {
0212     u16 spcr2;
0213     u16 spcr1;
0214     u16 rcr2;
0215     u16 rcr1;
0216     u16 xcr2;
0217     u16 xcr1;
0218     u16 srgr2;
0219     u16 srgr1;
0220     u16 mcr2;
0221     u16 mcr1;
0222     u16 pcr0;
0223     u16 rcerc;
0224     u16 rcerd;
0225     u16 xcerc;
0226     u16 xcerd;
0227     u16 rcere;
0228     u16 rcerf;
0229     u16 xcere;
0230     u16 xcerf;
0231     u16 rcerg;
0232     u16 rcerh;
0233     u16 xcerg;
0234     u16 xcerh;
0235     u16 xccr;
0236     u16 rccr;
0237 };
0238
0239 struct omap_mcbsp_st_data;
0240
0241 struct omap_mcbsp {
0242     struct device *dev;
0243     struct clk *fclk;
0244     spinlock_t lock;
0245     unsigned long phys_base;
0246     unsigned long phys_dma_base;
0247     void __iomem *io_base;
0248     u8 id;
0249     /*
0250      * Flags indicating is the bus already activated and configured by
0251      * another substream
0252      */
0253     int active;
0254     int configured;
0255     u8 free;
0256
0257     int irq;
0258     int rx_irq;
0259     int tx_irq;
0260
0261     /* Protect the field .free, while checking if the mcbsp is in use */
0262     struct omap_mcbsp_platform_data *pdata;
0263     struct omap_mcbsp_st_data *st_data;
0264     struct omap_mcbsp_reg_cfg cfg_regs;
0265     struct snd_dmaengine_dai_dma_data dma_data[2];
0266     unsigned int dma_req[2];
0267     int dma_op_mode;
0268     u16 max_tx_thres;
0269     u16 max_rx_thres;
0270     void *reg_cache;
0271     int reg_cache_size;
0272
0273     unsigned int fmt;
0274     unsigned int in_freq;
0275     unsigned int latency[2];
0276     int clk_div;
0277     int wlen;
0278
0279     struct pm_qos_request pm_qos_req;
0280 };
0281
0282 static inline void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
0283 {
0284     void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
0285
0286     if (mcbsp->pdata->reg_size == 2) {
0287         ((u16 *)mcbsp->reg_cache)[reg] = (u16)val;
0288         writew_relaxed((u16)val, addr);
0289     } else {
0290         ((u32 *)mcbsp->reg_cache)[reg] = val;
0291         writel_relaxed(val, addr);
0292     }
0293 }
0294
0295 static inline int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg,
0296                   bool from_cache)
0297 {
0298     void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
0299
0300     if (mcbsp->pdata->reg_size == 2) {
0301         return !from_cache ? readw_relaxed(addr) :
0302                      ((u16 *)mcbsp->reg_cache)[reg];
0303     } else {
0304         return !from_cache ? readl_relaxed(addr) :
0305                      ((u32 *)mcbsp->reg_cache)[reg];
0306     }
0307 }
0308
0309 #define MCBSP_READ(mcbsp, reg) \
0310         omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0)
0311 #define MCBSP_WRITE(mcbsp, reg, val) \
0312         omap_mcbsp_write(mcbsp, OMAP_MCBSP_REG_##reg, val)
0313 #define MCBSP_READ_CACHE(mcbsp, reg) \
0314         omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1)
0315
0316
0317 /* Sidetone specific API */
0318 int omap_mcbsp_st_init(struct platform_device *pdev);
0319 int omap_mcbsp_st_start(struct omap_mcbsp *mcbsp);
0320 int omap_mcbsp_st_stop(struct omap_mcbsp *mcbsp);
0321
0322 #endif /* __OMAP_MCBSP_PRIV_H__ */