soc/ti/omap-dmic.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * omap-dmic.h  --  OMAP Digital Microphone Controller
0004  */
0005
0006 #ifndef _OMAP_DMIC_H
0007 #define _OMAP_DMIC_H
0008
0009 #define OMAP_DMIC_REVISION_REG      0x00
0010 #define OMAP_DMIC_SYSCONFIG_REG     0x10
0011 #define OMAP_DMIC_IRQSTATUS_RAW_REG 0x24
0012 #define OMAP_DMIC_IRQSTATUS_REG     0x28
0013 #define OMAP_DMIC_IRQENABLE_SET_REG 0x2C
0014 #define OMAP_DMIC_IRQENABLE_CLR_REG 0x30
0015 #define OMAP_DMIC_IRQWAKE_EN_REG    0x34
0016 #define OMAP_DMIC_DMAENABLE_SET_REG 0x38
0017 #define OMAP_DMIC_DMAENABLE_CLR_REG 0x3C
0018 #define OMAP_DMIC_DMAWAKEEN_REG     0x40
0019 #define OMAP_DMIC_CTRL_REG      0x44
0020 #define OMAP_DMIC_DATA_REG      0x48
0021 #define OMAP_DMIC_FIFO_CTRL_REG     0x4C
0022 #define OMAP_DMIC_FIFO_DMIC1R_DATA_REG  0x50
0023 #define OMAP_DMIC_FIFO_DMIC1L_DATA_REG  0x54
0024 #define OMAP_DMIC_FIFO_DMIC2R_DATA_REG  0x58
0025 #define OMAP_DMIC_FIFO_DMIC2L_DATA_REG  0x5C
0026 #define OMAP_DMIC_FIFO_DMIC3R_DATA_REG  0x60
0027 #define OMAP_DMIC_FIFO_DMIC3L_DATA_REG  0x64
0028
0029 /* IRQSTATUS_RAW, IRQSTATUS, IRQENABLE_SET, IRQENABLE_CLR bit fields */
0030 #define OMAP_DMIC_IRQ           (1 << 0)
0031 #define OMAP_DMIC_IRQ_FULL      (1 << 1)
0032 #define OMAP_DMIC_IRQ_ALMST_EMPTY   (1 << 2)
0033 #define OMAP_DMIC_IRQ_EMPTY     (1 << 3)
0034 #define OMAP_DMIC_IRQ_MASK      0x07
0035
0036 /* DMIC_DMAENABLE bit fields */
0037 #define OMAP_DMIC_DMA_ENABLE        0x1
0038
0039 /* DMIC_CTRL bit fields */
0040 #define OMAP_DMIC_UP1_ENABLE        (1 << 0)
0041 #define OMAP_DMIC_UP2_ENABLE        (1 << 1)
0042 #define OMAP_DMIC_UP3_ENABLE        (1 << 2)
0043 #define OMAP_DMIC_UP_ENABLE_MASK    0x7
0044 #define OMAP_DMIC_FORMAT        (1 << 3)
0045 #define OMAP_DMIC_POLAR1        (1 << 4)
0046 #define OMAP_DMIC_POLAR2        (1 << 5)
0047 #define OMAP_DMIC_POLAR3        (1 << 6)
0048 #define OMAP_DMIC_POLAR_MASK        (0x7 << 4)
0049 #define OMAP_DMIC_CLK_DIV(x)        (((x) & 0x7) << 7)
0050 #define OMAP_DMIC_CLK_DIV_MASK      (0x7 << 7)
0051 #define OMAP_DMIC_RESET         (1 << 10)
0052
0053 #define OMAP_DMICOUTFORMAT_LJUST    (0 << 3)
0054 #define OMAP_DMICOUTFORMAT_RJUST    (1 << 3)
0055
0056 /* DMIC_FIFO_CTRL bit fields */
0057 #define OMAP_DMIC_THRES_MAX     0xF
0058
0059 enum omap_dmic_clk {
0060     OMAP_DMIC_SYSCLK_PAD_CLKS,      /* PAD_CLKS */
0061     OMAP_DMIC_SYSCLK_SLIMBLUS_CLKS,     /* SLIMBUS_CLK */
0062     OMAP_DMIC_SYSCLK_SYNC_MUX_CLKS,     /* DMIC_SYNC_MUX_CLK */
0063     OMAP_DMIC_ABE_DMIC_CLK,         /* abe_dmic_clk */
0064 };
0065
0066 #endif