soc/ti/davinci-mcasp.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * ALSA SoC McASP Audio Layer for TI DAVINCI processor
0004  *
0005  * Multi-channel Audio Serial Port Driver
0006  *
0007  * Author: Nirmal Pandey <n-pandey@ti.com>,
0008  *         Suresh Rajashekara <suresh.r@ti.com>
0009  *         Steve Chen <schen@.mvista.com>
0010  *
0011  * Copyright:   (C) 2009 MontaVista Software, Inc., <source@mvista.com>
0012  * Copyright:   (C) 2009  Texas Instruments, India
0013  */
0014
0015 #include <linux/init.h>
0016 #include <linux/module.h>
0017 #include <linux/device.h>
0018 #include <linux/slab.h>
0019 #include <linux/delay.h>
0020 #include <linux/io.h>
0021 #include <linux/clk.h>
0022 #include <linux/pm_runtime.h>
0023 #include <linux/of.h>
0024 #include <linux/of_platform.h>
0025 #include <linux/of_device.h>
0026 #include <linux/platform_data/davinci_asp.h>
0027 #include <linux/math64.h>
0028 #include <linux/bitmap.h>
0029 #include <linux/gpio/driver.h>
0030
0031 #include <sound/asoundef.h>
0032 #include <sound/core.h>
0033 #include <sound/pcm.h>
0034 #include <sound/pcm_params.h>
0035 #include <sound/initval.h>
0036 #include <sound/soc.h>
0037 #include <sound/dmaengine_pcm.h>
0038
0039 #include "edma-pcm.h"
0040 #include "sdma-pcm.h"
0041 #include "udma-pcm.h"
0042 #include "davinci-mcasp.h"
0043
0044 #define MCASP_MAX_AFIFO_DEPTH   64
0045
0046 #ifdef CONFIG_PM
0047 static u32 context_regs[] = {
0048     DAVINCI_MCASP_TXFMCTL_REG,
0049     DAVINCI_MCASP_RXFMCTL_REG,
0050     DAVINCI_MCASP_TXFMT_REG,
0051     DAVINCI_MCASP_RXFMT_REG,
0052     DAVINCI_MCASP_ACLKXCTL_REG,
0053     DAVINCI_MCASP_ACLKRCTL_REG,
0054     DAVINCI_MCASP_AHCLKXCTL_REG,
0055     DAVINCI_MCASP_AHCLKRCTL_REG,
0056     DAVINCI_MCASP_PDIR_REG,
0057     DAVINCI_MCASP_PFUNC_REG,
0058     DAVINCI_MCASP_RXMASK_REG,
0059     DAVINCI_MCASP_TXMASK_REG,
0060     DAVINCI_MCASP_RXTDM_REG,
0061     DAVINCI_MCASP_TXTDM_REG,
0062 };
0063
0064 struct davinci_mcasp_context {
0065     u32 config_regs[ARRAY_SIZE(context_regs)];
0066     u32 afifo_regs[2]; /* for read/write fifo control registers */
0067     u32 *xrsr_regs; /* for serializer configuration */
0068     bool    pm_state;
0069 };
0070 #endif
0071
0072 struct davinci_mcasp_ruledata {
0073     struct davinci_mcasp *mcasp;
0074     int serializers;
0075 };
0076
0077 struct davinci_mcasp {
0078     struct snd_dmaengine_dai_dma_data dma_data[2];
0079     struct davinci_mcasp_pdata *pdata;
0080     void __iomem *base;
0081     u32 fifo_base;
0082     struct device *dev;
0083     struct snd_pcm_substream *substreams[2];
0084     unsigned int dai_fmt;
0085
0086     u32 iec958_status;
0087
0088     /* Audio can not be enabled due to missing parameter(s) */
0089     bool    missing_audio_param;
0090
0091     /* McASP specific data */
0092     int tdm_slots;
0093     u32 tdm_mask[2];
0094     int slot_width;
0095     u8  op_mode;
0096     u8  dismod;
0097     u8  num_serializer;
0098     u8  *serial_dir;
0099     u8  version;
0100     u8  bclk_div;
0101     int streams;
0102     u32 irq_request[2];
0103
0104     int sysclk_freq;
0105     bool    bclk_master;
0106     u32 auxclk_fs_ratio;
0107
0108     unsigned long pdir; /* Pin direction bitfield */
0109
0110     /* McASP FIFO related */
0111     u8  txnumevt;
0112     u8  rxnumevt;
0113
0114     bool    dat_port;
0115
0116     /* Used for comstraint setting on the second stream */
0117     u32 channels;
0118     int max_format_width;
0119     u8  active_serializers[2];
0120
0121 #ifdef CONFIG_GPIOLIB
0122     struct gpio_chip gpio_chip;
0123 #endif
0124
0125 #ifdef CONFIG_PM
0126     struct davinci_mcasp_context context;
0127 #endif
0128
0129     struct davinci_mcasp_ruledata ruledata[2];
0130     struct snd_pcm_hw_constraint_list chconstr[2];
0131 };
0132
0133 static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
0134                   u32 val)
0135 {
0136     void __iomem *reg = mcasp->base + offset;
0137     __raw_writel(__raw_readl(reg) | val, reg);
0138 }
0139
0140 static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
0141                   u32 val)
0142 {
0143     void __iomem *reg = mcasp->base + offset;
0144     __raw_writel((__raw_readl(reg) & ~(val)), reg);
0145 }
0146
0147 static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
0148                   u32 val, u32 mask)
0149 {
0150     void __iomem *reg = mcasp->base + offset;
0151     __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
0152 }
0153
0154 static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
0155                  u32 val)
0156 {
0157     __raw_writel(val, mcasp->base + offset);
0158 }
0159
0160 static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
0161 {
0162     return (u32)__raw_readl(mcasp->base + offset);
0163 }
0164
0165 static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
0166 {
0167     int i = 0;
0168
0169     mcasp_set_bits(mcasp, ctl_reg, val);
0170
0171     /* programming GBLCTL needs to read back from GBLCTL and verfiy */
0172     /* loop count is to avoid the lock-up */
0173     for (i = 0; i < 1000; i++) {
0174         if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
0175             break;
0176     }
0177
0178     if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
0179         printk(KERN_ERR "GBLCTL write error\n");
0180 }
0181
0182 static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
0183 {
0184     u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
0185     u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
0186
0187     return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
0188 }
0189
0190 static inline void mcasp_set_clk_pdir(struct davinci_mcasp *mcasp, bool enable)
0191 {
0192     u32 bit = PIN_BIT_AMUTE;
0193
0194     for_each_set_bit_from(bit, &mcasp->pdir, PIN_BIT_AFSR + 1) {
0195         if (enable)
0196             mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
0197         else
0198             mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
0199     }
0200 }
0201
0202 static inline void mcasp_set_axr_pdir(struct davinci_mcasp *mcasp, bool enable)
0203 {
0204     u32 bit;
0205
0206     for_each_set_bit(bit, &mcasp->pdir, PIN_BIT_AMUTE) {
0207         if (enable)
0208             mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
0209         else
0210             mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
0211     }
0212 }
0213
0214 static void mcasp_start_rx(struct davinci_mcasp *mcasp)
0215 {
0216     if (mcasp->rxnumevt) {  /* enable FIFO */
0217         u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
0218
0219         mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
0220         mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
0221     }
0222
0223     /* Start clocks */
0224     mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
0225     mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
0226     /*
0227      * When ASYNC == 0 the transmit and receive sections operate
0228      * synchronously from the transmit clock and frame sync. We need to make
0229      * sure that the TX signlas are enabled when starting reception.
0230      */
0231     if (mcasp_is_synchronous(mcasp)) {
0232         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
0233         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
0234         mcasp_set_clk_pdir(mcasp, true);
0235     }
0236
0237     /* Activate serializer(s) */
0238     mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
0239     mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
0240     /* Release RX state machine */
0241     mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
0242     /* Release Frame Sync generator */
0243     mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
0244     if (mcasp_is_synchronous(mcasp))
0245         mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
0246
0247     /* enable receive IRQs */
0248     mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
0249                mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
0250 }
0251
0252 static void mcasp_start_tx(struct davinci_mcasp *mcasp)
0253 {
0254     u32 cnt;
0255
0256     if (mcasp->txnumevt) {  /* enable FIFO */
0257         u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
0258
0259         mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
0260         mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
0261     }
0262
0263     /* Start clocks */
0264     mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
0265     mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
0266     mcasp_set_clk_pdir(mcasp, true);
0267
0268     /* Activate serializer(s) */
0269     mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
0270     mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
0271
0272     /* wait for XDATA to be cleared */
0273     cnt = 0;
0274     while ((mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & XRDATA) &&
0275            (cnt < 100000))
0276         cnt++;
0277
0278     mcasp_set_axr_pdir(mcasp, true);
0279
0280     /* Release TX state machine */
0281     mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
0282     /* Release Frame Sync generator */
0283     mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
0284
0285     /* enable transmit IRQs */
0286     mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
0287                mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
0288 }
0289
0290 static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
0291 {
0292     mcasp->streams++;
0293
0294     if (stream == SNDRV_PCM_STREAM_PLAYBACK)
0295         mcasp_start_tx(mcasp);
0296     else
0297         mcasp_start_rx(mcasp);
0298 }
0299
0300 static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
0301 {
0302     /* disable IRQ sources */
0303     mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
0304                mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
0305
0306     /*
0307      * In synchronous mode stop the TX clocks if no other stream is
0308      * running
0309      */
0310     if (mcasp_is_synchronous(mcasp) && !mcasp->streams) {
0311         mcasp_set_clk_pdir(mcasp, false);
0312         mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
0313     }
0314
0315     mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
0316     mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
0317
0318     if (mcasp->rxnumevt) {  /* disable FIFO */
0319         u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
0320
0321         mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
0322     }
0323 }
0324
0325 static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
0326 {
0327     u32 val = 0;
0328
0329     /* disable IRQ sources */
0330     mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
0331                mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
0332
0333     /*
0334      * In synchronous mode keep TX clocks running if the capture stream is
0335      * still running.
0336      */
0337     if (mcasp_is_synchronous(mcasp) && mcasp->streams)
0338         val =  TXHCLKRST | TXCLKRST | TXFSRST;
0339     else
0340         mcasp_set_clk_pdir(mcasp, false);
0341
0342
0343     mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
0344     mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
0345
0346     if (mcasp->txnumevt) {  /* disable FIFO */
0347         u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
0348
0349         mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
0350     }
0351
0352     mcasp_set_axr_pdir(mcasp, false);
0353 }
0354
0355 static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
0356 {
0357     mcasp->streams--;
0358
0359     if (stream == SNDRV_PCM_STREAM_PLAYBACK)
0360         mcasp_stop_tx(mcasp);
0361     else
0362         mcasp_stop_rx(mcasp);
0363 }
0364
0365 static irqreturn_t davinci_mcasp_tx_irq_handler(int irq, void *data)
0366 {
0367     struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
0368     struct snd_pcm_substream *substream;
0369     u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK];
0370     u32 handled_mask = 0;
0371     u32 stat;
0372
0373     stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG);
0374     if (stat & XUNDRN & irq_mask) {
0375         dev_warn(mcasp->dev, "Transmit buffer underflow\n");
0376         handled_mask |= XUNDRN;
0377
0378         substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK];
0379         if (substream)
0380             snd_pcm_stop_xrun(substream);
0381     }
0382
0383     if (!handled_mask)
0384         dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n",
0385              stat);
0386
0387     if (stat & XRERR)
0388         handled_mask |= XRERR;
0389
0390     /* Ack the handled event only */
0391     mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask);
0392
0393     return IRQ_RETVAL(handled_mask);
0394 }
0395
0396 static irqreturn_t davinci_mcasp_rx_irq_handler(int irq, void *data)
0397 {
0398     struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
0399     struct snd_pcm_substream *substream;
0400     u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE];
0401     u32 handled_mask = 0;
0402     u32 stat;
0403
0404     stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG);
0405     if (stat & ROVRN & irq_mask) {
0406         dev_warn(mcasp->dev, "Receive buffer overflow\n");
0407         handled_mask |= ROVRN;
0408
0409         substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE];
0410         if (substream)
0411             snd_pcm_stop_xrun(substream);
0412     }
0413
0414     if (!handled_mask)
0415         dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n",
0416              stat);
0417
0418     if (stat & XRERR)
0419         handled_mask |= XRERR;
0420
0421     /* Ack the handled event only */
0422     mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask);
0423
0424     return IRQ_RETVAL(handled_mask);
0425 }
0426
0427 static irqreturn_t davinci_mcasp_common_irq_handler(int irq, void *data)
0428 {
0429     struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
0430     irqreturn_t ret = IRQ_NONE;
0431
0432     if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK])
0433         ret = davinci_mcasp_tx_irq_handler(irq, data);
0434
0435     if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE])
0436         ret |= davinci_mcasp_rx_irq_handler(irq, data);
0437
0438     return ret;
0439 }
0440
0441 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
0442                      unsigned int fmt)
0443 {
0444     struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
0445     int ret = 0;
0446     u32 data_delay;
0447     bool fs_pol_rising;
0448     bool inv_fs = false;
0449
0450     if (!fmt)
0451         return 0;
0452
0453     pm_runtime_get_sync(mcasp->dev);
0454     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0455     case SND_SOC_DAIFMT_DSP_A:
0456         mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
0457         mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
0458         /* 1st data bit occur one ACLK cycle after the frame sync */
0459         data_delay = 1;
0460         break;
0461     case SND_SOC_DAIFMT_DSP_B:
0462     case SND_SOC_DAIFMT_AC97:
0463         mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
0464         mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
0465         /* No delay after FS */
0466         data_delay = 0;
0467         break;
0468     case SND_SOC_DAIFMT_I2S:
0469         /* configure a full-word SYNC pulse (LRCLK) */
0470         mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
0471         mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
0472         /* 1st data bit occur one ACLK cycle after the frame sync */
0473         data_delay = 1;
0474         /* FS need to be inverted */
0475         inv_fs = true;
0476         break;
0477     case SND_SOC_DAIFMT_RIGHT_J:
0478     case SND_SOC_DAIFMT_LEFT_J:
0479         /* configure a full-word SYNC pulse (LRCLK) */
0480         mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
0481         mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
0482         /* No delay after FS */
0483         data_delay = 0;
0484         break;
0485     default:
0486         ret = -EINVAL;
0487         goto out;
0488     }
0489
0490     mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay),
0491                FSXDLY(3));
0492     mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay),
0493                FSRDLY(3));
0494
0495     switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
0496     case SND_SOC_DAIFMT_BP_FP:
0497         /* codec is clock and frame slave */
0498         mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
0499         mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
0500
0501         mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
0502         mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
0503
0504         /* BCLK */
0505         set_bit(PIN_BIT_ACLKX, &mcasp->pdir);
0506         set_bit(PIN_BIT_ACLKR, &mcasp->pdir);
0507         /* Frame Sync */
0508         set_bit(PIN_BIT_AFSX, &mcasp->pdir);
0509         set_bit(PIN_BIT_AFSR, &mcasp->pdir);
0510
0511         mcasp->bclk_master = 1;
0512         break;
0513     case SND_SOC_DAIFMT_BP_FC:
0514         /* codec is clock slave and frame master */
0515         mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
0516         mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
0517
0518         mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
0519         mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
0520
0521         /* BCLK */
0522         set_bit(PIN_BIT_ACLKX, &mcasp->pdir);
0523         set_bit(PIN_BIT_ACLKR, &mcasp->pdir);
0524         /* Frame Sync */
0525         clear_bit(PIN_BIT_AFSX, &mcasp->pdir);
0526         clear_bit(PIN_BIT_AFSR, &mcasp->pdir);
0527
0528         mcasp->bclk_master = 1;
0529         break;
0530     case SND_SOC_DAIFMT_BC_FP:
0531         /* codec is clock master and frame slave */
0532         mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
0533         mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
0534
0535         mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
0536         mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
0537
0538         /* BCLK */
0539         clear_bit(PIN_BIT_ACLKX, &mcasp->pdir);
0540         clear_bit(PIN_BIT_ACLKR, &mcasp->pdir);
0541         /* Frame Sync */
0542         set_bit(PIN_BIT_AFSX, &mcasp->pdir);
0543         set_bit(PIN_BIT_AFSR, &mcasp->pdir);
0544
0545         mcasp->bclk_master = 0;
0546         break;
0547     case SND_SOC_DAIFMT_BC_FC:
0548         /* codec is clock and frame master */
0549         mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
0550         mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
0551
0552         mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
0553         mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
0554
0555         /* BCLK */
0556         clear_bit(PIN_BIT_ACLKX, &mcasp->pdir);
0557         clear_bit(PIN_BIT_ACLKR, &mcasp->pdir);
0558         /* Frame Sync */
0559         clear_bit(PIN_BIT_AFSX, &mcasp->pdir);
0560         clear_bit(PIN_BIT_AFSR, &mcasp->pdir);
0561
0562         mcasp->bclk_master = 0;
0563         break;
0564     default:
0565         ret = -EINVAL;
0566         goto out;
0567     }
0568
0569     switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
0570     case SND_SOC_DAIFMT_IB_NF:
0571         mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
0572         mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
0573         fs_pol_rising = true;
0574         break;
0575     case SND_SOC_DAIFMT_NB_IF:
0576         mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
0577         mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
0578         fs_pol_rising = false;
0579         break;
0580     case SND_SOC_DAIFMT_IB_IF:
0581         mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
0582         mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
0583         fs_pol_rising = false;
0584         break;
0585     case SND_SOC_DAIFMT_NB_NF:
0586         mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
0587         mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
0588         fs_pol_rising = true;
0589         break;
0590     default:
0591         ret = -EINVAL;
0592         goto out;
0593     }
0594
0595     if (inv_fs)
0596         fs_pol_rising = !fs_pol_rising;
0597
0598     if (fs_pol_rising) {
0599         mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
0600         mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
0601     } else {
0602         mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
0603         mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
0604     }
0605
0606     mcasp->dai_fmt = fmt;
0607 out:
0608     pm_runtime_put(mcasp->dev);
0609     return ret;
0610 }
0611
0612 static int __davinci_mcasp_set_clkdiv(struct davinci_mcasp *mcasp, int div_id,
0613                       int div, bool explicit)
0614 {
0615     pm_runtime_get_sync(mcasp->dev);
0616     switch (div_id) {
0617     case MCASP_CLKDIV_AUXCLK:           /* MCLK divider */
0618         mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
0619                    AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
0620         mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
0621                    AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
0622         break;
0623
0624     case MCASP_CLKDIV_BCLK:         /* BCLK divider */
0625         mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
0626                    ACLKXDIV(div - 1), ACLKXDIV_MASK);
0627         mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
0628                    ACLKRDIV(div - 1), ACLKRDIV_MASK);
0629         if (explicit)
0630             mcasp->bclk_div = div;
0631         break;
0632
0633     case MCASP_CLKDIV_BCLK_FS_RATIO:
0634         /*
0635          * BCLK/LRCLK ratio descries how many bit-clock cycles
0636          * fit into one frame. The clock ratio is given for a
0637          * full period of data (for I2S format both left and
0638          * right channels), so it has to be divided by number
0639          * of tdm-slots (for I2S - divided by 2).
0640          * Instead of storing this ratio, we calculate a new
0641          * tdm_slot width by dividing the ratio by the
0642          * number of configured tdm slots.
0643          */
0644         mcasp->slot_width = div / mcasp->tdm_slots;
0645         if (div % mcasp->tdm_slots)
0646             dev_warn(mcasp->dev,
0647                  "%s(): BCLK/LRCLK %d is not divisible by %d tdm slots",
0648                  __func__, div, mcasp->tdm_slots);
0649         break;
0650
0651     default:
0652         return -EINVAL;
0653     }
0654
0655     pm_runtime_put(mcasp->dev);
0656     return 0;
0657 }
0658
0659 static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
0660                     int div)
0661 {
0662     struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
0663
0664     return __davinci_mcasp_set_clkdiv(mcasp, div_id, div, 1);
0665 }
0666
0667 static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
0668                     unsigned int freq, int dir)
0669 {
0670     struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
0671
0672     pm_runtime_get_sync(mcasp->dev);
0673
0674     if (dir == SND_SOC_CLOCK_IN) {
0675         switch (clk_id) {
0676         case MCASP_CLK_HCLK_AHCLK:
0677             mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
0678                        AHCLKXE);
0679             mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
0680                        AHCLKRE);
0681             clear_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
0682             break;
0683         case MCASP_CLK_HCLK_AUXCLK:
0684             mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
0685                        AHCLKXE);
0686             mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
0687                        AHCLKRE);
0688             set_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
0689             break;
0690         default:
0691             dev_err(mcasp->dev, "Invalid clk id: %d\n", clk_id);
0692             goto out;
0693         }
0694     } else {
0695         /* Select AUXCLK as HCLK */
0696         mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
0697         mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
0698         set_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
0699     }
0700     /*
0701      * When AHCLK X/R is selected to be output it means that the HCLK is
0702      * the same clock - coming via AUXCLK.
0703      */
0704     mcasp->sysclk_freq = freq;
0705 out:
0706     pm_runtime_put(mcasp->dev);
0707     return 0;
0708 }
0709
0710 /* All serializers must have equal number of channels */
0711 static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp, int stream,
0712                        int serializers)
0713 {
0714     struct snd_pcm_hw_constraint_list *cl = &mcasp->chconstr[stream];
0715     unsigned int *list = (unsigned int *) cl->list;
0716     int slots = mcasp->tdm_slots;
0717     int i, count = 0;
0718
0719     if (mcasp->tdm_mask[stream])
0720         slots = hweight32(mcasp->tdm_mask[stream]);
0721
0722     for (i = 1; i <= slots; i++)
0723         list[count++] = i;
0724
0725     for (i = 2; i <= serializers; i++)
0726         list[count++] = i*slots;
0727
0728     cl->count = count;
0729
0730     return 0;
0731 }
0732
0733 static int davinci_mcasp_set_ch_constraints(struct davinci_mcasp *mcasp)
0734 {
0735     int rx_serializers = 0, tx_serializers = 0, ret, i;
0736
0737     for (i = 0; i < mcasp->num_serializer; i++)
0738         if (mcasp->serial_dir[i] == TX_MODE)
0739             tx_serializers++;
0740         else if (mcasp->serial_dir[i] == RX_MODE)
0741             rx_serializers++;
0742
0743     ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_PLAYBACK,
0744                       tx_serializers);
0745     if (ret)
0746         return ret;
0747
0748     ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_CAPTURE,
0749                       rx_serializers);
0750
0751     return ret;
0752 }
0753
0754
0755 static int davinci_mcasp_set_tdm_slot(struct snd_soc_dai *dai,
0756                       unsigned int tx_mask,
0757                       unsigned int rx_mask,
0758                       int slots, int slot_width)
0759 {
0760     struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
0761
0762     if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
0763         return 0;
0764
0765     dev_dbg(mcasp->dev,
0766          "%s() tx_mask 0x%08x rx_mask 0x%08x slots %d width %d\n",
0767          __func__, tx_mask, rx_mask, slots, slot_width);
0768
0769     if (tx_mask >= (1<<slots) || rx_mask >= (1<<slots)) {
0770         dev_err(mcasp->dev,
0771             "Bad tdm mask tx: 0x%08x rx: 0x%08x slots %d\n",
0772             tx_mask, rx_mask, slots);
0773         return -EINVAL;
0774     }
0775
0776     if (slot_width &&
0777         (slot_width < 8 || slot_width > 32 || slot_width % 4 != 0)) {
0778         dev_err(mcasp->dev, "%s: Unsupported slot_width %d\n",
0779             __func__, slot_width);
0780         return -EINVAL;
0781     }
0782
0783     mcasp->tdm_slots = slots;
0784     mcasp->tdm_mask[SNDRV_PCM_STREAM_PLAYBACK] = tx_mask;
0785     mcasp->tdm_mask[SNDRV_PCM_STREAM_CAPTURE] = rx_mask;
0786     mcasp->slot_width = slot_width;
0787
0788     return davinci_mcasp_set_ch_constraints(mcasp);
0789 }
0790
0791 static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
0792                        int sample_width)
0793 {
0794     u32 fmt;
0795     u32 tx_rotate, rx_rotate, slot_width;
0796     u32 mask = (1ULL << sample_width) - 1;
0797
0798     if (mcasp->slot_width)
0799         slot_width = mcasp->slot_width;
0800     else if (mcasp->max_format_width)
0801         slot_width = mcasp->max_format_width;
0802     else
0803         slot_width = sample_width;
0804     /*
0805      * TX rotation:
0806      * right aligned formats: rotate w/ slot_width
0807      * left aligned formats: rotate w/ sample_width
0808      *
0809      * RX rotation:
0810      * right aligned formats: no rotation needed
0811      * left aligned formats: rotate w/ (slot_width - sample_width)
0812      */
0813     if ((mcasp->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==
0814         SND_SOC_DAIFMT_RIGHT_J) {
0815         tx_rotate = (slot_width / 4) & 0x7;
0816         rx_rotate = 0;
0817     } else {
0818         tx_rotate = (sample_width / 4) & 0x7;
0819         rx_rotate = (slot_width - sample_width) / 4;
0820     }
0821
0822     /* mapping of the XSSZ bit-field as described in the datasheet */
0823     fmt = (slot_width >> 1) - 1;
0824
0825     if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
0826         mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
0827                    RXSSZ(0x0F));
0828         mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
0829                    TXSSZ(0x0F));
0830         mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
0831                    TXROT(7));
0832         mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
0833                    RXROT(7));
0834         mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
0835     } else {
0836         /*
0837          * according to the TRM it should be TXROT=0, this one works:
0838          * 16 bit to 23-8 (TXROT=6, rotate 24 bits)
0839          * 24 bit to 23-0 (TXROT=0, rotate 0 bits)
0840          *
0841          * TXROT = 0 only works with 24bit samples
0842          */
0843         tx_rotate = (sample_width / 4 + 2) & 0x7;
0844
0845         mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
0846                    TXROT(7));
0847         mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(15),
0848                    TXSSZ(0x0F));
0849     }
0850
0851     mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
0852
0853     return 0;
0854 }
0855
0856 static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
0857                  int period_words, int channels)
0858 {
0859     struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream];
0860     int i;
0861     u8 tx_ser = 0;
0862     u8 rx_ser = 0;
0863     u8 slots = mcasp->tdm_slots;
0864     u8 max_active_serializers, max_rx_serializers, max_tx_serializers;
0865     int active_serializers, numevt;
0866     u32 reg;
0867
0868     /* In DIT mode we only allow maximum of one serializers for now */
0869     if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
0870         max_active_serializers = 1;
0871     else
0872         max_active_serializers = (channels + slots - 1) / slots;
0873
0874     /* Default configuration */
0875     if (mcasp->version < MCASP_VERSION_3)
0876         mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
0877
0878     if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
0879         mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
0880         mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
0881         max_tx_serializers = max_active_serializers;
0882         max_rx_serializers =
0883             mcasp->active_serializers[SNDRV_PCM_STREAM_CAPTURE];
0884     } else {
0885         mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
0886         mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
0887         max_tx_serializers =
0888             mcasp->active_serializers[SNDRV_PCM_STREAM_PLAYBACK];
0889         max_rx_serializers = max_active_serializers;
0890     }
0891
0892     for (i = 0; i < mcasp->num_serializer; i++) {
0893         mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
0894                    mcasp->serial_dir[i]);
0895         if (mcasp->serial_dir[i] == TX_MODE &&
0896                     tx_ser < max_tx_serializers) {
0897             mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
0898                        mcasp->dismod, DISMOD_MASK);
0899             set_bit(PIN_BIT_AXR(i), &mcasp->pdir);
0900             tx_ser++;
0901         } else if (mcasp->serial_dir[i] == RX_MODE &&
0902                     rx_ser < max_rx_serializers) {
0903             clear_bit(PIN_BIT_AXR(i), &mcasp->pdir);
0904             rx_ser++;
0905         } else {
0906             /* Inactive or unused pin, set it to inactive */
0907             mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
0908                        SRMOD_INACTIVE, SRMOD_MASK);
0909             /* If unused, set DISMOD for the pin */
0910             if (mcasp->serial_dir[i] != INACTIVE_MODE)
0911                 mcasp_mod_bits(mcasp,
0912                            DAVINCI_MCASP_XRSRCTL_REG(i),
0913                            mcasp->dismod, DISMOD_MASK);
0914             clear_bit(PIN_BIT_AXR(i), &mcasp->pdir);
0915         }
0916     }
0917
0918     if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
0919         active_serializers = tx_ser;
0920         numevt = mcasp->txnumevt;
0921         reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
0922     } else {
0923         active_serializers = rx_ser;
0924         numevt = mcasp->rxnumevt;
0925         reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
0926     }
0927
0928     if (active_serializers < max_active_serializers) {
0929         dev_warn(mcasp->dev, "stream has more channels (%d) than are "
0930              "enabled in mcasp (%d)\n", channels,
0931              active_serializers * slots);
0932         return -EINVAL;
0933     }
0934
0935     /* AFIFO is not in use */
0936     if (!numevt) {
0937         /* Configure the burst size for platform drivers */
0938         if (active_serializers > 1) {
0939             /*
0940              * If more than one serializers are in use we have one
0941              * DMA request to provide data for all serializers.
0942              * For example if three serializers are enabled the DMA
0943              * need to transfer three words per DMA request.
0944              */
0945             dma_data->maxburst = active_serializers;
0946         } else {
0947             dma_data->maxburst = 0;
0948         }
0949
0950         goto out;
0951     }
0952
0953     if (period_words % active_serializers) {
0954         dev_err(mcasp->dev, "Invalid combination of period words and "
0955             "active serializers: %d, %d\n", period_words,
0956             active_serializers);
0957         return -EINVAL;
0958     }
0959
0960     /*
0961      * Calculate the optimal AFIFO depth for platform side:
0962      * The number of words for numevt need to be in steps of active
0963      * serializers.
0964      */
0965     numevt = (numevt / active_serializers) * active_serializers;
0966
0967     while (period_words % numevt && numevt > 0)
0968         numevt -= active_serializers;
0969     if (numevt <= 0)
0970         numevt = active_serializers;
0971
0972     mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK);
0973     mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK);
0974
0975     /* Configure the burst size for platform drivers */
0976     if (numevt == 1)
0977         numevt = 0;
0978     dma_data->maxburst = numevt;
0979
0980 out:
0981     mcasp->active_serializers[stream] = active_serializers;
0982
0983     return 0;
0984 }
0985
0986 static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream,
0987                   int channels)
0988 {
0989     int i, active_slots;
0990     int total_slots;
0991     int active_serializers;
0992     u32 mask = 0;
0993     u32 busel = 0;
0994
0995     total_slots = mcasp->tdm_slots;
0996
0997     /*
0998      * If more than one serializer is needed, then use them with
0999      * all the specified tdm_slots. Otherwise, one serializer can
1000      * cope with the transaction using just as many slots as there
1001      * are channels in the stream.
1002      */
1003     if (mcasp->tdm_mask[stream]) {
1004         active_slots = hweight32(mcasp->tdm_mask[stream]);
1005         active_serializers = (channels + active_slots - 1) /
1006             active_slots;
1007         if (active_serializers == 1)
1008             active_slots = channels;
1009         for (i = 0; i < total_slots; i++) {
1010             if ((1 << i) & mcasp->tdm_mask[stream]) {
1011                 mask |= (1 << i);
1012                 if (--active_slots <= 0)
1013                     break;
1014             }
1015         }
1016     } else {
1017         active_serializers = (channels + total_slots - 1) / total_slots;
1018         if (active_serializers == 1)
1019             active_slots = channels;
1020         else
1021             active_slots = total_slots;
1022
1023         for (i = 0; i < active_slots; i++)
1024             mask |= (1 << i);
1025     }
1026
1027     mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
1028
1029     if (!mcasp->dat_port)
1030         busel = TXSEL;
1031
1032     if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1033         mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
1034         mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
1035         mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
1036                    FSXMOD(total_slots), FSXMOD(0x1FF));
1037     } else if (stream == SNDRV_PCM_STREAM_CAPTURE) {
1038         mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
1039         mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
1040         mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
1041                    FSRMOD(total_slots), FSRMOD(0x1FF));
1042         /*
1043          * If McASP is set to be TX/RX synchronous and the playback is
1044          * not running already we need to configure the TX slots in
1045          * order to have correct FSX on the bus
1046          */
1047         if (mcasp_is_synchronous(mcasp) && !mcasp->channels)
1048             mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
1049                        FSXMOD(total_slots), FSXMOD(0x1FF));
1050     }
1051
1052     return 0;
1053 }
1054
1055 /* S/PDIF */
1056 static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp,
1057                   unsigned int rate)
1058 {
1059     u8 *cs_bytes = (u8 *)&mcasp->iec958_status;
1060
1061     if (!mcasp->dat_port)
1062         mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSEL);
1063     else
1064         mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSEL);
1065
1066     /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
1067     mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
1068
1069     mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, 0xFFFF);
1070
1071     /* Set the TX tdm : for all the slots */
1072     mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
1073
1074     /* Set the TX clock controls : div = 1 and internal */
1075     mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
1076
1077     mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
1078
1079     /* Set S/PDIF channel status bits */
1080     cs_bytes[3] &= ~IEC958_AES3_CON_FS;
1081     switch (rate) {
1082     case 22050:
1083         cs_bytes[3] |= IEC958_AES3_CON_FS_22050;
1084         break;
1085     case 24000:
1086         cs_bytes[3] |= IEC958_AES3_CON_FS_24000;
1087         break;
1088     case 32000:
1089         cs_bytes[3] |= IEC958_AES3_CON_FS_32000;
1090         break;
1091     case 44100:
1092         cs_bytes[3] |= IEC958_AES3_CON_FS_44100;
1093         break;
1094     case 48000:
1095         cs_bytes[3] |= IEC958_AES3_CON_FS_48000;
1096         break;
1097     case 88200:
1098         cs_bytes[3] |= IEC958_AES3_CON_FS_88200;
1099         break;
1100     case 96000:
1101         cs_bytes[3] |= IEC958_AES3_CON_FS_96000;
1102         break;
1103     case 176400:
1104         cs_bytes[3] |= IEC958_AES3_CON_FS_176400;
1105         break;
1106     case 192000:
1107         cs_bytes[3] |= IEC958_AES3_CON_FS_192000;
1108         break;
1109     default:
1110         dev_err(mcasp->dev, "unsupported sampling rate: %d\n", rate);
1111         return -EINVAL;
1112     }
1113
1114     mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, mcasp->iec958_status);
1115     mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, mcasp->iec958_status);
1116
1117     /* Enable the DIT */
1118     mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
1119
1120     return 0;
1121 }
1122
1123 static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp,
1124                       unsigned int sysclk_freq,
1125                       unsigned int bclk_freq, bool set)
1126 {
1127     u32 reg = mcasp_get_reg(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG);
1128     int div = sysclk_freq / bclk_freq;
1129     int rem = sysclk_freq % bclk_freq;
1130     int error_ppm;
1131     int aux_div = 1;
1132
1133     if (div > (ACLKXDIV_MASK + 1)) {
1134         if (reg & AHCLKXE) {
1135             aux_div = div / (ACLKXDIV_MASK + 1);
1136             if (div % (ACLKXDIV_MASK + 1))
1137                 aux_div++;
1138
1139             sysclk_freq /= aux_div;
1140             div = sysclk_freq / bclk_freq;
1141             rem = sysclk_freq % bclk_freq;
1142         } else if (set) {
1143             dev_warn(mcasp->dev, "Too fast reference clock (%u)\n",
1144                  sysclk_freq);
1145         }
1146     }
1147
1148     if (rem != 0) {
1149         if (div == 0 ||
1150             ((sysclk_freq / div) - bclk_freq) >
1151             (bclk_freq - (sysclk_freq / (div+1)))) {
1152             div++;
1153             rem = rem - bclk_freq;
1154         }
1155     }
1156     error_ppm = (div*1000000 + (int)div64_long(1000000LL*rem,
1157              (int)bclk_freq)) / div - 1000000;
1158
1159     if (set) {
1160         if (error_ppm)
1161             dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n",
1162                  error_ppm);
1163
1164         __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_BCLK, div, 0);
1165         if (reg & AHCLKXE)
1166             __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_AUXCLK,
1167                            aux_div, 0);
1168     }
1169
1170     return error_ppm;
1171 }
1172
1173 static inline u32 davinci_mcasp_tx_delay(struct davinci_mcasp *mcasp)
1174 {
1175     if (!mcasp->txnumevt)
1176         return 0;
1177
1178     return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_WFIFOSTS_OFFSET);
1179 }
1180
1181 static inline u32 davinci_mcasp_rx_delay(struct davinci_mcasp *mcasp)
1182 {
1183     if (!mcasp->rxnumevt)
1184         return 0;
1185
1186     return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_RFIFOSTS_OFFSET);
1187 }
1188
1189 static snd_pcm_sframes_t davinci_mcasp_delay(
1190             struct snd_pcm_substream *substream,
1191             struct snd_soc_dai *cpu_dai)
1192 {
1193     struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1194     u32 fifo_use;
1195
1196     if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1197         fifo_use = davinci_mcasp_tx_delay(mcasp);
1198     else
1199         fifo_use = davinci_mcasp_rx_delay(mcasp);
1200
1201     /*
1202      * Divide the used locations with the channel count to get the
1203      * FIFO usage in samples (don't care about partial samples in the
1204      * buffer).
1205      */
1206     return fifo_use / substream->runtime->channels;
1207 }
1208
1209 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
1210                     struct snd_pcm_hw_params *params,
1211                     struct snd_soc_dai *cpu_dai)
1212 {
1213     struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1214     int word_length;
1215     int channels = params_channels(params);
1216     int period_size = params_period_size(params);
1217     int ret;
1218
1219     switch (params_format(params)) {
1220     case SNDRV_PCM_FORMAT_U8:
1221     case SNDRV_PCM_FORMAT_S8:
1222         word_length = 8;
1223         break;
1224
1225     case SNDRV_PCM_FORMAT_U16_LE:
1226     case SNDRV_PCM_FORMAT_S16_LE:
1227         word_length = 16;
1228         break;
1229
1230     case SNDRV_PCM_FORMAT_U24_3LE:
1231     case SNDRV_PCM_FORMAT_S24_3LE:
1232         word_length = 24;
1233         break;
1234
1235     case SNDRV_PCM_FORMAT_U24_LE:
1236     case SNDRV_PCM_FORMAT_S24_LE:
1237         word_length = 24;
1238         break;
1239
1240     case SNDRV_PCM_FORMAT_U32_LE:
1241     case SNDRV_PCM_FORMAT_S32_LE:
1242         word_length = 32;
1243         break;
1244
1245     default:
1246         printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
1247         return -EINVAL;
1248     }
1249
1250     ret = davinci_mcasp_set_dai_fmt(cpu_dai, mcasp->dai_fmt);
1251     if (ret)
1252         return ret;
1253
1254     /*
1255      * If mcasp is BCLK master, and a BCLK divider was not provided by
1256      * the machine driver, we need to calculate the ratio.
1257      */
1258     if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1259         int slots = mcasp->tdm_slots;
1260         int rate = params_rate(params);
1261         int sbits = params_width(params);
1262         unsigned int bclk_target;
1263
1264         if (mcasp->slot_width)
1265             sbits = mcasp->slot_width;
1266
1267         if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE)
1268             bclk_target = rate * sbits * slots;
1269         else
1270             bclk_target = rate * 128;
1271
1272         davinci_mcasp_calc_clk_div(mcasp, mcasp->sysclk_freq,
1273                        bclk_target, true);
1274     }
1275
1276     ret = mcasp_common_hw_param(mcasp, substream->stream,
1277                     period_size * channels, channels);
1278     if (ret)
1279         return ret;
1280
1281     if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1282         ret = mcasp_dit_hw_param(mcasp, params_rate(params));
1283     else
1284         ret = mcasp_i2s_hw_param(mcasp, substream->stream,
1285                      channels);
1286
1287     if (ret)
1288         return ret;
1289
1290     davinci_config_channel_size(mcasp, word_length);
1291
1292     if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {
1293         mcasp->channels = channels;
1294         if (!mcasp->max_format_width)
1295             mcasp->max_format_width = word_length;
1296     }
1297
1298     return 0;
1299 }
1300
1301 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
1302                      int cmd, struct snd_soc_dai *cpu_dai)
1303 {
1304     struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1305     int ret = 0;
1306
1307     switch (cmd) {
1308     case SNDRV_PCM_TRIGGER_RESUME:
1309     case SNDRV_PCM_TRIGGER_START:
1310     case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1311         davinci_mcasp_start(mcasp, substream->stream);
1312         break;
1313     case SNDRV_PCM_TRIGGER_SUSPEND:
1314     case SNDRV_PCM_TRIGGER_STOP:
1315     case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1316         davinci_mcasp_stop(mcasp, substream->stream);
1317         break;
1318
1319     default:
1320         ret = -EINVAL;
1321     }
1322
1323     return ret;
1324 }
1325
1326 static int davinci_mcasp_hw_rule_slot_width(struct snd_pcm_hw_params *params,
1327                         struct snd_pcm_hw_rule *rule)
1328 {
1329     struct davinci_mcasp_ruledata *rd = rule->private;
1330     struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1331     struct snd_mask nfmt;
1332     int i, slot_width;
1333
1334     snd_mask_none(&nfmt);
1335     slot_width = rd->mcasp->slot_width;
1336
1337     for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) {
1338         if (snd_mask_test(fmt, i)) {
1339             if (snd_pcm_format_width(i) <= slot_width) {
1340                 snd_mask_set(&nfmt, i);
1341             }
1342         }
1343     }
1344
1345     return snd_mask_refine(fmt, &nfmt);
1346 }
1347
1348 static int davinci_mcasp_hw_rule_format_width(struct snd_pcm_hw_params *params,
1349                           struct snd_pcm_hw_rule *rule)
1350 {
1351     struct davinci_mcasp_ruledata *rd = rule->private;
1352     struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1353     struct snd_mask nfmt;
1354     int i, format_width;
1355
1356     snd_mask_none(&nfmt);
1357     format_width = rd->mcasp->max_format_width;
1358
1359     for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) {
1360         if (snd_mask_test(fmt, i)) {
1361             if (snd_pcm_format_width(i) == format_width) {
1362                 snd_mask_set(&nfmt, i);
1363             }
1364         }
1365     }
1366
1367     return snd_mask_refine(fmt, &nfmt);
1368 }
1369
1370 static const unsigned int davinci_mcasp_dai_rates[] = {
1371     8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000,
1372     88200, 96000, 176400, 192000,
1373 };
1374
1375 #define DAVINCI_MAX_RATE_ERROR_PPM 1000
1376
1377 static int davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params *params,
1378                       struct snd_pcm_hw_rule *rule)
1379 {
1380     struct davinci_mcasp_ruledata *rd = rule->private;
1381     struct snd_interval *ri =
1382         hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
1383     int sbits = params_width(params);
1384     int slots = rd->mcasp->tdm_slots;
1385     struct snd_interval range;
1386     int i;
1387
1388     if (rd->mcasp->slot_width)
1389         sbits = rd->mcasp->slot_width;
1390
1391     snd_interval_any(&range);
1392     range.empty = 1;
1393
1394     for (i = 0; i < ARRAY_SIZE(davinci_mcasp_dai_rates); i++) {
1395         if (snd_interval_test(ri, davinci_mcasp_dai_rates[i])) {
1396             uint bclk_freq = sbits * slots *
1397                      davinci_mcasp_dai_rates[i];
1398             unsigned int sysclk_freq;
1399             int ppm;
1400
1401             if (rd->mcasp->auxclk_fs_ratio)
1402                 sysclk_freq =  davinci_mcasp_dai_rates[i] *
1403                            rd->mcasp->auxclk_fs_ratio;
1404             else
1405                 sysclk_freq = rd->mcasp->sysclk_freq;
1406
1407             ppm = davinci_mcasp_calc_clk_div(rd->mcasp, sysclk_freq,
1408                              bclk_freq, false);
1409             if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1410                 if (range.empty) {
1411                     range.min = davinci_mcasp_dai_rates[i];
1412                     range.empty = 0;
1413                 }
1414                 range.max = davinci_mcasp_dai_rates[i];
1415             }
1416         }
1417     }
1418
1419     dev_dbg(rd->mcasp->dev,
1420         "Frequencies %d-%d -> %d-%d for %d sbits and %d tdm slots\n",
1421         ri->min, ri->max, range.min, range.max, sbits, slots);
1422
1423     return snd_interval_refine(hw_param_interval(params, rule->var),
1424                    &range);
1425 }
1426
1427 static int davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params *params,
1428                     struct snd_pcm_hw_rule *rule)
1429 {
1430     struct davinci_mcasp_ruledata *rd = rule->private;
1431     struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1432     struct snd_mask nfmt;
1433     int rate = params_rate(params);
1434     int slots = rd->mcasp->tdm_slots;
1435     int i, count = 0;
1436
1437     snd_mask_none(&nfmt);
1438
1439     for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) {
1440         if (snd_mask_test(fmt, i)) {
1441             uint sbits = snd_pcm_format_width(i);
1442             unsigned int sysclk_freq;
1443             int ppm;
1444
1445             if (rd->mcasp->auxclk_fs_ratio)
1446                 sysclk_freq =  rate *
1447                            rd->mcasp->auxclk_fs_ratio;
1448             else
1449                 sysclk_freq = rd->mcasp->sysclk_freq;
1450
1451             if (rd->mcasp->slot_width)
1452                 sbits = rd->mcasp->slot_width;
1453
1454             ppm = davinci_mcasp_calc_clk_div(rd->mcasp, sysclk_freq,
1455                              sbits * slots * rate,
1456                              false);
1457             if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1458                 snd_mask_set(&nfmt, i);
1459                 count++;
1460             }
1461         }
1462     }
1463     dev_dbg(rd->mcasp->dev,
1464         "%d possible sample format for %d Hz and %d tdm slots\n",
1465         count, rate, slots);
1466
1467     return snd_mask_refine(fmt, &nfmt);
1468 }
1469
1470 static int davinci_mcasp_hw_rule_min_periodsize(
1471         struct snd_pcm_hw_params *params, struct snd_pcm_hw_rule *rule)
1472 {
1473     struct snd_interval *period_size = hw_param_interval(params,
1474                         SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
1475     struct snd_interval frames;
1476
1477     snd_interval_any(&frames);
1478     frames.min = 64;
1479     frames.integer = 1;
1480
1481     return snd_interval_refine(period_size, &frames);
1482 }
1483
1484 static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
1485                  struct snd_soc_dai *cpu_dai)
1486 {
1487     struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1488     struct davinci_mcasp_ruledata *ruledata =
1489                     &mcasp->ruledata[substream->stream];
1490     u32 max_channels = 0;
1491     int i, dir, ret;
1492     int tdm_slots = mcasp->tdm_slots;
1493
1494     /* Do not allow more then one stream per direction */
1495     if (mcasp->substreams[substream->stream])
1496         return -EBUSY;
1497
1498     mcasp->substreams[substream->stream] = substream;
1499
1500     if (mcasp->tdm_mask[substream->stream])
1501         tdm_slots = hweight32(mcasp->tdm_mask[substream->stream]);
1502
1503     if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1504         return 0;
1505
1506     /*
1507      * Limit the maximum allowed channels for the first stream:
1508      * number of serializers for the direction * tdm slots per serializer
1509      */
1510     if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1511         dir = TX_MODE;
1512     else
1513         dir = RX_MODE;
1514
1515     for (i = 0; i < mcasp->num_serializer; i++) {
1516         if (mcasp->serial_dir[i] == dir)
1517             max_channels++;
1518     }
1519     ruledata->serializers = max_channels;
1520     ruledata->mcasp = mcasp;
1521     max_channels *= tdm_slots;
1522     /*
1523      * If the already active stream has less channels than the calculated
1524      * limit based on the seirializers * tdm_slots, and only one serializer
1525      * is in use we need to use that as a constraint for the second stream.
1526      * Otherwise (first stream or less allowed channels or more than one
1527      * serializer in use) we use the calculated constraint.
1528      */
1529     if (mcasp->channels && mcasp->channels < max_channels &&
1530         ruledata->serializers == 1)
1531         max_channels = mcasp->channels;
1532     /*
1533      * But we can always allow channels upto the amount of
1534      * the available tdm_slots.
1535      */
1536     if (max_channels < tdm_slots)
1537         max_channels = tdm_slots;
1538
1539     snd_pcm_hw_constraint_minmax(substream->runtime,
1540                      SNDRV_PCM_HW_PARAM_CHANNELS,
1541                      0, max_channels);
1542
1543     snd_pcm_hw_constraint_list(substream->runtime,
1544                    0, SNDRV_PCM_HW_PARAM_CHANNELS,
1545                    &mcasp->chconstr[substream->stream]);
1546
1547     if (mcasp->max_format_width) {
1548         /*
1549          * Only allow formats which require same amount of bits on the
1550          * bus as the currently running stream
1551          */
1552         ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1553                       SNDRV_PCM_HW_PARAM_FORMAT,
1554                       davinci_mcasp_hw_rule_format_width,
1555                       ruledata,
1556                       SNDRV_PCM_HW_PARAM_FORMAT, -1);
1557         if (ret)
1558             return ret;
1559     }
1560     else if (mcasp->slot_width) {
1561         /* Only allow formats require <= slot_width bits on the bus */
1562         ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1563                       SNDRV_PCM_HW_PARAM_FORMAT,
1564                       davinci_mcasp_hw_rule_slot_width,
1565                       ruledata,
1566                       SNDRV_PCM_HW_PARAM_FORMAT, -1);
1567         if (ret)
1568             return ret;
1569     }
1570
1571     /*
1572      * If we rely on implicit BCLK divider setting we should
1573      * set constraints based on what we can provide.
1574      */
1575     if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1576         ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1577                       SNDRV_PCM_HW_PARAM_RATE,
1578                       davinci_mcasp_hw_rule_rate,
1579                       ruledata,
1580                       SNDRV_PCM_HW_PARAM_FORMAT, -1);
1581         if (ret)
1582             return ret;
1583         ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1584                       SNDRV_PCM_HW_PARAM_FORMAT,
1585                       davinci_mcasp_hw_rule_format,
1586                       ruledata,
1587                       SNDRV_PCM_HW_PARAM_RATE, -1);
1588         if (ret)
1589             return ret;
1590     }
1591
1592     snd_pcm_hw_rule_add(substream->runtime, 0,
1593                 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
1594                 davinci_mcasp_hw_rule_min_periodsize, NULL,
1595                 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, -1);
1596
1597     return 0;
1598 }
1599
1600 static void davinci_mcasp_shutdown(struct snd_pcm_substream *substream,
1601                    struct snd_soc_dai *cpu_dai)
1602 {
1603     struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1604
1605     mcasp->substreams[substream->stream] = NULL;
1606     mcasp->active_serializers[substream->stream] = 0;
1607
1608     if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1609         return;
1610
1611     if (!snd_soc_dai_active(cpu_dai)) {
1612         mcasp->channels = 0;
1613         mcasp->max_format_width = 0;
1614     }
1615 }
1616
1617 static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
1618     .startup    = davinci_mcasp_startup,
1619     .shutdown   = davinci_mcasp_shutdown,
1620     .trigger    = davinci_mcasp_trigger,
1621     .delay      = davinci_mcasp_delay,
1622     .hw_params  = davinci_mcasp_hw_params,
1623     .set_fmt    = davinci_mcasp_set_dai_fmt,
1624     .set_clkdiv = davinci_mcasp_set_clkdiv,
1625     .set_sysclk = davinci_mcasp_set_sysclk,
1626     .set_tdm_slot   = davinci_mcasp_set_tdm_slot,
1627 };
1628
1629 static int davinci_mcasp_iec958_info(struct snd_kcontrol *kcontrol,
1630                      struct snd_ctl_elem_info *uinfo)
1631 {
1632     uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1633     uinfo->count = 1;
1634
1635     return 0;
1636 }
1637
1638 static int davinci_mcasp_iec958_get(struct snd_kcontrol *kcontrol,
1639                     struct snd_ctl_elem_value *uctl)
1640 {
1641     struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
1642     struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1643
1644     memcpy(uctl->value.iec958.status, &mcasp->iec958_status,
1645            sizeof(mcasp->iec958_status));
1646
1647     return 0;
1648 }
1649
1650 static int davinci_mcasp_iec958_put(struct snd_kcontrol *kcontrol,
1651                     struct snd_ctl_elem_value *uctl)
1652 {
1653     struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
1654     struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1655
1656     memcpy(&mcasp->iec958_status, uctl->value.iec958.status,
1657            sizeof(mcasp->iec958_status));
1658
1659     return 0;
1660 }
1661
1662 static int davinci_mcasp_iec958_con_mask_get(struct snd_kcontrol *kcontrol,
1663                          struct snd_ctl_elem_value *ucontrol)
1664 {
1665     struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
1666     struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1667
1668     memset(ucontrol->value.iec958.status, 0xff, sizeof(mcasp->iec958_status));
1669     return 0;
1670 }
1671
1672 static const struct snd_kcontrol_new davinci_mcasp_iec958_ctls[] = {
1673     {
1674         .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
1675                SNDRV_CTL_ELEM_ACCESS_VOLATILE),
1676         .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1677         .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
1678         .info = davinci_mcasp_iec958_info,
1679         .get = davinci_mcasp_iec958_get,
1680         .put = davinci_mcasp_iec958_put,
1681     }, {
1682         .access = SNDRV_CTL_ELEM_ACCESS_READ,
1683         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1684         .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK),
1685         .info = davinci_mcasp_iec958_info,
1686         .get = davinci_mcasp_iec958_con_mask_get,
1687     },
1688 };
1689
1690 static void davinci_mcasp_init_iec958_status(struct davinci_mcasp *mcasp)
1691 {
1692     unsigned char *cs = (u8 *)&mcasp->iec958_status;
1693
1694     cs[0] = IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_NONE;
1695     cs[1] = IEC958_AES1_CON_PCM_CODER;
1696     cs[2] = IEC958_AES2_CON_SOURCE_UNSPEC | IEC958_AES2_CON_CHANNEL_UNSPEC;
1697     cs[3] = IEC958_AES3_CON_CLOCK_1000PPM;
1698 }
1699
1700 static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai)
1701 {
1702     struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1703
1704     dai->playback_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
1705     dai->capture_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
1706
1707     if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) {
1708         davinci_mcasp_init_iec958_status(mcasp);
1709         snd_soc_add_dai_controls(dai, davinci_mcasp_iec958_ctls,
1710                      ARRAY_SIZE(davinci_mcasp_iec958_ctls));
1711     }
1712
1713     return 0;
1714 }
1715
1716 #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000
1717
1718 #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
1719                 SNDRV_PCM_FMTBIT_U8 | \
1720                 SNDRV_PCM_FMTBIT_S16_LE | \
1721                 SNDRV_PCM_FMTBIT_U16_LE | \
1722                 SNDRV_PCM_FMTBIT_S24_LE | \
1723                 SNDRV_PCM_FMTBIT_U24_LE | \
1724                 SNDRV_PCM_FMTBIT_S24_3LE | \
1725                 SNDRV_PCM_FMTBIT_U24_3LE | \
1726                 SNDRV_PCM_FMTBIT_S32_LE | \
1727                 SNDRV_PCM_FMTBIT_U32_LE)
1728
1729 static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
1730     {
1731         .name       = "davinci-mcasp.0",
1732         .probe      = davinci_mcasp_dai_probe,
1733         .playback   = {
1734             .stream_name = "IIS Playback",
1735             .channels_min   = 1,
1736             .channels_max   = 32 * 16,
1737             .rates      = DAVINCI_MCASP_RATES,
1738             .formats    = DAVINCI_MCASP_PCM_FMTS,
1739         },
1740         .capture    = {
1741             .stream_name = "IIS Capture",
1742             .channels_min   = 1,
1743             .channels_max   = 32 * 16,
1744             .rates      = DAVINCI_MCASP_RATES,
1745             .formats    = DAVINCI_MCASP_PCM_FMTS,
1746         },
1747         .ops        = &davinci_mcasp_dai_ops,
1748
1749         .symmetric_rate     = 1,
1750     },
1751     {
1752         .name       = "davinci-mcasp.1",
1753         .probe      = davinci_mcasp_dai_probe,
1754         .playback   = {
1755             .stream_name = "DIT Playback",
1756             .channels_min   = 1,
1757             .channels_max   = 384,
1758             .rates      = DAVINCI_MCASP_RATES,
1759             .formats    = SNDRV_PCM_FMTBIT_S16_LE |
1760                       SNDRV_PCM_FMTBIT_S24_LE,
1761         },
1762         .ops        = &davinci_mcasp_dai_ops,
1763     },
1764
1765 };
1766
1767 static const struct snd_soc_component_driver davinci_mcasp_component = {
1768     .name           = "davinci-mcasp",
1769     .legacy_dai_naming  = 1,
1770 };
1771
1772 /* Some HW specific values and defaults. The rest is filled in from DT. */
1773 static struct davinci_mcasp_pdata dm646x_mcasp_pdata = {
1774     .tx_dma_offset = 0x400,
1775     .rx_dma_offset = 0x400,
1776     .version = MCASP_VERSION_1,
1777 };
1778
1779 static struct davinci_mcasp_pdata da830_mcasp_pdata = {
1780     .tx_dma_offset = 0x2000,
1781     .rx_dma_offset = 0x2000,
1782     .version = MCASP_VERSION_2,
1783 };
1784
1785 static struct davinci_mcasp_pdata am33xx_mcasp_pdata = {
1786     .tx_dma_offset = 0,
1787     .rx_dma_offset = 0,
1788     .version = MCASP_VERSION_3,
1789 };
1790
1791 static struct davinci_mcasp_pdata dra7_mcasp_pdata = {
1792     /* The CFG port offset will be calculated if it is needed */
1793     .tx_dma_offset = 0,
1794     .rx_dma_offset = 0,
1795     .version = MCASP_VERSION_4,
1796 };
1797
1798 static struct davinci_mcasp_pdata omap_mcasp_pdata = {
1799     .tx_dma_offset = 0x200,
1800     .rx_dma_offset = 0,
1801     .version = MCASP_VERSION_OMAP,
1802 };
1803
1804 static const struct of_device_id mcasp_dt_ids[] = {
1805     {
1806         .compatible = "ti,dm646x-mcasp-audio",
1807         .data = &dm646x_mcasp_pdata,
1808     },
1809     {
1810         .compatible = "ti,da830-mcasp-audio",
1811         .data = &da830_mcasp_pdata,
1812     },
1813     {
1814         .compatible = "ti,am33xx-mcasp-audio",
1815         .data = &am33xx_mcasp_pdata,
1816     },
1817     {
1818         .compatible = "ti,dra7-mcasp-audio",
1819         .data = &dra7_mcasp_pdata,
1820     },
1821     {
1822         .compatible = "ti,omap4-mcasp-audio",
1823         .data = &omap_mcasp_pdata,
1824     },
1825     { /* sentinel */ }
1826 };
1827 MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
1828
1829 static int mcasp_reparent_fck(struct platform_device *pdev)
1830 {
1831     struct device_node *node = pdev->dev.of_node;
1832     struct clk *gfclk, *parent_clk;
1833     const char *parent_name;
1834     int ret;
1835
1836     if (!node)
1837         return 0;
1838
1839     parent_name = of_get_property(node, "fck_parent", NULL);
1840     if (!parent_name)
1841         return 0;
1842
1843     dev_warn(&pdev->dev, "Update the bindings to use assigned-clocks!\n");
1844
1845     gfclk = clk_get(&pdev->dev, "fck");
1846     if (IS_ERR(gfclk)) {
1847         dev_err(&pdev->dev, "failed to get fck\n");
1848         return PTR_ERR(gfclk);
1849     }
1850
1851     parent_clk = clk_get(NULL, parent_name);
1852     if (IS_ERR(parent_clk)) {
1853         dev_err(&pdev->dev, "failed to get parent clock\n");
1854         ret = PTR_ERR(parent_clk);
1855         goto err1;
1856     }
1857
1858     ret = clk_set_parent(gfclk, parent_clk);
1859     if (ret) {
1860         dev_err(&pdev->dev, "failed to reparent fck\n");
1861         goto err2;
1862     }
1863
1864 err2:
1865     clk_put(parent_clk);
1866 err1:
1867     clk_put(gfclk);
1868     return ret;
1869 }
1870
1871 static bool davinci_mcasp_have_gpiochip(struct davinci_mcasp *mcasp)
1872 {
1873 #ifdef CONFIG_OF_GPIO
1874     return of_property_read_bool(mcasp->dev->of_node, "gpio-controller");
1875 #else
1876     return false;
1877 #endif
1878 }
1879
1880 static int davinci_mcasp_get_config(struct davinci_mcasp *mcasp,
1881                     struct platform_device *pdev)
1882 {
1883     const struct of_device_id *match = of_match_device(mcasp_dt_ids, &pdev->dev);
1884     struct device_node *np = pdev->dev.of_node;
1885     struct davinci_mcasp_pdata *pdata = NULL;
1886     const u32 *of_serial_dir32;
1887     u32 val;
1888     int i;
1889
1890     if (pdev->dev.platform_data) {
1891         pdata = pdev->dev.platform_data;
1892         pdata->dismod = DISMOD_LOW;
1893         goto out;
1894     } else if (match) {
1895         pdata = devm_kmemdup(&pdev->dev, match->data, sizeof(*pdata),
1896                      GFP_KERNEL);
1897         if (!pdata)
1898             return -ENOMEM;
1899     } else {
1900         dev_err(&pdev->dev, "No compatible match found\n");
1901         return -EINVAL;
1902     }
1903
1904     if (of_property_read_u32(np, "op-mode", &val) == 0) {
1905         pdata->op_mode = val;
1906     } else {
1907         mcasp->missing_audio_param = true;
1908         goto out;
1909     }
1910
1911     if (of_property_read_u32(np, "tdm-slots", &val) == 0) {
1912         if (val < 2 || val > 32) {
1913             dev_err(&pdev->dev, "tdm-slots must be in rage [2-32]\n");
1914             return -EINVAL;
1915         }
1916
1917         pdata->tdm_slots = val;
1918     } else if (pdata->op_mode == DAVINCI_MCASP_IIS_MODE) {
1919         mcasp->missing_audio_param = true;
1920         goto out;
1921     }
1922
1923     of_serial_dir32 = of_get_property(np, "serial-dir", &val);
1924     val /= sizeof(u32);
1925     if (of_serial_dir32) {
1926         u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
1927                          (sizeof(*of_serial_dir) * val),
1928                          GFP_KERNEL);
1929         if (!of_serial_dir)
1930             return -ENOMEM;
1931
1932         for (i = 0; i < val; i++)
1933             of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
1934
1935         pdata->num_serializer = val;
1936         pdata->serial_dir = of_serial_dir;
1937     } else {
1938         mcasp->missing_audio_param = true;
1939         goto out;
1940     }
1941
1942     if (of_property_read_u32(np, "tx-num-evt", &val) == 0)
1943         pdata->txnumevt = val;
1944
1945     if (of_property_read_u32(np, "rx-num-evt", &val) == 0)
1946         pdata->rxnumevt = val;
1947
1948     if (of_property_read_u32(np, "auxclk-fs-ratio", &val) == 0)
1949         mcasp->auxclk_fs_ratio = val;
1950
1951     if (of_property_read_u32(np, "dismod", &val) == 0) {
1952         if (val == 0 || val == 2 || val == 3) {
1953             pdata->dismod = DISMOD_VAL(val);
1954         } else {
1955             dev_warn(&pdev->dev, "Invalid dismod value: %u\n", val);
1956             pdata->dismod = DISMOD_LOW;
1957         }
1958     } else {
1959         pdata->dismod = DISMOD_LOW;
1960     }
1961
1962 out:
1963     mcasp->pdata = pdata;
1964
1965     if (mcasp->missing_audio_param) {
1966         if (davinci_mcasp_have_gpiochip(mcasp)) {
1967             dev_dbg(&pdev->dev, "Missing DT parameter(s) for audio\n");
1968             return 0;
1969         }
1970
1971         dev_err(&pdev->dev, "Insufficient DT parameter(s)\n");
1972         return -ENODEV;
1973     }
1974
1975     mcasp->op_mode = pdata->op_mode;
1976     /* sanity check for tdm slots parameter */
1977     if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {
1978         if (pdata->tdm_slots < 2) {
1979             dev_warn(&pdev->dev, "invalid tdm slots: %d\n",
1980                  pdata->tdm_slots);
1981             mcasp->tdm_slots = 2;
1982         } else if (pdata->tdm_slots > 32) {
1983             dev_warn(&pdev->dev, "invalid tdm slots: %d\n",
1984                  pdata->tdm_slots);
1985             mcasp->tdm_slots = 32;
1986         } else {
1987             mcasp->tdm_slots = pdata->tdm_slots;
1988         }
1989     } else {
1990         mcasp->tdm_slots = 32;
1991     }
1992
1993     mcasp->num_serializer = pdata->num_serializer;
1994 #ifdef CONFIG_PM
1995     mcasp->context.xrsr_regs = devm_kcalloc(&pdev->dev,
1996                         mcasp->num_serializer, sizeof(u32),
1997                         GFP_KERNEL);
1998     if (!mcasp->context.xrsr_regs)
1999         return -ENOMEM;
2000 #endif
2001     mcasp->serial_dir = pdata->serial_dir;
2002     mcasp->version = pdata->version;
2003     mcasp->txnumevt = pdata->txnumevt;
2004     mcasp->rxnumevt = pdata->rxnumevt;
2005     mcasp->dismod = pdata->dismod;
2006
2007     return 0;
2008 }
2009
2010 enum {
2011     PCM_EDMA,
2012     PCM_SDMA,
2013     PCM_UDMA,
2014 };
2015 static const char *sdma_prefix = "ti,omap";
2016
2017 static int davinci_mcasp_get_dma_type(struct davinci_mcasp *mcasp)
2018 {
2019     struct dma_chan *chan;
2020     const char *tmp;
2021     int ret = PCM_EDMA;
2022
2023     if (!mcasp->dev->of_node)
2024         return PCM_EDMA;
2025
2026     tmp = mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data;
2027     chan = dma_request_chan(mcasp->dev, tmp);
2028     if (IS_ERR(chan))
2029         return dev_err_probe(mcasp->dev, PTR_ERR(chan),
2030                      "Can't verify DMA configuration\n");
2031     if (WARN_ON(!chan->device || !chan->device->dev)) {
2032         dma_release_channel(chan);
2033         return -EINVAL;
2034     }
2035
2036     if (chan->device->dev->of_node)
2037         ret = of_property_read_string(chan->device->dev->of_node,
2038                           "compatible", &tmp);
2039     else
2040         dev_dbg(mcasp->dev, "DMA controller has no of-node\n");
2041
2042     dma_release_channel(chan);
2043     if (ret)
2044         return ret;
2045
2046     dev_dbg(mcasp->dev, "DMA controller compatible = \"%s\"\n", tmp);
2047     if (!strncmp(tmp, sdma_prefix, strlen(sdma_prefix)))
2048         return PCM_SDMA;
2049     else if (strstr(tmp, "udmap"))
2050         return PCM_UDMA;
2051     else if (strstr(tmp, "bcdma"))
2052         return PCM_UDMA;
2053
2054     return PCM_EDMA;
2055 }
2056
2057 static u32 davinci_mcasp_txdma_offset(struct davinci_mcasp_pdata *pdata)
2058 {
2059     int i;
2060     u32 offset = 0;
2061
2062     if (pdata->version != MCASP_VERSION_4)
2063         return pdata->tx_dma_offset;
2064
2065     for (i = 0; i < pdata->num_serializer; i++) {
2066         if (pdata->serial_dir[i] == TX_MODE) {
2067             if (!offset) {
2068                 offset = DAVINCI_MCASP_TXBUF_REG(i);
2069             } else {
2070                 pr_err("%s: Only one serializer allowed!\n",
2071                        __func__);
2072                 break;
2073             }
2074         }
2075     }
2076
2077     return offset;
2078 }
2079
2080 static u32 davinci_mcasp_rxdma_offset(struct davinci_mcasp_pdata *pdata)
2081 {
2082     int i;
2083     u32 offset = 0;
2084
2085     if (pdata->version != MCASP_VERSION_4)
2086         return pdata->rx_dma_offset;
2087
2088     for (i = 0; i < pdata->num_serializer; i++) {
2089         if (pdata->serial_dir[i] == RX_MODE) {
2090             if (!offset) {
2091                 offset = DAVINCI_MCASP_RXBUF_REG(i);
2092             } else {
2093                 pr_err("%s: Only one serializer allowed!\n",
2094                        __func__);
2095                 break;
2096             }
2097         }
2098     }
2099
2100     return offset;
2101 }
2102
2103 #ifdef CONFIG_GPIOLIB
2104 static int davinci_mcasp_gpio_request(struct gpio_chip *chip, unsigned offset)
2105 {
2106     struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2107
2108     if (mcasp->num_serializer && offset < mcasp->num_serializer &&
2109         mcasp->serial_dir[offset] != INACTIVE_MODE) {
2110         dev_err(mcasp->dev, "AXR%u pin is  used for audio\n", offset);
2111         return -EBUSY;
2112     }
2113
2114     /* Do not change the PIN yet */
2115     return pm_runtime_resume_and_get(mcasp->dev);
2116 }
2117
2118 static void davinci_mcasp_gpio_free(struct gpio_chip *chip, unsigned offset)
2119 {
2120     struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2121
2122     /* Set the direction to input */
2123     mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset));
2124
2125     /* Set the pin as McASP pin */
2126     mcasp_clr_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset));
2127
2128     pm_runtime_put_sync(mcasp->dev);
2129 }
2130
2131 static int davinci_mcasp_gpio_direction_out(struct gpio_chip *chip,
2132                         unsigned offset, int value)
2133 {
2134     struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2135     u32 val;
2136
2137     if (value)
2138         mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
2139     else
2140         mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
2141
2142     val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG);
2143     if (!(val & BIT(offset))) {
2144         /* Set the pin as GPIO pin */
2145         mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset));
2146
2147         /* Set the direction to output */
2148         mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset));
2149     }
2150
2151     return 0;
2152 }
2153
2154 static void davinci_mcasp_gpio_set(struct gpio_chip *chip, unsigned offset,
2155                   int value)
2156 {
2157     struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2158
2159     if (value)
2160         mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
2161     else
2162         mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
2163 }
2164
2165 static int davinci_mcasp_gpio_direction_in(struct gpio_chip *chip,
2166                        unsigned offset)
2167 {
2168     struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2169     u32 val;
2170
2171     val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG);
2172     if (!(val & BIT(offset))) {
2173         /* Set the direction to input */
2174         mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset));
2175
2176         /* Set the pin as GPIO pin */
2177         mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset));
2178     }
2179
2180     return 0;
2181 }
2182
2183 static int davinci_mcasp_gpio_get(struct gpio_chip *chip, unsigned offset)
2184 {
2185     struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2186     u32 val;
2187
2188     val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDSET_REG);
2189     if (val & BIT(offset))
2190         return 1;
2191
2192     return 0;
2193 }
2194
2195 static int davinci_mcasp_gpio_get_direction(struct gpio_chip *chip,
2196                         unsigned offset)
2197 {
2198     struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2199     u32 val;
2200
2201     val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDIR_REG);
2202     if (val & BIT(offset))
2203         return 0;
2204
2205     return 1;
2206 }
2207
2208 static const struct gpio_chip davinci_mcasp_template_chip = {
2209     .owner          = THIS_MODULE,
2210     .request        = davinci_mcasp_gpio_request,
2211     .free           = davinci_mcasp_gpio_free,
2212     .direction_output   = davinci_mcasp_gpio_direction_out,
2213     .set            = davinci_mcasp_gpio_set,
2214     .direction_input    = davinci_mcasp_gpio_direction_in,
2215     .get            = davinci_mcasp_gpio_get,
2216     .get_direction      = davinci_mcasp_gpio_get_direction,
2217     .base           = -1,
2218     .ngpio          = 32,
2219 };
2220
2221 static int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp)
2222 {
2223     if (!davinci_mcasp_have_gpiochip(mcasp))
2224         return 0;
2225
2226     mcasp->gpio_chip = davinci_mcasp_template_chip;
2227     mcasp->gpio_chip.label = dev_name(mcasp->dev);
2228     mcasp->gpio_chip.parent = mcasp->dev;
2229
2230     return devm_gpiochip_add_data(mcasp->dev, &mcasp->gpio_chip, mcasp);
2231 }
2232
2233 #else /* CONFIG_GPIOLIB */
2234 static inline int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp)
2235 {
2236     return 0;
2237 }
2238 #endif /* CONFIG_GPIOLIB */
2239
2240 static int davinci_mcasp_probe(struct platform_device *pdev)
2241 {
2242     struct snd_dmaengine_dai_dma_data *dma_data;
2243     struct resource *mem, *dat;
2244     struct davinci_mcasp *mcasp;
2245     char *irq_name;
2246     int irq;
2247     int ret;
2248
2249     if (!pdev->dev.platform_data && !pdev->dev.of_node) {
2250         dev_err(&pdev->dev, "No platform data supplied\n");
2251         return -EINVAL;
2252     }
2253
2254     mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
2255                GFP_KERNEL);
2256     if (!mcasp)
2257         return  -ENOMEM;
2258
2259     mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
2260     if (!mem) {
2261         dev_warn(&pdev->dev,
2262              "\"mpu\" mem resource not found, using index 0\n");
2263         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2264         if (!mem) {
2265             dev_err(&pdev->dev, "no mem resource?\n");
2266             return -ENODEV;
2267         }
2268     }
2269
2270     mcasp->base = devm_ioremap_resource(&pdev->dev, mem);
2271     if (IS_ERR(mcasp->base))
2272         return PTR_ERR(mcasp->base);
2273
2274     dev_set_drvdata(&pdev->dev, mcasp);
2275     pm_runtime_enable(&pdev->dev);
2276
2277     mcasp->dev = &pdev->dev;
2278     ret = davinci_mcasp_get_config(mcasp, pdev);
2279     if (ret)
2280         goto err;
2281
2282     /* All PINS as McASP */
2283     pm_runtime_get_sync(mcasp->dev);
2284     mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
2285     pm_runtime_put(mcasp->dev);
2286
2287     /* Skip audio related setup code if the configuration is not adequat */
2288     if (mcasp->missing_audio_param)
2289         goto no_audio;
2290
2291     irq = platform_get_irq_byname_optional(pdev, "common");
2292     if (irq > 0) {
2293         irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_common",
2294                       dev_name(&pdev->dev));
2295         if (!irq_name) {
2296             ret = -ENOMEM;
2297             goto err;
2298         }
2299         ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
2300                         davinci_mcasp_common_irq_handler,
2301                         IRQF_ONESHOT | IRQF_SHARED,
2302                         irq_name, mcasp);
2303         if (ret) {
2304             dev_err(&pdev->dev, "common IRQ request failed\n");
2305             goto err;
2306         }
2307
2308         mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
2309         mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
2310     }
2311
2312     irq = platform_get_irq_byname_optional(pdev, "rx");
2313     if (irq > 0) {
2314         irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx",
2315                       dev_name(&pdev->dev));
2316         if (!irq_name) {
2317             ret = -ENOMEM;
2318             goto err;
2319         }
2320         ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
2321                         davinci_mcasp_rx_irq_handler,
2322                         IRQF_ONESHOT, irq_name, mcasp);
2323         if (ret) {
2324             dev_err(&pdev->dev, "RX IRQ request failed\n");
2325             goto err;
2326         }
2327
2328         mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
2329     }
2330
2331     irq = platform_get_irq_byname_optional(pdev, "tx");
2332     if (irq > 0) {
2333         irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx",
2334                       dev_name(&pdev->dev));
2335         if (!irq_name) {
2336             ret = -ENOMEM;
2337             goto err;
2338         }
2339         ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
2340                         davinci_mcasp_tx_irq_handler,
2341                         IRQF_ONESHOT, irq_name, mcasp);
2342         if (ret) {
2343             dev_err(&pdev->dev, "TX IRQ request failed\n");
2344             goto err;
2345         }
2346
2347         mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
2348     }
2349
2350     dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
2351     if (dat)
2352         mcasp->dat_port = true;
2353
2354     dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
2355     dma_data->filter_data = "tx";
2356     if (dat) {
2357         dma_data->addr = dat->start;
2358         /*
2359          * According to the TRM there should be 0x200 offset added to
2360          * the DAT port address
2361          */
2362         if (mcasp->version == MCASP_VERSION_OMAP)
2363             dma_data->addr += davinci_mcasp_txdma_offset(mcasp->pdata);
2364     } else {
2365         dma_data->addr = mem->start + davinci_mcasp_txdma_offset(mcasp->pdata);
2366     }
2367
2368
2369     /* RX is not valid in DIT mode */
2370     if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
2371         dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
2372         dma_data->filter_data = "rx";
2373         if (dat)
2374             dma_data->addr = dat->start;
2375         else
2376             dma_data->addr =
2377                 mem->start + davinci_mcasp_rxdma_offset(mcasp->pdata);
2378     }
2379
2380     if (mcasp->version < MCASP_VERSION_3) {
2381         mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
2382         /* dma_params->dma_addr is pointing to the data port address */
2383         mcasp->dat_port = true;
2384     } else {
2385         mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
2386     }
2387
2388     /* Allocate memory for long enough list for all possible
2389      * scenarios. Maximum number tdm slots is 32 and there cannot
2390      * be more serializers than given in the configuration.  The
2391      * serializer directions could be taken into account, but it
2392      * would make code much more complex and save only couple of
2393      * bytes.
2394      */
2395     mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list =
2396         devm_kcalloc(mcasp->dev,
2397                  32 + mcasp->num_serializer - 1,
2398                  sizeof(unsigned int),
2399                  GFP_KERNEL);
2400
2401     mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list =
2402         devm_kcalloc(mcasp->dev,
2403                  32 + mcasp->num_serializer - 1,
2404                  sizeof(unsigned int),
2405                  GFP_KERNEL);
2406
2407     if (!mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list ||
2408         !mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list) {
2409         ret = -ENOMEM;
2410         goto err;
2411     }
2412
2413     ret = davinci_mcasp_set_ch_constraints(mcasp);
2414     if (ret)
2415         goto err;
2416
2417     mcasp_reparent_fck(pdev);
2418
2419     ret = devm_snd_soc_register_component(&pdev->dev, &davinci_mcasp_component,
2420                           &davinci_mcasp_dai[mcasp->op_mode], 1);
2421
2422     if (ret != 0)
2423         goto err;
2424
2425     ret = davinci_mcasp_get_dma_type(mcasp);
2426     switch (ret) {
2427     case PCM_EDMA:
2428         ret = edma_pcm_platform_register(&pdev->dev);
2429         break;
2430     case PCM_SDMA:
2431         if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE)
2432             ret = sdma_pcm_platform_register(&pdev->dev, "tx", "rx");
2433         else
2434             ret = sdma_pcm_platform_register(&pdev->dev, "tx", NULL);
2435         break;
2436     case PCM_UDMA:
2437         ret = udma_pcm_platform_register(&pdev->dev);
2438         break;
2439     default:
2440         dev_err(&pdev->dev, "No DMA controller found (%d)\n", ret);
2441         fallthrough;
2442     case -EPROBE_DEFER:
2443         goto err;
2444     }
2445
2446     if (ret) {
2447         dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
2448         goto err;
2449     }
2450
2451 no_audio:
2452     ret = davinci_mcasp_init_gpiochip(mcasp);
2453     if (ret) {
2454         dev_err(&pdev->dev, "gpiochip registration failed: %d\n", ret);
2455         goto err;
2456     }
2457
2458     return 0;
2459 err:
2460     pm_runtime_disable(&pdev->dev);
2461     return ret;
2462 }
2463
2464 static int davinci_mcasp_remove(struct platform_device *pdev)
2465 {
2466     pm_runtime_disable(&pdev->dev);
2467
2468     return 0;
2469 }
2470
2471 #ifdef CONFIG_PM
2472 static int davinci_mcasp_runtime_suspend(struct device *dev)
2473 {
2474     struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
2475     struct davinci_mcasp_context *context = &mcasp->context;
2476     u32 reg;
2477     int i;
2478
2479     for (i = 0; i < ARRAY_SIZE(context_regs); i++)
2480         context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]);
2481
2482     if (mcasp->txnumevt) {
2483         reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
2484         context->afifo_regs[0] = mcasp_get_reg(mcasp, reg);
2485     }
2486     if (mcasp->rxnumevt) {
2487         reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
2488         context->afifo_regs[1] = mcasp_get_reg(mcasp, reg);
2489     }
2490
2491     for (i = 0; i < mcasp->num_serializer; i++)
2492         context->xrsr_regs[i] = mcasp_get_reg(mcasp,
2493                         DAVINCI_MCASP_XRSRCTL_REG(i));
2494
2495     return 0;
2496 }
2497
2498 static int davinci_mcasp_runtime_resume(struct device *dev)
2499 {
2500     struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
2501     struct davinci_mcasp_context *context = &mcasp->context;
2502     u32 reg;
2503     int i;
2504
2505     for (i = 0; i < ARRAY_SIZE(context_regs); i++)
2506         mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]);
2507
2508     if (mcasp->txnumevt) {
2509         reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
2510         mcasp_set_reg(mcasp, reg, context->afifo_regs[0]);
2511     }
2512     if (mcasp->rxnumevt) {
2513         reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
2514         mcasp_set_reg(mcasp, reg, context->afifo_regs[1]);
2515     }
2516
2517     for (i = 0; i < mcasp->num_serializer; i++)
2518         mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
2519                   context->xrsr_regs[i]);
2520
2521     return 0;
2522 }
2523
2524 #endif
2525
2526 static const struct dev_pm_ops davinci_mcasp_pm_ops = {
2527     SET_RUNTIME_PM_OPS(davinci_mcasp_runtime_suspend,
2528                davinci_mcasp_runtime_resume,
2529                NULL)
2530 };
2531
2532 static struct platform_driver davinci_mcasp_driver = {
2533     .probe      = davinci_mcasp_probe,
2534     .remove     = davinci_mcasp_remove,
2535     .driver     = {
2536         .name   = "davinci-mcasp",
2537         .pm     = &davinci_mcasp_pm_ops,
2538         .of_match_table = mcasp_dt_ids,
2539     },
2540 };
2541
2542 module_platform_driver(davinci_mcasp_driver);
2543
2544 MODULE_AUTHOR("Steve Chen");
2545 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
2546 MODULE_LICENSE("GPL");