soc/tegra/tegra_audio_graph_card.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 //
0003 // tegra_audio_graph_card.c - Audio Graph based Tegra Machine Driver
0004 //
0005 // Copyright (c) 2020-2021 NVIDIA CORPORATION.  All rights reserved.
0006
0007 #include <linux/math64.h>
0008 #include <linux/module.h>
0009 #include <linux/of_device.h>
0010 #include <linux/platform_device.h>
0011 #include <sound/graph_card.h>
0012 #include <sound/pcm_params.h>
0013
0014 #define MAX_PLLA_OUT0_DIV 128
0015
0016 #define simple_to_tegra_priv(simple) \
0017         container_of(simple, struct tegra_audio_priv, simple)
0018
0019 enum srate_type {
0020     /*
0021      * Sample rates multiple of 8000 Hz and below are supported:
0022      * ( 8000, 16000, 32000, 48000, 96000, 192000 Hz )
0023      */
0024     x8_RATE,
0025
0026     /*
0027      * Sample rates multiple of 11025 Hz and below are supported:
0028      * ( 11025, 22050, 44100, 88200, 176400 Hz )
0029      */
0030     x11_RATE,
0031
0032     NUM_RATE_TYPE,
0033 };
0034
0035 struct tegra_audio_priv {
0036     struct asoc_simple_priv simple;
0037     struct clk *clk_plla_out0;
0038     struct clk *clk_plla;
0039 };
0040
0041 /* Tegra audio chip data */
0042 struct tegra_audio_cdata {
0043     unsigned int plla_rates[NUM_RATE_TYPE];
0044     unsigned int plla_out0_rates[NUM_RATE_TYPE];
0045 };
0046
0047 /* Setup PLL clock as per the given sample rate */
0048 static int tegra_audio_graph_update_pll(struct snd_pcm_substream *substream,
0049                     struct snd_pcm_hw_params *params)
0050 {
0051     struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
0052     struct asoc_simple_priv *simple = snd_soc_card_get_drvdata(rtd->card);
0053     struct tegra_audio_priv *priv = simple_to_tegra_priv(simple);
0054     struct device *dev = rtd->card->dev;
0055     const struct tegra_audio_cdata *data = of_device_get_match_data(dev);
0056     unsigned int plla_rate, plla_out0_rate, bclk;
0057     unsigned int srate = params_rate(params);
0058     int err;
0059
0060     switch (srate) {
0061     case 11025:
0062     case 22050:
0063     case 44100:
0064     case 88200:
0065     case 176400:
0066         plla_out0_rate = data->plla_out0_rates[x11_RATE];
0067         plla_rate = data->plla_rates[x11_RATE];
0068         break;
0069     case 8000:
0070     case 16000:
0071     case 32000:
0072     case 48000:
0073     case 96000:
0074     case 192000:
0075         plla_out0_rate = data->plla_out0_rates[x8_RATE];
0076         plla_rate = data->plla_rates[x8_RATE];
0077         break;
0078     default:
0079         dev_err(rtd->card->dev, "Unsupported sample rate %u\n",
0080             srate);
0081         return -EINVAL;
0082     }
0083
0084     /*
0085      * Below is the clock relation:
0086      *
0087      *  PLLA
0088      *    |
0089      *    |--> PLLA_OUT0
0090      *        |
0091      *        |---> I2S modules
0092      *        |
0093      *        |---> DMIC modules
0094      *        |
0095      *        |---> DSPK modules
0096      *
0097      *
0098      * Default PLLA_OUT0 rate might be too high when I/O is running
0099      * at minimum PCM configurations. This may result in incorrect
0100      * clock rates and glitchy audio. The maximum divider is 128
0101      * and any thing higher than that won't work. Thus reduce PLLA_OUT0
0102      * to work for lower configurations.
0103      *
0104      * This problem is seen for I2S only, as DMIC and DSPK minimum
0105      * clock requirements are under allowed divider limits.
0106      */
0107     bclk = srate * params_channels(params) * params_width(params);
0108     if (div_u64(plla_out0_rate, bclk) > MAX_PLLA_OUT0_DIV)
0109         plla_out0_rate >>= 1;
0110
0111     dev_dbg(rtd->card->dev,
0112         "Update clock rates: PLLA(= %u Hz) and PLLA_OUT0(= %u Hz)\n",
0113         plla_rate, plla_out0_rate);
0114
0115     /* Set PLLA rate */
0116     err = clk_set_rate(priv->clk_plla, plla_rate);
0117     if (err) {
0118         dev_err(rtd->card->dev,
0119             "Can't set plla rate for %u, err: %d\n",
0120             plla_rate, err);
0121         return err;
0122     }
0123
0124     /* Set PLLA_OUT0 rate */
0125     err = clk_set_rate(priv->clk_plla_out0, plla_out0_rate);
0126     if (err) {
0127         dev_err(rtd->card->dev,
0128             "Can't set plla_out0 rate %u, err: %d\n",
0129             plla_out0_rate, err);
0130         return err;
0131     }
0132
0133     return err;
0134 }
0135
0136 static int tegra_audio_graph_hw_params(struct snd_pcm_substream *substream,
0137                        struct snd_pcm_hw_params *params)
0138 {
0139     struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
0140     struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
0141     int err;
0142
0143     /*
0144      * This gets called for each DAI link (FE or BE) when DPCM is used.
0145      * We may not want to update PLLA rate for each call. So PLLA update
0146      * must be restricted to external I/O links (I2S, DMIC or DSPK) since
0147      * they actually depend on it. I/O modules update their clocks in
0148      * hw_param() of their respective component driver and PLLA rate
0149      * update here helps them to derive appropriate rates.
0150      *
0151      * TODO: When more HW accelerators get added (like sample rate
0152      * converter, volume gain controller etc., which don't really
0153      * depend on PLLA) we need a better way to filter here.
0154      */
0155     if (cpu_dai->driver->ops && rtd->dai_link->no_pcm) {
0156         err = tegra_audio_graph_update_pll(substream, params);
0157         if (err)
0158             return err;
0159     }
0160
0161     return asoc_simple_hw_params(substream, params);
0162 }
0163
0164 static const struct snd_soc_ops tegra_audio_graph_ops = {
0165     .startup    = asoc_simple_startup,
0166     .shutdown   = asoc_simple_shutdown,
0167     .hw_params  = tegra_audio_graph_hw_params,
0168 };
0169
0170 static int tegra_audio_graph_card_probe(struct snd_soc_card *card)
0171 {
0172     struct asoc_simple_priv *simple = snd_soc_card_get_drvdata(card);
0173     struct tegra_audio_priv *priv = simple_to_tegra_priv(simple);
0174
0175     priv->clk_plla = devm_clk_get(card->dev, "pll_a");
0176     if (IS_ERR(priv->clk_plla)) {
0177         dev_err(card->dev, "Can't retrieve clk pll_a\n");
0178         return PTR_ERR(priv->clk_plla);
0179     }
0180
0181     priv->clk_plla_out0 = devm_clk_get(card->dev, "plla_out0");
0182     if (IS_ERR(priv->clk_plla_out0)) {
0183         dev_err(card->dev, "Can't retrieve clk plla_out0\n");
0184         return PTR_ERR(priv->clk_plla_out0);
0185     }
0186
0187     return asoc_graph_card_probe(card);
0188 }
0189
0190 static int tegra_audio_graph_probe(struct platform_device *pdev)
0191 {
0192     struct tegra_audio_priv *priv;
0193     struct device *dev = &pdev->dev;
0194     struct snd_soc_card *card;
0195
0196     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0197     if (!priv)
0198         return -ENOMEM;
0199
0200     card = simple_priv_to_card(&priv->simple);
0201     card->driver_name = "tegra-ape";
0202
0203     card->probe = tegra_audio_graph_card_probe;
0204
0205     /* audio_graph_parse_of() depends on below */
0206     card->component_chaining = 1;
0207     priv->simple.ops = &tegra_audio_graph_ops;
0208     priv->simple.force_dpcm = 1;
0209
0210     return audio_graph_parse_of(&priv->simple, dev);
0211 }
0212
0213 static const struct tegra_audio_cdata tegra210_data = {
0214     /* PLLA */
0215     .plla_rates[x8_RATE] = 368640000,
0216     .plla_rates[x11_RATE] = 338688000,
0217     /* PLLA_OUT0 */
0218     .plla_out0_rates[x8_RATE] = 49152000,
0219     .plla_out0_rates[x11_RATE] = 45158400,
0220 };
0221
0222 static const struct tegra_audio_cdata tegra186_data = {
0223     /* PLLA */
0224     .plla_rates[x8_RATE] = 245760000,
0225     .plla_rates[x11_RATE] = 270950400,
0226     /* PLLA_OUT0 */
0227     .plla_out0_rates[x8_RATE] = 49152000,
0228     .plla_out0_rates[x11_RATE] = 45158400,
0229 };
0230
0231 static const struct of_device_id graph_of_tegra_match[] = {
0232     { .compatible = "nvidia,tegra210-audio-graph-card",
0233       .data = &tegra210_data },
0234     { .compatible = "nvidia,tegra186-audio-graph-card",
0235       .data = &tegra186_data },
0236     {},
0237 };
0238 MODULE_DEVICE_TABLE(of, graph_of_tegra_match);
0239
0240 static struct platform_driver tegra_audio_graph_card = {
0241     .driver = {
0242         .name = "tegra-audio-graph-card",
0243         .pm = &snd_soc_pm_ops,
0244         .of_match_table = graph_of_tegra_match,
0245     },
0246     .probe = tegra_audio_graph_probe,
0247     .remove = asoc_simple_remove,
0248 };
0249 module_platform_driver(tegra_audio_graph_card);
0250
0251 MODULE_LICENSE("GPL v2");
0252 MODULE_DESCRIPTION("ASoC Tegra Audio Graph Sound Card");
0253 MODULE_AUTHOR("Sameer Pujar <spujar@nvidia.com>");