soc/tegra/tegra210_sfc.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * tegra210_sfc.h - Definitions for Tegra210 SFC driver
0004  *
0005  * Copyright (c) 2021 NVIDIA CORPORATION.  All rights reserved.
0006  *
0007  */
0008
0009 #ifndef __TEGRA210_SFC_H__
0010 #define __TEGRA210_SFC_H__
0011
0012 /*
0013  * SFC_RX registers are with respect to XBAR.
0014  * The data comes from XBAR to SFC.
0015  */
0016 #define TEGRA210_SFC_RX_STATUS          0x0c
0017 #define TEGRA210_SFC_RX_INT_STATUS      0x10
0018 #define TEGRA210_SFC_RX_INT_MASK        0x14
0019 #define TEGRA210_SFC_RX_INT_SET         0x18
0020 #define TEGRA210_SFC_RX_INT_CLEAR       0x1c
0021 #define TEGRA210_SFC_RX_CIF_CTRL        0x20
0022 #define TEGRA210_SFC_RX_FREQ            0x24
0023
0024 /*
0025  * SFC_TX registers are with respect to XBAR.
0026  * The data goes out of SFC.
0027  */
0028 #define TEGRA210_SFC_TX_STATUS          0x4c
0029 #define TEGRA210_SFC_TX_INT_STATUS      0x50
0030 #define TEGRA210_SFC_TX_INT_MASK        0x54
0031 #define TEGRA210_SFC_TX_INT_SET         0x58
0032 #define TEGRA210_SFC_TX_INT_CLEAR       0x5c
0033 #define TEGRA210_SFC_TX_CIF_CTRL        0x60
0034 #define TEGRA210_SFC_TX_FREQ            0x64
0035
0036 /* Register offsets from TEGRA210_SFC*_BASE */
0037 #define TEGRA210_SFC_ENABLE         0x80
0038 #define TEGRA210_SFC_SOFT_RESET         0x84
0039 #define TEGRA210_SFC_CG             0x88
0040 #define TEGRA210_SFC_STATUS         0x8c
0041 #define TEGRA210_SFC_INT_STATUS         0x90
0042 #define TEGRA210_SFC_COEF_RAM           0xbc
0043 #define TEGRA210_SFC_CFG_RAM_CTRL       0xc0
0044 #define TEGRA210_SFC_CFG_RAM_DATA       0xc4
0045
0046 /* Fields in TEGRA210_SFC_ENABLE */
0047 #define TEGRA210_SFC_EN_SHIFT           0
0048 #define TEGRA210_SFC_EN             (1 << TEGRA210_SFC_EN_SHIFT)
0049
0050 #define TEGRA210_SFC_NUM_RATES 12
0051
0052 /* Fields in TEGRA210_SFC_COEF_RAM */
0053 #define TEGRA210_SFC_COEF_RAM_EN        BIT(0)
0054
0055 #define TEGRA210_SFC_SOFT_RESET_EN              BIT(0)
0056
0057 /* Coefficients */
0058 #define TEGRA210_SFC_COEF_RAM_DEPTH     64
0059 #define TEGRA210_SFC_RAM_CTRL_RW_WRITE      (1 << 14)
0060 #define TEGRA210_SFC_RAM_CTRL_ADDR_INIT_EN  (1 << 13)
0061 #define TEGRA210_SFC_RAM_CTRL_SEQ_ACCESS_EN (1 << 12)
0062
0063
0064 enum tegra210_sfc_path {
0065     SFC_RX_PATH,
0066     SFC_TX_PATH,
0067     SFC_PATHS,
0068 };
0069
0070 struct tegra210_sfc {
0071     unsigned int mono_to_stereo[SFC_PATHS];
0072     unsigned int stereo_to_mono[SFC_PATHS];
0073     unsigned int srate_out;
0074     unsigned int srate_in;
0075     struct regmap *regmap;
0076 };
0077
0078 #endif