soc/tegra/tegra210_sfc.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 //
0003 // tegra210_sfc.c - Tegra210 SFC driver
0004 //
0005 // Copyright (c) 2021 NVIDIA CORPORATION.  All rights reserved.
0006
0007 #include <linux/clk.h>
0008 #include <linux/device.h>
0009 #include <linux/io.h>
0010 #include <linux/module.h>
0011 #include <linux/of.h>
0012 #include <linux/of_device.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/pm_runtime.h>
0015 #include <linux/regmap.h>
0016 #include <sound/core.h>
0017 #include <sound/pcm.h>
0018 #include <sound/pcm_params.h>
0019 #include <sound/soc.h>
0020
0021 #include "tegra210_sfc.h"
0022 #include "tegra_cif.h"
0023
0024 #define UNSUPP_CONV ((void *)(-EOPNOTSUPP))
0025 #define BYPASS_CONV NULL
0026
0027 static const struct reg_default tegra210_sfc_reg_defaults[] = {
0028     { TEGRA210_SFC_RX_INT_MASK, 0x00000001},
0029     { TEGRA210_SFC_RX_CIF_CTRL, 0x00007700},
0030     { TEGRA210_SFC_TX_INT_MASK, 0x00000001},
0031     { TEGRA210_SFC_TX_CIF_CTRL, 0x00007700},
0032     { TEGRA210_SFC_CG, 0x1},
0033     { TEGRA210_SFC_CFG_RAM_CTRL, 0x00004000},
0034 };
0035
0036 static const int tegra210_sfc_rates[TEGRA210_SFC_NUM_RATES] = {
0037     8000,
0038     11025,
0039     16000,
0040     22050,
0041     24000,
0042     32000,
0043     44100,
0044     48000,
0045     88200,
0046     96000,
0047     176400,
0048     192000,
0049 };
0050
0051 /* coeff RAM tables required for SFC */
0052 static u32 coef_8to11[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0053     0x000c6102,//header
0054     0x0001d727,//input gain
0055     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0056     0x00e55557, 0xffcadd5b, 0x003d80ba,
0057     0x00d13397, 0xfff232f8, 0x00683337,
0058     0x00000002,//output gain
0059     0x0018a102,//header
0060     0x000005d6,//input gain
0061     0x00c6543e, 0xff342935, 0x0052f116,
0062     0x000a1d78, 0xff3330c0, 0x005f88a3,
0063     0xffbee7c0, 0xff2b5ba5, 0x0073eb26,
0064     0x00000003,//output gain
0065     0x00235204,//farrow
0066     0x000aaaab,
0067     0xffaaaaab,
0068     0xfffaaaab,
0069     0x00555555,
0070     0xff600000,
0071     0xfff55555,
0072     0x00155555,
0073     0x00055555,
0074     0xffeaaaab,
0075     0x00200000,
0076     0x00005102,//header
0077     0x0000015f,//input gain
0078     0x00a7909c, 0xff241c71, 0x005f5e00,
0079     0xffca77f4, 0xff20dd50, 0x006855eb,
0080     0xff86c552, 0xff18137a, 0x00773648,
0081     0x00000001//output gain
0082 };
0083
0084 static u32 coef_8to16[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0085     0x00006102,//header
0086     0x0001d727,//input gain
0087     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0088     0x00e55557, 0xffcadd5b, 0x003d80ba,
0089     0x00d13397, 0xfff232f8, 0x00683337,
0090     0x00000002//output gain
0091 };
0092
0093 static u32 coef_8to22[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0094     0x000c6102,//header
0095     0x0001d727,//input gain
0096     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0097     0x00e55557, 0xffcadd5b, 0x003d80ba,
0098     0x00d13397, 0xfff232f8, 0x00683337,
0099     0x00000002,//output gain
0100     0x0018a102,//header
0101     0x000005d6,//input gain
0102     0x00c6543e, 0xff342935, 0x0052f116,
0103     0x000a1d78, 0xff3330c0, 0x005f88a3,
0104     0xffbee7c0, 0xff2b5ba5, 0x0073eb26,
0105     0x00000003,//output gain
0106     0x00230204,//farrow
0107     0x000aaaab,
0108     0xffaaaaab,
0109     0xfffaaaab,
0110     0x00555555,
0111     0xff600000,
0112     0xfff55555,
0113     0x00155555,
0114     0x00055555,
0115     0xffeaaaab,
0116     0x00200000,
0117     0x00005102,//header
0118     0x000005f3,//input gain
0119     0x00d816d6, 0xff385383, 0x004fe566,
0120     0x003c548d, 0xff38c23d, 0x005d0b1c,
0121     0xfff02f7d, 0xff31e983, 0x0072d65d,
0122     0x00000001//output gain
0123 };
0124
0125 static u32 coef_8to24[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0126     0x0000a105,//header
0127     0x000005e1,//input gain
0128     0x00dca92f, 0xff45647a, 0x0046b59c,
0129     0x00429d1e, 0xff4fec62, 0x00516d30,
0130     0xffdea779, 0xff5e08ba, 0x0060185e,
0131     0xffafbab2, 0xff698d5a, 0x006ce3ae,
0132     0xff9a82d2, 0xff704674, 0x007633c5,
0133     0xff923433, 0xff721128, 0x007cff42,
0134     0x00000003//output gain
0135 };
0136
0137 static u32 coef_8to32[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0138     0x000c6102,//header
0139     0x0001d727,//input gain
0140     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0141     0x00e55557, 0xffcadd5b, 0x003d80ba,
0142     0x00d13397, 0xfff232f8, 0x00683337,
0143     0x00000002,//output gain
0144     0x00006102,//header
0145     0x000013d9,//input gain
0146     0x00ebd477, 0xff4ce383, 0x0042049d,
0147     0x0089c278, 0xff54414d, 0x00531ded,
0148     0x004a5e07, 0xff53cf41, 0x006efbdc,
0149     0x00000002//output gain
0150 };
0151
0152 static u32 coef_8to44[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0153     0x0156105,//interpolation + IIR filter
0154     0x0000d649,//input gain
0155     0x00e87afb, 0xff5f69d0, 0x003df3cf,
0156     0x007ce488, 0xff99a5c8, 0x0056a6a0,
0157     0x00344928, 0xffcba3e5, 0x006be470,
0158     0x00137aa7, 0xffe60276, 0x00773410,
0159     0x0005fa2a, 0xfff1ac11, 0x007c795b,
0160     0x00012d36, 0xfff5eca2, 0x007f10ef,
0161     0x00000002,//ouptut gain
0162     0x0021a102,//interpolation + IIR filter
0163     0x00000e00,//input gain
0164     0x00e2e000, 0xff6e1a00, 0x002aaa00,
0165     0x00610a00, 0xff5dda00, 0x003ccc00,
0166     0x00163a00, 0xff3c0400, 0x00633200,
0167     0x00000003,//Output gain
0168     0x00000204,//Farrow filter
0169     0x000aaaab,
0170     0xffaaaaab,
0171     0xfffaaaab,
0172     0x00555555,
0173     0xff600000,
0174     0xfff55555,
0175     0x00155555,
0176     0x00055555,
0177     0xffeaaaab,
0178     0x00200000
0179 };
0180
0181 static u32 coef_8to48[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0182     0x00156105,//interpolation + IIR Filter
0183     0x0000d649,//input gain
0184     0x00e87afb, 0xff5f69d0, 0x003df3cf,
0185     0x007ce488, 0xff99a5c8, 0x0056a6a0,
0186     0x00344928, 0xffcba3e5, 0x006be470,
0187     0x00137aa7, 0xffe60276, 0x00773410,
0188     0x0005fa2a, 0xfff1ac11, 0x007c795b,
0189     0x00012d36, 0xfff5eca2, 0x007f10ef,
0190     0x00000002,//ouptut gain
0191     0x0000a102,//interpolation + IIR filter
0192     0x00000e00,//input gain
0193     0x00e2e000, 0xff6e1a00, 0x002aaa00,
0194     0x00610a00, 0xff5dda00, 0x003ccc00,
0195     0x00163a00, 0xff3c0400, 0x00633200,
0196     0x00000003//output gain
0197 };
0198
0199 static u32 coef_8to88[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0200     0x000c6102,//header
0201     0x0001d727,//input gain
0202     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0203     0x00e55557, 0xffcadd5b, 0x003d80ba,
0204     0x00d13397, 0xfff232f8, 0x00683337,
0205     0x00000002,//output gain
0206     0x00186102,//header
0207     0x000013d9,//input gain
0208     0x00ebd477, 0xff4ce383, 0x0042049d,
0209     0x0089c278, 0xff54414d, 0x00531ded,
0210     0x004a5e07, 0xff53cf41, 0x006efbdc,
0211     0x00000002,//output gain
0212     0x0024a102,//header
0213     0x0000007d,//input gain
0214     0x007d1f20, 0xff1a540e, 0x00678bf9,
0215     0xff916625, 0xff16b0ff, 0x006e433a,
0216     0xff5af660, 0xff0eb91f, 0x00797356,
0217     0x00000003,//output gain
0218     0x00000204,//farrow
0219     0x000aaaab,
0220     0xffaaaaab,
0221     0xfffaaaab,
0222     0x00555555,
0223     0xff600000,
0224     0xfff55555,
0225     0x00155555,
0226     0x00055555,
0227     0xffeaaaab,
0228     0x00200000
0229 };
0230
0231 static u32 coef_8to96[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0232     0x000c6102,//header
0233     0x0001d727,//input gain
0234     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0235     0x00e55557, 0xffcadd5b, 0x003d80ba,
0236     0x00d13397, 0xfff232f8, 0x00683337,
0237     0x00000002,//output gain
0238     0x00186102,//header
0239     0x000013d9,//input gain
0240     0x00ebd477, 0xff4ce383, 0x0042049d,
0241     0x0089c278, 0xff54414d, 0x00531ded,
0242     0x004a5e07, 0xff53cf41, 0x006efbdc,
0243     0x00000002,//output gain
0244     0x0000a102,//header
0245     0x0000007d,//input gain
0246     0x007d1f20, 0xff1a540e, 0x00678bf9,
0247     0xff916625, 0xff16b0ff, 0x006e433a,
0248     0xff5af660, 0xff0eb91f, 0x00797356,
0249     0x00000003//output gain
0250 };
0251
0252 static u32 coef_11to8[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0253     0x000c6102,//header
0254     0x0000015f,//input gain
0255     0x00a7909c, 0xff241c71, 0x005f5e00,
0256     0xffca77f4, 0xff20dd50, 0x006855eb,
0257     0xff86c552, 0xff18137a, 0x00773648,
0258     0x00000002,//output gain
0259     0x00186102,//header
0260     0x000005f3,//input gain
0261     0x00d816d6, 0xff385383, 0x004fe566,
0262     0x003c548d, 0xff38c23d, 0x005d0b1c,
0263     0xfff02f7d, 0xff31e983, 0x0072d65d,
0264     0x00000002,//output gain
0265     0x00239204,//farrow
0266     0x000aaaab,
0267     0xffaaaaab,
0268     0xfffaaaab,
0269     0x00555555,
0270     0xff600000,
0271     0xfff55555,
0272     0x00155555,
0273     0x00055555,
0274     0xffeaaaab,
0275     0x00200000,
0276     0x00005102,//header
0277     0x0001d727,//input gain
0278     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0279     0x00e55557, 0xffcadd5b, 0x003d80ba,
0280     0x00d13397, 0xfff232f8, 0x00683337,
0281     0x00000001//output gain
0282 };
0283
0284 static u32 coef_11to16[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0285     0x000c6102,//header
0286     0x0001d727,//input gain
0287     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0288     0x00e55557, 0xffcadd5b, 0x003d80ba,
0289     0x00d13397, 0xfff232f8, 0x00683337,
0290     0x00000002,//output gain
0291     0x00186102,//header
0292     0x000013d9,//input gain
0293     0x00ebd477, 0xff4ce383, 0x0042049d,
0294     0x0089c278, 0xff54414d, 0x00531ded,
0295     0x004a5e07, 0xff53cf41, 0x006efbdc,
0296     0x00000002,//output gain
0297     0x00009204,//farrow
0298     0x000aaaab,
0299     0xffaaaaab,
0300     0xfffaaaab,
0301     0x00555555,
0302     0xff600000,
0303     0xfff55555,
0304     0x00155555,
0305     0x00055555,
0306     0xffeaaaab,
0307     0x00200000
0308 };
0309
0310 static u32 coef_11to22[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0311     0x00006102,//header
0312     0x0001d727,//input gain
0313     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0314     0x00e55557, 0xffcadd5b, 0x003d80ba,
0315     0x00d13397, 0xfff232f8, 0x00683337,
0316     0x00000002//output gain
0317 };
0318
0319 static u32 coef_11to24[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0320     0x000c6102,//header
0321     0x0001d727,//input gain
0322     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0323     0x00e55557, 0xffcadd5b, 0x003d80ba,
0324     0x00d13397, 0xfff232f8, 0x00683337,
0325     0x00000002,//output gain
0326     0x00186102,//header
0327     0x000013d9,//input gain
0328     0x00ebd477, 0xff4ce383, 0x0042049d,
0329     0x0089c278, 0xff54414d, 0x00531ded,
0330     0x004a5e07, 0xff53cf41, 0x006efbdc,
0331     0x00000002,//output gain
0332     0x00005204,//farrow
0333     0x000aaaab,
0334     0xffaaaaab,
0335     0xfffaaaab,
0336     0x00555555,
0337     0xff600000,
0338     0xfff55555,
0339     0x00155555,
0340     0x00055555,
0341     0xffeaaaab,
0342     0x00200000
0343 };
0344
0345 static u32 coef_11to32[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0346     0x000c6102,//header
0347     0x0001d727,//input gain
0348     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0349     0x00e55557, 0xffcadd5b, 0x003d80ba,
0350     0x00d13397, 0xfff232f8, 0x00683337,
0351     0x00000002,//output gain
0352     0x00186102,//header
0353     0x000013d9,//input gain
0354     0x00ebd477, 0xff4ce383, 0x0042049d,
0355     0x0089c278, 0xff54414d, 0x00531ded,
0356     0x004a5e07, 0xff53cf41, 0x006efbdc,
0357     0x00000002,//output gain
0358     0x00246102,//header
0359     0x0000010a,//input gain
0360     0x00c93dc4, 0xff26f5f6, 0x005d1041,
0361     0x001002c4, 0xff245b76, 0x00666002,
0362     0xffc30a45, 0xff1baecd, 0x00765921,
0363     0x00000002,//output gain
0364     0x00009204,//farrow
0365     0x000aaaab,
0366     0xffaaaaab,
0367     0xfffaaaab,
0368     0x00555555,
0369     0xff600000,
0370     0xfff55555,
0371     0x00155555,
0372     0x00055555,
0373     0xffeaaaab,
0374     0x00200000
0375 };
0376
0377 static u32 coef_11to44[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0378     0x000c6102,//header
0379     0x0001d727,//input gain
0380     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0381     0x00e55557, 0xffcadd5b, 0x003d80ba,
0382     0x00d13397, 0xfff232f8, 0x00683337,
0383     0x00000002,//output gain
0384     0x00006102,//header
0385     0x000013d9,//input gain
0386     0x00ebd477, 0xff4ce383, 0x0042049d,
0387     0x0089c278, 0xff54414d, 0x00531ded,
0388     0x004a5e07, 0xff53cf41, 0x006efbdc,
0389     0x00000002//output gain
0390 };
0391
0392 static u32 coef_11to48[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0393     0x000c6102,//header
0394     0x0001d727,//input gain
0395     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0396     0x00e55557, 0xffcadd5b, 0x003d80ba,
0397     0x00d13397, 0xfff232f8, 0x00683337,
0398     0x00000002,//output gain
0399     0x00186102,//header
0400     0x000013d9,//input gain
0401     0x00ebd477, 0xff4ce383, 0x0042049d,
0402     0x0089c278, 0xff54414d, 0x00531ded,
0403     0x004a5e07, 0xff53cf41, 0x006efbdc,
0404     0x00000002,//output gain
0405     0x00246102,//header
0406     0x0000010a,//input gain
0407     0x00c93dc4, 0xff26f5f6, 0x005d1041,
0408     0x001002c4, 0xff245b76, 0x00666002,
0409     0xffc30a45, 0xff1baecd, 0x00765921,
0410     0x00000002,//output gain
0411     0x00005204,//farrow
0412     0x000aaaab,
0413     0xffaaaaab,
0414     0xfffaaaab,
0415     0x00555555,
0416     0xff600000,
0417     0xfff55555,
0418     0x00155555,
0419     0x00055555,
0420     0xffeaaaab,
0421     0x00200000
0422 };
0423
0424 static u32 coef_11to88[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0425     0x000c6102,//header
0426     0x0001d727,//input gain
0427     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0428     0x00e55557, 0xffcadd5b, 0x003d80ba,
0429     0x00d13397, 0xfff232f8, 0x00683337,
0430     0x00000002,//output gain
0431     0x00186102,//header
0432     0x000013d9,//input gain
0433     0x00ebd477, 0xff4ce383, 0x0042049d,
0434     0x0089c278, 0xff54414d, 0x00531ded,
0435     0x004a5e07, 0xff53cf41, 0x006efbdc,
0436     0x00000002,//output gain
0437     0x00006102,//header
0438     0x0000010a,//input gain
0439     0x00c93dc4, 0xff26f5f6, 0x005d1041,
0440     0x001002c4, 0xff245b76, 0x00666002,
0441     0xffc30a45, 0xff1baecd, 0x00765921,
0442     0x00000002//output gain
0443 };
0444
0445 static u32 coef_11to96[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0446     0x000c6102,//header
0447     0x0001d727,//input gain
0448     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0449     0x00e55557, 0xffcadd5b, 0x003d80ba,
0450     0x00d13397, 0xfff232f8, 0x00683337,
0451     0x00000002,//output gain
0452     0x00186102,//header
0453     0x000013d9,//input gain
0454     0x00ebd477, 0xff4ce383, 0x0042049d,
0455     0x0089c278, 0xff54414d, 0x00531ded,
0456     0x004a5e07, 0xff53cf41, 0x006efbdc,
0457     0x00000002,//output gain
0458     0x00246102,//header
0459     0x0000010a,//input gain
0460     0x00c93dc4, 0xff26f5f6, 0x005d1041,
0461     0x001002c4, 0xff245b76, 0x00666002,
0462     0xffc30a45, 0xff1baecd, 0x00765921,
0463     0x00000002,//output gain
0464     0x00000204,//farrow
0465     0x000aaaab,
0466     0xffaaaaab,
0467     0xfffaaaab,
0468     0x00555555,
0469     0xff600000,
0470     0xfff55555,
0471     0x00155555,
0472     0x00055555,
0473     0xffeaaaab,
0474     0x00200000
0475 };
0476
0477 static u32 coef_16to8[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0478     0x00005102,//header
0479     0x0001d727,//input gain
0480     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0481     0x00e55557, 0xffcadd5b, 0x003d80ba,
0482     0x00d13397, 0xfff232f8, 0x00683337,
0483     0x00000001//output gain
0484 };
0485
0486 static u32 coef_16to11[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0487     0x000fa103,//header
0488     0x000001e0,//input gain
0489     0x00de44c0, 0xff380b7f, 0x004ffc73,
0490     0x00494b44, 0xff3d493a, 0x005908bf,
0491     0xffe9a3c8, 0xff425647, 0x006745f7,
0492     0xffc42d61, 0xff40a6c7, 0x00776709,
0493     0x00000003,//output gain
0494     0x001a5204,//farrow
0495     0x000aaaab,
0496     0xffaaaaab,
0497     0xfffaaaab,
0498     0x00555555,
0499     0xff600000,
0500     0xfff55555,
0501     0x00155555,
0502     0x00055555,
0503     0xffeaaaab,
0504     0x00200000,
0505     0x00005102,//header
0506     0x0001d727,//input gain
0507     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0508     0x00e55557, 0xffcadd5b, 0x003d80ba,
0509     0x00d13397, 0xfff232f8, 0x00683337,
0510     0x00000001//output gain
0511 };
0512
0513 static u32 coef_16to22[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0514     0x000c6102,//header
0515     0x0001d727,//input gain
0516     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0517     0x00e55557, 0xffcadd5b, 0x003d80ba,
0518     0x00d13397, 0xfff232f8, 0x00683337,
0519     0x00000002,//output gain
0520     0x0018a102,//header
0521     0x000005d6,//input gain
0522     0x00c6543e, 0xff342935, 0x0052f116,
0523     0x000a1d78, 0xff3330c0, 0x005f88a3,
0524     0xffbee7c0, 0xff2b5ba5, 0x0073eb26,
0525     0x00000003,//output gain
0526     0x00235204,//farrow
0527     0x000aaaab,
0528     0xffaaaaab,
0529     0xfffaaaab,
0530     0x00555555,
0531     0xff600000,
0532     0xfff55555,
0533     0x00155555,
0534     0x00055555,
0535     0xffeaaaab,
0536     0x00200000,
0537     0x00005102,//header
0538     0x0000015f,//input gain
0539     0x00a7909c, 0xff241c71, 0x005f5e00,
0540     0xffca77f4, 0xff20dd50, 0x006855eb,
0541     0xff86c552, 0xff18137a, 0x00773648,
0542     0x00000001//output gain
0543 };
0544
0545 static u32 coef_16to24[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0546     0x0015a105,//header
0547     0x00000292,//input gain
0548     0x00e4320a, 0xff41d2d9, 0x004911ac,
0549     0x005dd9e3, 0xff4c7d80, 0x0052103e,
0550     0xfff8ebef, 0xff5b6fab, 0x005f0a0d,
0551     0xffc4b414, 0xff68582c, 0x006b38e5,
0552     0xffabb861, 0xff704bec, 0x0074de52,
0553     0xffa19f4c, 0xff729059, 0x007c7e90,
0554     0x00000003,//output gain
0555     0x00005105,//header
0556     0x00000292,//input gain
0557     0x00e4320a, 0xff41d2d9, 0x004911ac,
0558     0x005dd9e3, 0xff4c7d80, 0x0052103e,
0559     0xfff8ebef, 0xff5b6fab, 0x005f0a0d,
0560     0xffc4b414, 0xff68582c, 0x006b38e5,
0561     0xffabb861, 0xff704bec, 0x0074de52,
0562     0xffa19f4c, 0xff729059, 0x007c7e90,
0563     0x00000001//output gain
0564 };
0565
0566 static u32 coef_16to32[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0567     0x00006102,//header
0568     0x0001d727,//input gain
0569     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0570     0x00e55557, 0xffcadd5b, 0x003d80ba,
0571     0x00d13397, 0xfff232f8, 0x00683337,
0572     0x00000002//output gain
0573 };
0574
0575 static u32 coef_16to44[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0576     0x00156105,//interpolation + IIR filter
0577     0x0000d649,//input gain
0578     0x00e87afb, 0xff5f69d0, 0x003df3cf,
0579     0x007ce488, 0xff99a5c8, 0x0056a6a0,
0580     0x00344928, 0xffcba3e5, 0x006be470,
0581     0x00137aa7, 0xffe60276, 0x00773410,
0582     0x0005fa2a, 0xfff1ac11, 0x007c795b,
0583     0x00012d36, 0xfff5eca2, 0x007f10ef,
0584     0x00000002,//output gain
0585     0x0021a102,//interpolation + IIR filter
0586     0x00000e00,//input gain
0587     0x00e2e000, 0xff6e1a00, 0x002aaa00,
0588     0x00610a00, 0xff5dda00, 0x003ccc00,
0589     0x00163a00, 0xff3c0400, 0x00633200,
0590     0x00000003,//output gain
0591     0x002c0204,//Farrow Filter
0592     0x000aaaab,
0593     0xffaaaaab,
0594     0xfffaaaab,
0595     0x00555555,
0596     0xff600000,
0597     0xfff55555,
0598     0x00155555,
0599     0x00055555,
0600     0xffeaaaab,
0601     0x00200000,
0602     0x00005101,//IIR Filter + Decimator
0603     0x0000203c,//input gain
0604     0x00f52d35, 0xff2e2162, 0x005a21e0,
0605     0x00c6f0f0, 0xff2ecd69, 0x006fa78d,
0606     0x00000001//output gain
0607 };
0608
0609 static u32 coef_16to48[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0610     0x0000a105,//interpolation + IIR Filter
0611     0x00000784,//input gain
0612     0x00cc516e, 0xff2c9639, 0x005ad5b3,
0613     0x0013ad0d, 0xff3d4799, 0x0063ce75,
0614     0xffb6f398, 0xff5138d1, 0x006e9e1f,
0615     0xff9186e5, 0xff5f96a4, 0x0076a86e,
0616     0xff82089c, 0xff676b81, 0x007b9f8a,
0617     0xff7c48a5, 0xff6a31e7, 0x007ebb7b,
0618     0x00000003//output gain
0619 };
0620
0621 static u32 coef_16to88[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0622     0x000c6102,//header
0623     0x0001d727,//input gain
0624     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0625     0x00e55557, 0xffcadd5b, 0x003d80ba,
0626     0x00d13397, 0xfff232f8, 0x00683337,
0627     0x00000002,//output gain
0628     0x0018a102,//header
0629     0x000005d6,//input gain
0630     0x00c6543e, 0xff342935, 0x0052f116,
0631     0x000a1d78, 0xff3330c0, 0x005f88a3,
0632     0xffbee7c0, 0xff2b5ba5, 0x0073eb26,
0633     0x00000003,//output gain
0634     0x00000204,//farrow
0635     0x000aaaab,
0636     0xffaaaaab,
0637     0xfffaaaab,
0638     0x00555555,
0639     0xff600000,
0640     0xfff55555,
0641     0x00155555,
0642     0x00055555,
0643     0xffeaaaab,
0644     0x00200000
0645 };
0646
0647 static u32 coef_16to96[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0648     0x000c6102,//header
0649     0x0001d727,//input gain
0650     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0651     0x00e55557, 0xffcadd5b, 0x003d80ba,
0652     0x00d13397, 0xfff232f8, 0x00683337,
0653     0x00000002,//output gain
0654     0x0000a102,//header
0655     0x000005d6,//input gain
0656     0x00c6543e, 0xff342935, 0x0052f116,
0657     0x000a1d78, 0xff3330c0, 0x005f88a3,
0658     0xffbee7c0, 0xff2b5ba5, 0x0073eb26,
0659     0x00000003//output gain
0660 };
0661
0662 static u32 coef_16to176[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0663     0x000c6102,//header
0664     0x0001d727,//input gain
0665     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0666     0x00e55557, 0xffcadd5b, 0x003d80ba,
0667     0x00d13397, 0xfff232f8, 0x00683337,
0668     0x00000002,//output gain
0669     0x00186102,//header
0670     0x000013d9,//input gain
0671     0x00ebd477, 0xff4ce383, 0x0042049d,
0672     0x0089c278, 0xff54414d, 0x00531ded,
0673     0x004a5e07, 0xff53cf41, 0x006efbdc,
0674     0x00000002,//output gain
0675     0x0024a102,//header
0676     0x0000007d,//input gain
0677     0x007d1f20, 0xff1a540e, 0x00678bf9,
0678     0xff916625, 0xff16b0ff, 0x006e433a,
0679     0xff5af660, 0xff0eb91f, 0x00797356,
0680     0x00000003,//output gain
0681     0x00000204,//farrow
0682     0x000aaaab,
0683     0xffaaaaab,
0684     0xfffaaaab,
0685     0x00555555,
0686     0xff600000,
0687     0xfff55555,
0688     0x00155555,
0689     0x00055555,
0690     0xffeaaaab,
0691     0x00200000
0692 };
0693
0694 static u32 coef_16to192[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0695     0x000c6102,//header
0696     0x0001d727,//input gain
0697     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0698     0x00e55557, 0xffcadd5b, 0x003d80ba,
0699     0x00d13397, 0xfff232f8, 0x00683337,
0700     0x00000002,//output gain
0701     0x00186102,//header
0702     0x000013d9,//input gain
0703     0x00ebd477, 0xff4ce383, 0x0042049d,
0704     0x0089c278, 0xff54414d, 0x00531ded,
0705     0x004a5e07, 0xff53cf41, 0x006efbdc,
0706     0x00000002,//output gain
0707     0x0000a102,//header
0708     0x0000007d,//input gain
0709     0x007d1f20, 0xff1a540e, 0x00678bf9,
0710     0xff916625, 0xff16b0ff, 0x006e433a,
0711     0xff5af660, 0xff0eb91f, 0x00797356,
0712     0x00000003//output gain
0713 };
0714
0715 static u32 coef_22to8[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0716     0x000c6102,//header
0717     0x000005f3,//input gain
0718     0x00d816d6, 0xff385383, 0x004fe566,
0719     0x003c548d, 0xff38c23d, 0x005d0b1c,
0720     0xfff02f7d, 0xff31e983, 0x0072d65d,
0721     0x00000002,//output gain
0722     0x00179204,//farrow
0723     0x000aaaab,
0724     0xffaaaaab,
0725     0xfffaaaab,
0726     0x00555555,
0727     0xff600000,
0728     0xfff55555,
0729     0x00155555,
0730     0x00055555,
0731     0xffeaaaab,
0732     0x00200000,
0733     0x00005102,//header
0734     0x0001d727,//input gain
0735     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0736     0x00e55557, 0xffcadd5b, 0x003d80ba,
0737     0x00d13397, 0xfff232f8, 0x00683337,
0738     0x00000001//output gain
0739 };
0740
0741 static u32 coef_22to11[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0742     0x00005102,//header
0743     0x0001d727,//input gain
0744     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0745     0x00e55557, 0xffcadd5b, 0x003d80ba,
0746     0x00d13397, 0xfff232f8, 0x00683337,
0747     0x00000001//output gain
0748 };
0749
0750 static u32 coef_22to16[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0751     0x000c6102,//header
0752     0x0000015f,//input gain
0753     0x00a7909c, 0xff241c71, 0x005f5e00,
0754     0xffca77f4, 0xff20dd50, 0x006855eb,
0755     0xff86c552, 0xff18137a, 0x00773648,
0756     0x00000002,//output gain
0757     0x00186102,//header
0758     0x000005f3,//input gain
0759     0x00d816d6, 0xff385383, 0x004fe566,
0760     0x003c548d, 0xff38c23d, 0x005d0b1c,
0761     0xfff02f7d, 0xff31e983, 0x0072d65d,
0762     0x00000002,//output gain
0763     0x00239204,//farrow
0764     0x000aaaab,
0765     0xffaaaaab,
0766     0xfffaaaab,
0767     0x00555555,
0768     0xff600000,
0769     0xfff55555,
0770     0x00155555,
0771     0x00055555,
0772     0xffeaaaab,
0773     0x00200000,
0774     0x00005102,//header
0775     0x0001d727,//input gain
0776     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0777     0x00e55557, 0xffcadd5b, 0x003d80ba,
0778     0x00d13397, 0xfff232f8, 0x00683337,
0779     0x00000001//output gain
0780 };
0781
0782 static u32 coef_22to24[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0783     0x000c6102,//header
0784     0x0001d727,//input gain
0785     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0786     0x00e55557, 0xffcadd5b, 0x003d80ba,
0787     0x00d13397, 0xfff232f8, 0x00683337,
0788     0x00000002,//output gain
0789     0x00186102,//header
0790     0x000013d9,//input gain
0791     0x00ebd477, 0xff4ce383, 0x0042049d,
0792     0x0089c278, 0xff54414d, 0x00531ded,
0793     0x004a5e07, 0xff53cf41, 0x006efbdc,
0794     0x00000002,//output gain
0795     0x00235204,//farrow
0796     0x000aaaab,
0797     0xffaaaaab,
0798     0xfffaaaab,
0799     0x00555555,
0800     0xff600000,
0801     0xfff55555,
0802     0x00155555,
0803     0x00055555,
0804     0xffeaaaab,
0805     0x00200000,
0806     0x00005102,//header
0807     0x0001d029,//input gain
0808     0x00f2a98b, 0xff92aa71, 0x001fcd16,
0809     0x00ae9004, 0xffb85140, 0x0041813a,
0810     0x007f8ed1, 0xffd585fc, 0x006a69e6,
0811     0x00000001//output gain
0812 };
0813
0814 static u32 coef_22to32[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0815     0x000c6102,//header
0816     0x0001d727,//input gain
0817     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0818     0x00e55557, 0xffcadd5b, 0x003d80ba,
0819     0x00d13397, 0xfff232f8, 0x00683337,
0820     0x00000002,//output gain
0821     0x00186102,//header
0822     0x000013d9,//input gain
0823     0x00ebd477, 0xff4ce383, 0x0042049d,
0824     0x0089c278, 0xff54414d, 0x00531ded,
0825     0x004a5e07, 0xff53cf41, 0x006efbdc,
0826     0x00000002,//output gain
0827     0x00009204,//farrow
0828     0x000aaaab,
0829     0xffaaaaab,
0830     0xfffaaaab,
0831     0x00555555,
0832     0xff600000,
0833     0xfff55555,
0834     0x00155555,
0835     0x00055555,
0836     0xffeaaaab,
0837     0x00200000
0838 };
0839
0840 static u32 coef_22to44[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0841     0x00006102,//header
0842     0x0001d727,//input gain
0843     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0844     0x00e55557, 0xffcadd5b, 0x003d80ba,
0845     0x00d13397, 0xfff232f8, 0x00683337,
0846     0x00000002//output gain
0847 };
0848
0849 static u32 coef_22to48[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0850     0x000c6102,//header
0851     0x0001d727,//input gain
0852     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0853     0x00e55557, 0xffcadd5b, 0x003d80ba,
0854     0x00d13397, 0xfff232f8, 0x00683337,
0855     0x00000002,//output gain
0856     0x00186102,//header
0857     0x000013d9,//input gain
0858     0x00ebd477, 0xff4ce383, 0x0042049d,
0859     0x0089c278, 0xff54414d, 0x00531ded,
0860     0x004a5e07, 0xff53cf41, 0x006efbdc,
0861     0x00000002,//output gain
0862     0x00005204,//farrow
0863     0x000aaaab,
0864     0xffaaaaab,
0865     0xfffaaaab,
0866     0x00555555,
0867     0xff600000,
0868     0xfff55555,
0869     0x00155555,
0870     0x00055555,
0871     0xffeaaaab,
0872     0x00200000
0873 };
0874
0875 static u32 coef_22to88[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0876     0x000c6102,//header
0877     0x0001d727,//input gain
0878     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0879     0x00e55557, 0xffcadd5b, 0x003d80ba,
0880     0x00d13397, 0xfff232f8, 0x00683337,
0881     0x00000002,//output gain
0882     0x00006102,//header
0883     0x000013d9,//input gain
0884     0x00ebd477, 0xff4ce383, 0x0042049d,
0885     0x0089c278, 0xff54414d, 0x00531ded,
0886     0x004a5e07, 0xff53cf41, 0x006efbdc,
0887     0x00000002//output gain
0888 };
0889
0890 static u32 coef_22to96[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0891     0x000c6102,//header
0892     0x0001d727,//input gain
0893     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0894     0x00e55557, 0xffcadd5b, 0x003d80ba,
0895     0x00d13397, 0xfff232f8, 0x00683337,
0896     0x00000002,//output gain
0897     0x00186102,//header
0898     0x000013d9,//input gain
0899     0x00ebd477, 0xff4ce383, 0x0042049d,
0900     0x0089c278, 0xff54414d, 0x00531ded,
0901     0x004a5e07, 0xff53cf41, 0x006efbdc,
0902     0x00000002,//output gain
0903     0x00246102,//header
0904     0x0000010a,//input gain
0905     0x00c93dc4, 0xff26f5f6, 0x005d1041,
0906     0x001002c4, 0xff245b76, 0x00666002,
0907     0xffc30a45, 0xff1baecd, 0x00765921,
0908     0x00000002,//output gain
0909     0x00005204,//farrow
0910     0x000aaaab,
0911     0xffaaaaab,
0912     0xfffaaaab,
0913     0x00555555,
0914     0xff600000,
0915     0xfff55555,
0916     0x00155555,
0917     0x00055555,
0918     0xffeaaaab,
0919     0x00200000
0920 };
0921
0922 static u32 coef_22to176[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0923     0x000c6102,//header
0924     0x0001d727,//input gain
0925     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0926     0x00e55557, 0xffcadd5b, 0x003d80ba,
0927     0x00d13397, 0xfff232f8, 0x00683337,
0928     0x00000002,//output gain
0929     0x00186102,//header
0930     0x000013d9,//input gain
0931     0x00ebd477, 0xff4ce383, 0x0042049d,
0932     0x0089c278, 0xff54414d, 0x00531ded,
0933     0x004a5e07, 0xff53cf41, 0x006efbdc,
0934     0x00000002,//output gain
0935     0x00006102,//header
0936     0x0000010a,//input gain
0937     0x00c93dc4, 0xff26f5f6, 0x005d1041,
0938     0x001002c4, 0xff245b76, 0x00666002,
0939     0xffc30a45, 0xff1baecd, 0x00765921,
0940     0x00000002//output gain
0941 };
0942
0943 static u32 coef_22to192[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0944     0x000c6102,//header
0945     0x0001d727,//input gain
0946     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0947     0x00e55557, 0xffcadd5b, 0x003d80ba,
0948     0x00d13397, 0xfff232f8, 0x00683337,
0949     0x00000002,//output gain
0950     0x00186102,//header
0951     0x000013d9,//input gain
0952     0x00ebd477, 0xff4ce383, 0x0042049d,
0953     0x0089c278, 0xff54414d, 0x00531ded,
0954     0x004a5e07, 0xff53cf41, 0x006efbdc,
0955     0x00000002,//output gain
0956     0x00246102,//header
0957     0x0000010a,//input gain
0958     0x00c93dc4, 0xff26f5f6, 0x005d1041,
0959     0x001002c4, 0xff245b76, 0x00666002,
0960     0xffc30a45, 0xff1baecd, 0x00765921,
0961     0x00000002,//output gain
0962     0x00000204,//farrow
0963     0x000aaaab,
0964     0xffaaaaab,
0965     0xfffaaaab,
0966     0x00555555,
0967     0xff600000,
0968     0xfff55555,
0969     0x00155555,
0970     0x00055555,
0971     0xffeaaaab,
0972     0x00200000
0973 };
0974
0975 static u32 coef_24to8[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0976     0x00009105,//header
0977     0x000005e1,//input gain
0978     0x00dca92f, 0xff45647a, 0x0046b59c,
0979     0x00429d1e, 0xff4fec62, 0x00516d30,
0980     0xffdea779, 0xff5e08ba, 0x0060185e,
0981     0xffafbab2, 0xff698d5a, 0x006ce3ae,
0982     0xff9a82d2, 0xff704674, 0x007633c5,
0983     0xff923433, 0xff721128, 0x007cff42,
0984     0x00000001//output gain
0985 };
0986
0987 static u32 coef_24to11[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0988     0x000f6103,//header
0989     0x000001e0,//input gain
0990     0x00de44c0, 0xff380b7f, 0x004ffc73,
0991     0x00494b44, 0xff3d493a, 0x005908bf,
0992     0xffe9a3c8, 0xff425647, 0x006745f7,
0993     0xffc42d61, 0xff40a6c7, 0x00776709,
0994     0x00000002,//output gain
0995     0x001a5204,//farrow
0996     0x000aaaab,
0997     0xffaaaaab,
0998     0xfffaaaab,
0999     0x00555555,
1000     0xff600000,
1001     0xfff55555,
1002     0x00155555,
1003     0x00055555,
1004     0xffeaaaab,
1005     0x00200000,
1006     0x00005102,//header
1007     0x0001d727,//input gain
1008     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1009     0x00e55557, 0xffcadd5b, 0x003d80ba,
1010     0x00d13397, 0xfff232f8, 0x00683337,
1011     0x00000001//output gain
1012 };
1013
1014 static u32 coef_24to16[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1015     0x00156105,//header
1016     0x00000292,//input gain
1017     0x00e4320a, 0xff41d2d9, 0x004911ac,
1018     0x005dd9e3, 0xff4c7d80, 0x0052103e,
1019     0xfff8ebef, 0xff5b6fab, 0x005f0a0d,
1020     0xffc4b414, 0xff68582c, 0x006b38e5,
1021     0xffabb861, 0xff704bec, 0x0074de52,
1022     0xffa19f4c, 0xff729059, 0x007c7e90,
1023     0x00000002,//output gain
1024     0x00009105,//header
1025     0x00000292,//input gain
1026     0x00e4320a, 0xff41d2d9, 0x004911ac,
1027     0x005dd9e3, 0xff4c7d80, 0x0052103e,
1028     0xfff8ebef, 0xff5b6fab, 0x005f0a0d,
1029     0xffc4b414, 0xff68582c, 0x006b38e5,
1030     0xffabb861, 0xff704bec, 0x0074de52,
1031     0xffa19f4c, 0xff729059, 0x007c7e90,
1032     0x00000001//output gain
1033 };
1034
1035 static u32 coef_24to22[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1036     0x000c6102,//header
1037     0x0001d029,//input gain
1038     0x00f2a98b, 0xff92aa71, 0x001fcd16,
1039     0x00ae9004, 0xffb85140, 0x0041813a,
1040     0x007f8ed1, 0xffd585fc, 0x006a69e6,
1041     0x00000002,//output gain
1042     0x001b6103,//header
1043     0x000001e0,//input gain
1044     0x00de44c0, 0xff380b7f, 0x004ffc73,
1045     0x00494b44, 0xff3d493a, 0x005908bf,
1046     0xffe9a3c8, 0xff425647, 0x006745f7,
1047     0xffc42d61, 0xff40a6c7, 0x00776709,
1048     0x00000002,//output gain
1049     0x00265204,//farrow
1050     0x000aaaab,
1051     0xffaaaaab,
1052     0xfffaaaab,
1053     0x00555555,
1054     0xff600000,
1055     0xfff55555,
1056     0x00155555,
1057     0x00055555,
1058     0xffeaaaab,
1059     0x00200000,
1060     0x00005102,//header
1061     0x0001d727,//input gain
1062     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1063     0x00e55557, 0xffcadd5b, 0x003d80ba,
1064     0x00d13397, 0xfff232f8, 0x00683337,
1065     0x00000001//output gain
1066 };
1067
1068 static u32 coef_24to32[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1069     0x000c6102,//header
1070     0x0001d727,//input gain
1071     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1072     0x00e55557, 0xffcadd5b, 0x003d80ba,
1073     0x00d13397, 0xfff232f8, 0x00683337,
1074     0x00000002,//output gain
1075     0x00186102,//header
1076     0x000013d9,//input gain
1077     0x00ebd477, 0xff4ce383, 0x0042049d,
1078     0x0089c278, 0xff54414d, 0x00531ded,
1079     0x004a5e07, 0xff53cf41, 0x006efbdc,
1080     0x00000002,//output gain
1081     0x00009102,//header
1082     0x000013d9,//input gain
1083     0x00ebd477, 0xff4ce383, 0x0042049d,
1084     0x0089c278, 0xff54414d, 0x00531ded,
1085     0x004a5e07, 0xff53cf41, 0x006efbdc,
1086     0x00000001//output gain
1087 };
1088
1089 static u32 coef_24to44[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1090     0x000c6102,//header
1091     0x0001d727,//input gain
1092     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1093     0x00e55557, 0xffcadd5b, 0x003d80ba,
1094     0x00d13397, 0xfff232f8, 0x00683337,
1095     0x00000002,//output gain
1096     0x00186102,//header
1097     0x000013d9,//input gain
1098     0x00ebd477, 0xff4ce383, 0x0042049d,
1099     0x0089c278, 0xff54414d, 0x00531ded,
1100     0x004a5e07, 0xff53cf41, 0x006efbdc,
1101     0x00000002,//output gain
1102     0x00230204,//farrow
1103     0x000aaaab,
1104     0xffaaaaab,
1105     0xfffaaaab,
1106     0x00555555,
1107     0xff600000,
1108     0xfff55555,
1109     0x00155555,
1110     0x00055555,
1111     0xffeaaaab,
1112     0x00200000,
1113     0x00005102,//header
1114     0x00001685,//input gain
1115     0x00f53ae9, 0xff52f196, 0x003e3e08,
1116     0x00b9f857, 0xff5d8985, 0x0050070a,
1117     0x008c3e86, 0xff6053f0, 0x006d98ef,
1118     0x00000001//output gain
1119 };
1120
1121 static u32 coef_24to48[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1122     0x00006102,//header
1123     0x0001d727,//input gain
1124     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1125     0x00e55557, 0xffcadd5b, 0x003d80ba,
1126     0x00d13397, 0xfff232f8, 0x00683337,
1127     0x00000002//output gain
1128 };
1129
1130 static u32 coef_24to88[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1131     0x000c6102,//header
1132     0x0001d727,//input gain
1133     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1134     0x00e55557, 0xffcadd5b, 0x003d80ba,
1135     0x00d13397, 0xfff232f8, 0x00683337,
1136     0x00000002,//output gain
1137     0x00186102,//header
1138     0x000013d9,//input gain
1139     0x00ebd477, 0xff4ce383, 0x0042049d,
1140     0x0089c278, 0xff54414d, 0x00531ded,
1141     0x004a5e07, 0xff53cf41, 0x006efbdc,
1142     0x00000002,//output gain
1143     0x00246102,//header
1144     0x0000010a,//input gain
1145     0x00c93dc4, 0xff26f5f6, 0x005d1041,
1146     0x001002c4, 0xff245b76, 0x00666002,
1147     0xffc30a45, 0xff1baecd, 0x00765921,
1148     0x00000002,//output gain
1149     0x002f0204,//farrow
1150     0x000aaaab,
1151     0xffaaaaab,
1152     0xfffaaaab,
1153     0x00555555,
1154     0xff600000,
1155     0xfff55555,
1156     0x00155555,
1157     0x00055555,
1158     0xffeaaaab,
1159     0x00200000,
1160     0x00005102,//header
1161     0x00000138,//input gain
1162     0x00d5d232, 0xff2a3bf8, 0x005a785c,
1163     0x0034001b, 0xff283109, 0x006462a6,
1164     0xffe6746a, 0xff1fb09c, 0x00758a91,
1165     0x00000001//output gain
1166 };
1167
1168 static u32 coef_24to96[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1169     0x000c6102,//header
1170     0x0001d727,//input gain
1171     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1172     0x00e55557, 0xffcadd5b, 0x003d80ba,
1173     0x00d13397, 0xfff232f8, 0x00683337,
1174     0x00000002,//output gain
1175     0x00006102,//header
1176     0x000013d9,//input gain
1177     0x00ebd477, 0xff4ce383, 0x0042049d,
1178     0x0089c278, 0xff54414d, 0x00531ded,
1179     0x004a5e07, 0xff53cf41, 0x006efbdc,
1180     0x00000002//output gain
1181 };
1182
1183 static u32 coef_24to176[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1184     0x000c6102,//header
1185     0x0001d727,//input gain
1186     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1187     0x00e55557, 0xffcadd5b, 0x003d80ba,
1188     0x00d13397, 0xfff232f8, 0x00683337,
1189     0x00000002,//output gain
1190     0x00186102,//header
1191     0x000013d9,//input gain
1192     0x00ebd477, 0xff4ce383, 0x0042049d,
1193     0x0089c278, 0xff54414d, 0x00531ded,
1194     0x004a5e07, 0xff53cf41, 0x006efbdc,
1195     0x00000002,//output gain
1196     0x00246102,//header
1197     0x0000010a,//input gain
1198     0x00c93dc4, 0xff26f5f6, 0x005d1041,
1199     0x001002c4, 0xff245b76, 0x00666002,
1200     0xffc30a45, 0xff1baecd, 0x00765921,
1201     0x00000002,//output gain
1202     0x00000204,//farrow
1203     0x000aaaab,
1204     0xffaaaaab,
1205     0xfffaaaab,
1206     0x00555555,
1207     0xff600000,
1208     0xfff55555,
1209     0x00155555,
1210     0x00055555,
1211     0xffeaaaab,
1212     0x00200000
1213 };
1214
1215 static u32 coef_24to192[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1216     0x000c6102,//header
1217     0x0001d727,//input gain
1218     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1219     0x00e55557, 0xffcadd5b, 0x003d80ba,
1220     0x00d13397, 0xfff232f8, 0x00683337,
1221     0x00000002,//output gain
1222     0x00186102,//header
1223     0x000013d9,//input gain
1224     0x00ebd477, 0xff4ce383, 0x0042049d,
1225     0x0089c278, 0xff54414d, 0x00531ded,
1226     0x004a5e07, 0xff53cf41, 0x006efbdc,
1227     0x00000002,//output gain
1228     0x00006102,//header
1229     0x0000010a,//input gain
1230     0x00c93dc4, 0xff26f5f6, 0x005d1041,
1231     0x001002c4, 0xff245b76, 0x00666002,
1232     0xffc30a45, 0xff1baecd, 0x00765921,
1233     0x00000002//output gain
1234 };
1235
1236 static u32 coef_32to8[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1237     0x000c5102,//header
1238     0x000013d9,//input gain
1239     0x00ebd477, 0xff4ce383, 0x0042049d,
1240     0x0089c278, 0xff54414d, 0x00531ded,
1241     0x004a5e07, 0xff53cf41, 0x006efbdc,
1242     0x00000001,//output gain
1243     0x00005102,//header
1244     0x0001d727,//input gain
1245     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1246     0x00e55557, 0xffcadd5b, 0x003d80ba,
1247     0x00d13397, 0xfff232f8, 0x00683337,
1248     0x00000001//output gain
1249 };
1250
1251 static u32 coef_32to11[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1252     0x000ca102,//header
1253     0x000000af,//input gain
1254     0x00c65663, 0xff23d2ce, 0x005f97d6,
1255     0x00086ad6, 0xff20ec4f, 0x00683201,
1256     0xffbbbef6, 0xff184447, 0x00770963,
1257     0x00000003,//output gain
1258     0x00175204,//farrow
1259     0x000aaaab,
1260     0xffaaaaab,
1261     0xfffaaaab,
1262     0x00555555,
1263     0xff600000,
1264     0xfff55555,
1265     0x00155555,
1266     0x00055555,
1267     0xffeaaaab,
1268     0x00200000,
1269     0x0000d102,//header
1270     0x000013d9,//input gain
1271     0x00ebd477, 0xff4ce383, 0x0042049d,
1272     0x0089c278, 0xff54414d, 0x00531ded,
1273     0x004a5e07, 0xff53cf41, 0x006efbdc,
1274     0x00000001//output gain
1275 };
1276
1277 static u32 coef_32to16[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1278     0x00005102,//header
1279     0x0001d727,//input gain
1280     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1281     0x00e55557, 0xffcadd5b, 0x003d80ba,
1282     0x00d13397, 0xfff232f8, 0x00683337,
1283     0x00000001//output gain
1284 };
1285
1286 static u32 coef_32to22[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1287     0x000fa103,//header
1288     0x000001e0,//input gain
1289     0x00de44c0, 0xff380b7f, 0x004ffc73,
1290     0x00494b44, 0xff3d493a, 0x005908bf,
1291     0xffe9a3c8, 0xff425647, 0x006745f7,
1292     0xffc42d61, 0xff40a6c7, 0x00776709,
1293     0x00000003,//output gain
1294     0x001a5204,//farrow
1295     0x000aaaab,
1296     0xffaaaaab,
1297     0xfffaaaab,
1298     0x00555555,
1299     0xff600000,
1300     0xfff55555,
1301     0x00155555,
1302     0x00055555,
1303     0xffeaaaab,
1304     0x00200000,
1305     0x00005102,//header
1306     0x0001d727,//input gain
1307     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1308     0x00e55557, 0xffcadd5b, 0x003d80ba,
1309     0x00d13397, 0xfff232f8, 0x00683337,
1310     0x00000001//output gain
1311 };
1312
1313 static u32 coef_32to24[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1314     0x000ca102,//header
1315     0x000013d9,//input gain
1316     0x00ebd477, 0xff4ce383, 0x0042049d,
1317     0x0089c278, 0xff54414d, 0x00531ded,
1318     0x004a5e07, 0xff53cf41, 0x006efbdc,
1319     0x00000003,//output gain
1320     0x0000d102,//header
1321     0x000013d9,//input gain
1322     0x00ebd477, 0xff4ce383, 0x0042049d,
1323     0x0089c278, 0xff54414d, 0x00531ded,
1324     0x004a5e07, 0xff53cf41, 0x006efbdc,
1325     0x00000001//output gain
1326 };
1327
1328 static u32 coef_32to44[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1329     0x000c6102,//header
1330     0x0001d727,//input gain
1331     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1332     0x00e55557, 0xffcadd5b, 0x003d80ba,
1333     0x00d13397, 0xfff232f8, 0x00683337,
1334     0x00000002,//output gain
1335     0x0018a102,//header
1336     0x000005d6,//input gain
1337     0x00c6543e, 0xff342935, 0x0052f116,
1338     0x000a1d78, 0xff3330c0, 0x005f88a3,
1339     0xffbee7c0, 0xff2b5ba5, 0x0073eb26,
1340     0x00000003,//output gain
1341     0x00235204,//farrow
1342     0x000aaaab,
1343     0xffaaaaab,
1344     0xfffaaaab,
1345     0x00555555,
1346     0xff600000,
1347     0xfff55555,
1348     0x00155555,
1349     0x00055555,
1350     0xffeaaaab,
1351     0x00200000,
1352     0x00005102,//header
1353     0x0000015f,//input gain
1354     0x00a7909c, 0xff241c71, 0x005f5e00,
1355     0xffca77f4, 0xff20dd50, 0x006855eb,
1356     0xff86c552, 0xff18137a, 0x00773648,
1357     0x00000001//output gain
1358 };
1359
1360 static u32 coef_32to48[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1361     0x0015a105,//header
1362     0x00000292,//input gain
1363     0x00e4320a, 0xff41d2d9, 0x004911ac,
1364     0x005dd9e3, 0xff4c7d80, 0x0052103e,
1365     0xfff8ebef, 0xff5b6fab, 0x005f0a0d,
1366     0xffc4b414, 0xff68582c, 0x006b38e5,
1367     0xffabb861, 0xff704bec, 0x0074de52,
1368     0xffa19f4c, 0xff729059, 0x007c7e90,
1369     0x00000003,//output gain
1370     0x00005105,//header
1371     0x00000292,//input gain
1372     0x00e4320a, 0xff41d2d9, 0x004911ac,
1373     0x005dd9e3, 0xff4c7d80, 0x0052103e,
1374     0xfff8ebef, 0xff5b6fab, 0x005f0a0d,
1375     0xffc4b414, 0xff68582c, 0x006b38e5,
1376     0xffabb861, 0xff704bec, 0x0074de52,
1377     0xffa19f4c, 0xff729059, 0x007c7e90,
1378     0x00000001//output gain
1379 };
1380
1381 static u32 coef_32to88[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1382     0x000c6102,//header
1383     0x0001d727,//input gain
1384     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1385     0x00e55557, 0xffcadd5b, 0x003d80ba,
1386     0x00d13397, 0xfff232f8, 0x00683337,
1387     0x00000002,//output gain
1388     0x0018a102,//header
1389     0x000005d6,//input gain
1390     0x00c6543e, 0xff342935, 0x0052f116,
1391     0x000a1d78, 0xff3330c0, 0x005f88a3,
1392     0xffbee7c0, 0xff2b5ba5, 0x0073eb26,
1393     0x00000003,//output gain
1394     0x00230204,//farrow
1395     0x000aaaab,
1396     0xffaaaaab,
1397     0xfffaaaab,
1398     0x00555555,
1399     0xff600000,
1400     0xfff55555,
1401     0x00155555,
1402     0x00055555,
1403     0xffeaaaab,
1404     0x00200000,
1405     0x00005102,//header
1406     0x000005f3,//input gain
1407     0x00d816d6, 0xff385383, 0x004fe566,
1408     0x003c548d, 0xff38c23d, 0x005d0b1c,
1409     0xfff02f7d, 0xff31e983, 0x0072d65d,
1410     0x00000001//output gain
1411 };
1412
1413 static u32 coef_32to96[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1414     0x0000a105,//header
1415     0x00000292,//input gain
1416     0x00e4320a, 0xff41d2d9, 0x004911ac,
1417     0x005dd9e3, 0xff4c7d80, 0x0052103e,
1418     0xfff8ebef, 0xff5b6fab, 0x005f0a0d,
1419     0xffc4b414, 0xff68582c, 0x006b38e5,
1420     0xffabb861, 0xff704bec, 0x0074de52,
1421     0xffa19f4c, 0xff729059, 0x007c7e90,
1422     0x00000003//output gain
1423 };
1424
1425 static u32 coef_32to176[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1426     0x000c6102,//header
1427     0x0001d727,//input gain
1428     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1429     0x00e55557, 0xffcadd5b, 0x003d80ba,
1430     0x00d13397, 0xfff232f8, 0x00683337,
1431     0x00000002,//output gain
1432     0x0018a102,//header
1433     0x000005d6,//input gain
1434     0x00c6543e, 0xff342935, 0x0052f116,
1435     0x000a1d78, 0xff3330c0, 0x005f88a3,
1436     0xffbee7c0, 0xff2b5ba5, 0x0073eb26,
1437     0x00000003,//output gain
1438     0x00000204,//farrow
1439     0x000aaaab,
1440     0xffaaaaab,
1441     0xfffaaaab,
1442     0x00555555,
1443     0xff600000,
1444     0xfff55555,
1445     0x00155555,
1446     0x00055555,
1447     0xffeaaaab,
1448     0x00200000
1449 };
1450
1451 static u32 coef_32to192[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1452     0x000c6102,//header
1453     0x0001d727,//input gain
1454     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1455     0x00e55557, 0xffcadd5b, 0x003d80ba,
1456     0x00d13397, 0xfff232f8, 0x00683337,
1457     0x00000002,//output gain
1458     0x0000a102,//header
1459     0x000005d6,//input gain
1460     0x00c6543e, 0xff342935, 0x0052f116,
1461     0x000a1d78, 0xff3330c0, 0x005f88a3,
1462     0xffbee7c0, 0xff2b5ba5, 0x0073eb26,
1463     0x00000003//output gain
1464 };
1465
1466 static u32 coef_44to8[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1467     0x00120104,//IIR Filter
1468     0x00000af2,//input gain
1469     0x0057eebe, 0xff1e9863, 0x00652604,
1470     0xff7206ea, 0xff22ad7e, 0x006d47e1,
1471     0xff42a4d7, 0xff26e722, 0x0075fd83,
1472     0xff352f66, 0xff29312b, 0x007b986b,
1473     0xff310a07, 0xff296f51, 0x007eca7c,
1474     0x00000001,//output gain
1475     0x001d9204,//Farrow Filter + decimation
1476     0x000aaaab,
1477     0xffaaaaab,
1478     0xfffaaaab,
1479     0x00555555,
1480     0xff600000,
1481     0xfff55555,
1482     0x00155555,
1483     0x00055555,
1484     0xffeaaaab,
1485     0x00200000,
1486     0x00005105,//IIR Filter + Decimator
1487     0x0000d649,//input gain
1488     0x00e87afb, 0xff5f69d0, 0x003df3cf,
1489     0x007ce488, 0xff99a5c8, 0x0056a6a0,
1490     0x00344928, 0xffcba3e5, 0x006be470,
1491     0x00137aa7, 0xffe60276, 0x00773410,
1492     0x0005fa2a, 0xfff1ac11, 0x007c795b,
1493     0x00012d36, 0xfff5eca2, 0x007f10ef,
1494     0x00000001//output gain
1495 };
1496
1497 static u32 coef_44to11[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1498     0x000c5102,//header
1499     0x000013d9,//input gain
1500     0x00ebd477, 0xff4ce383, 0x0042049d,
1501     0x0089c278, 0xff54414d, 0x00531ded,
1502     0x004a5e07, 0xff53cf41, 0x006efbdc,
1503     0x00000001,//output gain
1504     0x00005102,//header
1505     0x0001d727,//input gain
1506     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1507     0x00e55557, 0xffcadd5b, 0x003d80ba,
1508     0x00d13397, 0xfff232f8, 0x00683337,
1509     0x00000001//output gain
1510 };
1511
1512 static u32 coef_44to16[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1513     0x00126104,//IIR Filter + interpolation
1514     0x00000af2,//input gain
1515     0x0057eebe, 0xff1e9863, 0x00652604,
1516     0xff7206ea, 0xff22ad7e, 0x006d47e1,
1517     0xff42a4d7, 0xff26e722, 0x0075fd83,
1518     0xff352f66, 0xff29312b, 0x007b986b,
1519     0xff310a07, 0xff296f51, 0x007eca7c,
1520     0x00000002,//output gain
1521     0x001d9204,//Farrow Filter + decimation
1522     0x000aaaab,
1523     0xffaaaaab,
1524     0xfffaaaab,
1525     0x00555555,
1526     0xff600000,
1527     0xfff55555,
1528     0x00155555,
1529     0x00055555,
1530     0xffeaaaab,
1531     0x00200000,
1532     0x00005105,//IIR Filter + Decimator
1533     0x0000d649,//input gain
1534     0x00e87afb, 0xff5f69d0, 0x003df3cf,
1535     0x007ce488, 0xff99a5c8, 0x0056a6a0,
1536     0x00344928, 0xffcba3e5, 0x006be470,
1537     0x00137aa7, 0xffe60276, 0x00773410,
1538     0x0005fa2a, 0xfff1ac11, 0x007c795b,
1539     0x00012d36, 0xfff5eca2, 0x007f10ef,
1540     0x00000001//output gain
1541 };
1542
1543 static u32 coef_44to22[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1544     0x00005102,//header
1545     0x0001d727,//input gain
1546     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1547     0x00e55557, 0xffcadd5b, 0x003d80ba,
1548     0x00d13397, 0xfff232f8, 0x00683337,
1549     0x00000001//output gain
1550 };
1551
1552 static u32 coef_44to24[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1553     0x000c6102,//header
1554     0x00001685,//input gain
1555     0x00f53ae9, 0xff52f196, 0x003e3e08,
1556     0x00b9f857, 0xff5d8985, 0x0050070a,
1557     0x008c3e86, 0xff6053f0, 0x006d98ef,
1558     0x00000002,//output gain
1559     0x00175204,//farrow
1560     0x000aaaab,
1561     0xffaaaaab,
1562     0xfffaaaab,
1563     0x00555555,
1564     0xff600000,
1565     0xfff55555,
1566     0x00155555,
1567     0x00055555,
1568     0xffeaaaab,
1569     0x00200000,
1570     0x00005102,//header
1571     0x0001d727,//input gain
1572     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1573     0x00e55557, 0xffcadd5b, 0x003d80ba,
1574     0x00d13397, 0xfff232f8, 0x00683337,
1575     0x00000001//output gain
1576 };
1577
1578 static u32 coef_44to32[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1579     0x000c6102,//header
1580     0x0000015f,//input gain
1581     0x00a7909c, 0xff241c71, 0x005f5e00,
1582     0xffca77f4, 0xff20dd50, 0x006855eb,
1583     0xff86c552, 0xff18137a, 0x00773648,
1584     0x00000002,//output gain
1585     0x00186102,//header
1586     0x000005f3,//input gain
1587     0x00d816d6, 0xff385383, 0x004fe566,
1588     0x003c548d, 0xff38c23d, 0x005d0b1c,
1589     0xfff02f7d, 0xff31e983, 0x0072d65d,
1590     0x00000002,//output gain
1591     0x00239204,//farrow
1592     0x000aaaab,
1593     0xffaaaaab,
1594     0xfffaaaab,
1595     0x00555555,
1596     0xff600000,
1597     0xfff55555,
1598     0x00155555,
1599     0x00055555,
1600     0xffeaaaab,
1601     0x00200000,
1602     0x00005102,//header
1603     0x0001d727,//input gain
1604     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1605     0x00e55557, 0xffcadd5b, 0x003d80ba,
1606     0x00d13397, 0xfff232f8, 0x00683337,
1607     0x00000001//output gain
1608 };
1609
1610 static u32 coef_44to48[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1611     0x000c6102,//header
1612     0x0001d727,//input gain
1613     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1614     0x00e55557, 0xffcadd5b, 0x003d80ba,
1615     0x00d13397, 0xfff232f8, 0x00683337,
1616     0x00000002,//output gain
1617     0x00186102,//header
1618     0x000013d9,//input gain
1619     0x00ebd477, 0xff4ce383, 0x0042049d,
1620     0x0089c278, 0xff54414d, 0x00531ded,
1621     0x004a5e07, 0xff53cf41, 0x006efbdc,
1622     0x00000002,//output gain
1623     0x00235204,//farrow
1624     0x000aaaab,
1625     0xffaaaaab,
1626     0xfffaaaab,
1627     0x00555555,
1628     0xff600000,
1629     0xfff55555,
1630     0x00155555,
1631     0x00055555,
1632     0xffeaaaab,
1633     0x00200000,
1634     0x00005102,//header
1635     0x0001d029,//input gain
1636     0x00f2a98b, 0xff92aa71, 0x001fcd16,
1637     0x00ae9004, 0xffb85140, 0x0041813a,
1638     0x007f8ed1, 0xffd585fc, 0x006a69e6,
1639     0x00000001//output gain
1640 };
1641
1642 static u32 coef_44to88[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1643     0x00006102,//header
1644     0x0001d727,//input gain
1645     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1646     0x00e55557, 0xffcadd5b, 0x003d80ba,
1647     0x00d13397, 0xfff232f8, 0x00683337,
1648     0x00000002//output gain
1649 };
1650
1651 static u32 coef_44to96[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1652     0x000c6102,//header
1653     0x0001d727,//input gain
1654     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1655     0x00e55557, 0xffcadd5b, 0x003d80ba,
1656     0x00d13397, 0xfff232f8, 0x00683337,
1657     0x00000002,//output gain
1658     0x00186102,//header
1659     0x000013d9,//input gain
1660     0x00ebd477, 0xff4ce383, 0x0042049d,
1661     0x0089c278, 0xff54414d, 0x00531ded,
1662     0x004a5e07, 0xff53cf41, 0x006efbdc,
1663     0x00000002,//output gain
1664     0x00005204,//farrow
1665     0x000aaaab,
1666     0xffaaaaab,
1667     0xfffaaaab,
1668     0x00555555,
1669     0xff600000,
1670     0xfff55555,
1671     0x00155555,
1672     0x00055555,
1673     0xffeaaaab,
1674     0x00200000
1675 };
1676
1677 static u32 coef_44to176[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1678     0x000c6102,//header
1679     0x0001d727,//input gain
1680     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1681     0x00e55557, 0xffcadd5b, 0x003d80ba,
1682     0x00d13397, 0xfff232f8, 0x00683337,
1683     0x00000002,//output gain
1684     0x00006102,//header
1685     0x000013d9,//input gain
1686     0x00ebd477, 0xff4ce383, 0x0042049d,
1687     0x0089c278, 0xff54414d, 0x00531ded,
1688     0x004a5e07, 0xff53cf41, 0x006efbdc,
1689     0x00000002//output gain
1690 };
1691
1692 static u32 coef_44to192[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1693     0x000c6102,//header
1694     0x0001d727,//input gain
1695     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1696     0x00e55557, 0xffcadd5b, 0x003d80ba,
1697     0x00d13397, 0xfff232f8, 0x00683337,
1698     0x00000002,//output gain
1699     0x00186102,//header
1700     0x000013d9,//input gain
1701     0x00ebd477, 0xff4ce383, 0x0042049d,
1702     0x0089c278, 0xff54414d, 0x00531ded,
1703     0x004a5e07, 0xff53cf41, 0x006efbdc,
1704     0x00000002,//output gain
1705     0x00246102,//header
1706     0x0000010a,//input gain
1707     0x00c93dc4, 0xff26f5f6, 0x005d1041,
1708     0x001002c4, 0xff245b76, 0x00666002,
1709     0xffc30a45, 0xff1baecd, 0x00765921,
1710     0x00000002,//output gain
1711     0x00005204,//farrow
1712     0x000aaaab,
1713     0xffaaaaab,
1714     0xfffaaaab,
1715     0x00555555,
1716     0xff600000,
1717     0xfff55555,
1718     0x00155555,
1719     0x00055555,
1720     0xffeaaaab,
1721     0x00200000
1722 };
1723
1724 static u32 coef_48to8[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1725     0x000c9102,//IIR Filter + Decimator
1726     0x00000e00,//input gain
1727     0x00e2e000, 0xff6e1a00, 0x002aaa00,
1728     0x00610a00, 0xff5dda00, 0x003ccc00,
1729     0x00163a00, 0xff3c0400, 0x00633200,
1730     0x00000001,//output gain
1731     0x00005105,//IIR Filter + Decimator
1732     0x0000d649,//input gain
1733     0x00e87afb, 0xff5f69d0, 0x003df3cf,
1734     0x007ce488, 0xff99a5c8, 0x0056a6a0,
1735     0x00344928, 0xffcba3e5, 0x006be470,
1736     0x00137aa7, 0xffe60276, 0x00773410,
1737     0x0005fa2a, 0xfff1ac11, 0x007c795b,
1738     0x00012d36, 0xfff5eca2, 0x007f10ef,
1739     0x00000001//output gain
1740 };
1741
1742 static u32 coef_48to11[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1743     0x000c6102,//header
1744     0x000000af,//input gain
1745     0x00c65663, 0xff23d2ce, 0x005f97d6,
1746     0x00086ad6, 0xff20ec4f, 0x00683201,
1747     0xffbbbef6, 0xff184447, 0x00770963,
1748     0x00000002,//output gain
1749     0x00175204,//farrow
1750     0x000aaaab,
1751     0xffaaaaab,
1752     0xfffaaaab,
1753     0x00555555,
1754     0xff600000,
1755     0xfff55555,
1756     0x00155555,
1757     0x00055555,
1758     0xffeaaaab,
1759     0x00200000,
1760     0x00235102,//header
1761     0x000013d9,//input gain
1762     0x00ebd477, 0xff4ce383, 0x0042049d,
1763     0x0089c278, 0xff54414d, 0x00531ded,
1764     0x004a5e07, 0xff53cf41, 0x006efbdc,
1765     0x00000001,//output gain
1766     0x00005102,//header
1767     0x0001d727,//input gain
1768     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1769     0x00e55557, 0xffcadd5b, 0x003d80ba,
1770     0x00d13397, 0xfff232f8, 0x00683337,
1771     0x00000001//output gain
1772 };
1773
1774 static u32 coef_48to16[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1775     0x00009105,//IIR Filter + Decimator
1776     0x00000784,//input gain
1777     0x00cc516e, 0xff2c9639, 0x005ad5b3,
1778     0x0013ad0d, 0xff3d4799, 0x0063ce75,
1779     0xffb6f398, 0xff5138d1, 0x006e9e1f,
1780     0xff9186e5, 0xff5f96a4, 0x0076a86e,
1781     0xff82089c, 0xff676b81, 0x007b9f8a,
1782     0xff7c48a5, 0xff6a31e7, 0x007ebb7b,
1783     0x00000001//output gain
1784 };
1785
1786 static u32 coef_48to22[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1787     0x000f6103,//header
1788     0x000001e0,//input gain
1789     0x00de44c0, 0xff380b7f, 0x004ffc73,
1790     0x00494b44, 0xff3d493a, 0x005908bf,
1791     0xffe9a3c8, 0xff425647, 0x006745f7,
1792     0xffc42d61, 0xff40a6c7, 0x00776709,
1793     0x00000002,//output gain
1794     0x001a5204,//farrow
1795     0x000aaaab,
1796     0xffaaaaab,
1797     0xfffaaaab,
1798     0x00555555,
1799     0xff600000,
1800     0xfff55555,
1801     0x00155555,
1802     0x00055555,
1803     0xffeaaaab,
1804     0x00200000,
1805     0x00005102,//header
1806     0x0001d727,//input gain
1807     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1808     0x00e55557, 0xffcadd5b, 0x003d80ba,
1809     0x00d13397, 0xfff232f8, 0x00683337,
1810     0x00000001//output gain
1811 };
1812
1813 static u32 coef_48to24[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1814     0x00005102,//header
1815     0x0001d727,//input gain
1816     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1817     0x00e55557, 0xffcadd5b, 0x003d80ba,
1818     0x00d13397, 0xfff232f8, 0x00683337,
1819     0x00000001//output gain
1820 };
1821
1822 static u32 coef_48to32[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1823     0x00156105,//header
1824     0x00000292,//input gain
1825     0x00e4320a, 0xff41d2d9, 0x004911ac,
1826     0x005dd9e3, 0xff4c7d80, 0x0052103e,
1827     0xfff8ebef, 0xff5b6fab, 0x005f0a0d,
1828     0xffc4b414, 0xff68582c, 0x006b38e5,
1829     0xffabb861, 0xff704bec, 0x0074de52,
1830     0xffa19f4c, 0xff729059, 0x007c7e90,
1831     0x00000002,//output gain
1832     0x00009105,//header
1833     0x00000292,//input gain
1834     0x00e4320a, 0xff41d2d9, 0x004911ac,
1835     0x005dd9e3, 0xff4c7d80, 0x0052103e,
1836     0xfff8ebef, 0xff5b6fab, 0x005f0a0d,
1837     0xffc4b414, 0xff68582c, 0x006b38e5,
1838     0xffabb861, 0xff704bec, 0x0074de52,
1839     0xffa19f4c, 0xff729059, 0x007c7e90,
1840     0x00000001//output gain
1841 };
1842
1843 static u32 coef_48to44[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1844     0x000c6102,//header
1845     0x0001d029,//input gain
1846     0x00f2a98b, 0xff92aa71, 0x001fcd16,
1847     0x00ae9004, 0xffb85140, 0x0041813a,
1848     0x007f8ed1, 0xffd585fc, 0x006a69e6,
1849     0x00000002,//output gain
1850     0x001b6103,//header
1851     0x000001e0,//input gain
1852     0x00de44c0, 0xff380b7f, 0x004ffc73,
1853     0x00494b44, 0xff3d493a, 0x005908bf,
1854     0xffe9a3c8, 0xff425647, 0x006745f7,
1855     0xffc42d61, 0xff40a6c7, 0x00776709,
1856     0x00000002,//output gain
1857     0x00265204,//farrow
1858     0x000aaaab,
1859     0xffaaaaab,
1860     0xfffaaaab,
1861     0x00555555,
1862     0xff600000,
1863     0xfff55555,
1864     0x00155555,
1865     0x00055555,
1866     0xffeaaaab,
1867     0x00200000,
1868     0x00005102,//header
1869     0x0001d727,//input gain
1870     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1871     0x00e55557, 0xffcadd5b, 0x003d80ba,
1872     0x00d13397, 0xfff232f8, 0x00683337,
1873     0x00000001//output gain
1874 };
1875
1876 static u32 coef_48to88[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1877     0x000c6102,//header
1878     0x0001d727,//input gain
1879     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1880     0x00e55557, 0xffcadd5b, 0x003d80ba,
1881     0x00d13397, 0xfff232f8, 0x00683337,
1882     0x00000002,//output gain
1883     0x00186102,//header
1884     0x000013d9,//input gain
1885     0x00ebd477, 0xff4ce383, 0x0042049d,
1886     0x0089c278, 0xff54414d, 0x00531ded,
1887     0x004a5e07, 0xff53cf41, 0x006efbdc,
1888     0x00000002,//output gain
1889     0x00230204,//farrow
1890     0x000aaaab,
1891     0xffaaaaab,
1892     0xfffaaaab,
1893     0x00555555,
1894     0xff600000,
1895     0xfff55555,
1896     0x00155555,
1897     0x00055555,
1898     0xffeaaaab,
1899     0x00200000,
1900     0x00005102,//header
1901     0x00001685,//input gain
1902     0x00f53ae9, 0xff52f196, 0x003e3e08,
1903     0x00b9f857, 0xff5d8985, 0x0050070a,
1904     0x008c3e86, 0xff6053f0, 0x006d98ef,
1905     0x00000001//output gain
1906 };
1907
1908 static u32 coef_48to96[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1909     0x00006102,//header
1910     0x0001d727,//input gain
1911     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1912     0x00e55557, 0xffcadd5b, 0x003d80ba,
1913     0x00d13397, 0xfff232f8, 0x00683337,
1914     0x00000002//output gain
1915 };
1916
1917 static u32 coef_48to176[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1918     0x000c6102,//header
1919     0x0001d727,//input gain
1920     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1921     0x00e55557, 0xffcadd5b, 0x003d80ba,
1922     0x00d13397, 0xfff232f8, 0x00683337,
1923     0x00000002,//output gain
1924     0x00186102,//header
1925     0x000013d9,//input gain
1926     0x00ebd477, 0xff4ce383, 0x0042049d,
1927     0x0089c278, 0xff54414d, 0x00531ded,
1928     0x004a5e07, 0xff53cf41, 0x006efbdc,
1929     0x00000002,//output gain
1930     0x00246102,//header
1931     0x0000010a,//input gain
1932     0x00c93dc4, 0xff26f5f6, 0x005d1041,
1933     0x001002c4, 0xff245b76, 0x00666002,
1934     0xffc30a45, 0xff1baecd, 0x00765921,
1935     0x00000002,//output gain
1936     0x002f0204,//farrow
1937     0x000aaaab,
1938     0xffaaaaab,
1939     0xfffaaaab,
1940     0x00555555,
1941     0xff600000,
1942     0xfff55555,
1943     0x00155555,
1944     0x00055555,
1945     0xffeaaaab,
1946     0x00200000,
1947     0x00005102,//header
1948     0x00000138,//input gain
1949     0x00d5d232, 0xff2a3bf8, 0x005a785c,
1950     0x0034001b, 0xff283109, 0x006462a6,
1951     0xffe6746a, 0xff1fb09c, 0x00758a91,
1952     0x00000001//output gain
1953 };
1954
1955 static u32 coef_48to192[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1956     0x000c6102,//header
1957     0x0001d727,//input gain
1958     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1959     0x00e55557, 0xffcadd5b, 0x003d80ba,
1960     0x00d13397, 0xfff232f8, 0x00683337,
1961     0x00000002,//output gain
1962     0x00006102,//header
1963     0x000013d9,//input gain
1964     0x00ebd477, 0xff4ce383, 0x0042049d,
1965     0x0089c278, 0xff54414d, 0x00531ded,
1966     0x004a5e07, 0xff53cf41, 0x006efbdc,
1967     0x00000002//output gain
1968 };
1969
1970 static u32 coef_88to8[TEGRA210_SFC_COEF_RAM_DEPTH] = {
1971     0x000c0102,//header
1972     0x00000057,//input gain
1973     0x00a8e717, 0xff1c748d, 0x0065b976,
1974     0xffcbccab, 0xff190aff, 0x006cc1cf,
1975     0xff871ce1, 0xff10d878, 0x0078cfc5,
1976     0x00000001,//output gain
1977     0x00179204,//farrow
1978     0x000aaaab,
1979     0xffaaaaab,
1980     0xfffaaaab,
1981     0x00555555,
1982     0xff600000,
1983     0xfff55555,
1984     0x00155555,
1985     0x00055555,
1986     0xffeaaaab,
1987     0x00200000,
1988     0x00235102,//header
1989     0x000013d9,//input gain
1990     0x00ebd477, 0xff4ce383, 0x0042049d,
1991     0x0089c278, 0xff54414d, 0x00531ded,
1992     0x004a5e07, 0xff53cf41, 0x006efbdc,
1993     0x00000001,//output gain
1994     0x00005102,//header
1995     0x0001d727,//input gain
1996     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
1997     0x00e55557, 0xffcadd5b, 0x003d80ba,
1998     0x00d13397, 0xfff232f8, 0x00683337,
1999     0x00000001//output gain
2000 };
2001
2002 static u32 coef_88to11[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2003     0x000c5102,//header
2004     0x0000010a,//input gain
2005     0x00c93dc4, 0xff26f5f6, 0x005d1041,
2006     0x001002c4, 0xff245b76, 0x00666002,
2007     0xffc30a45, 0xff1baecd, 0x00765921,
2008     0x00000001,//output gain
2009     0x00185102,//header
2010     0x000013d9,//input gain
2011     0x00ebd477, 0xff4ce383, 0x0042049d,
2012     0x0089c278, 0xff54414d, 0x00531ded,
2013     0x004a5e07, 0xff53cf41, 0x006efbdc,
2014     0x00000001,//output gain
2015     0x00005102,//header
2016     0x0001d727,//input gain
2017     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
2018     0x00e55557, 0xffcadd5b, 0x003d80ba,
2019     0x00d13397, 0xfff232f8, 0x00683337,
2020     0x00000001//output gain
2021 };
2022
2023 static u32 coef_88to16[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2024     0x000c0102,//header
2025     0x000005f3,//input gain
2026     0x00d816d6, 0xff385383, 0x004fe566,
2027     0x003c548d, 0xff38c23d, 0x005d0b1c,
2028     0xfff02f7d, 0xff31e983, 0x0072d65d,
2029     0x00000001,//output gain
2030     0x00179204,//farrow
2031     0x000aaaab,
2032     0xffaaaaab,
2033     0xfffaaaab,
2034     0x00555555,
2035     0xff600000,
2036     0xfff55555,
2037     0x00155555,
2038     0x00055555,
2039     0xffeaaaab,
2040     0x00200000,
2041     0x00005102,//header
2042     0x0001d727,//input gain
2043     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
2044     0x00e55557, 0xffcadd5b, 0x003d80ba,
2045     0x00d13397, 0xfff232f8, 0x00683337,
2046     0x00000001//output gain
2047 };
2048
2049 static u32 coef_88to22[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2050     0x000c5102,//header
2051     0x000013d9,//input gain
2052     0x00ebd477, 0xff4ce383, 0x0042049d,
2053     0x0089c278, 0xff54414d, 0x00531ded,
2054     0x004a5e07, 0xff53cf41, 0x006efbdc,
2055     0x00000001,//output gain
2056     0x00005102,//header
2057     0x0001d727,//input gain
2058     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
2059     0x00e55557, 0xffcadd5b, 0x003d80ba,
2060     0x00d13397, 0xfff232f8, 0x00683337,
2061     0x00000001//output gain
2062 };
2063
2064 static u32 coef_88to24[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2065     0x000c0102,//header
2066     0x00001685,//input gain
2067     0x00f53ae9, 0xff52f196, 0x003e3e08,
2068     0x00b9f857, 0xff5d8985, 0x0050070a,
2069     0x008c3e86, 0xff6053f0, 0x006d98ef,
2070     0x00000001,//output gain
2071     0x00175204,//farrow
2072     0x000aaaab,
2073     0xffaaaaab,
2074     0xfffaaaab,
2075     0x00555555,
2076     0xff600000,
2077     0xfff55555,
2078     0x00155555,
2079     0x00055555,
2080     0xffeaaaab,
2081     0x00200000,
2082     0x00005102,//header
2083     0x0001d727,//input gain
2084     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
2085     0x00e55557, 0xffcadd5b, 0x003d80ba,
2086     0x00d13397, 0xfff232f8, 0x00683337,
2087     0x00000001//output gain
2088 };
2089
2090 static u32 coef_88to32[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2091     0x000c6102,//header
2092     0x000005f3,//input gain
2093     0x00d816d6, 0xff385383, 0x004fe566,
2094     0x003c548d, 0xff38c23d, 0x005d0b1c,
2095     0xfff02f7d, 0xff31e983, 0x0072d65d,
2096     0x00000002,//output gain
2097     0x00179204,//farrow
2098     0x000aaaab,
2099     0xffaaaaab,
2100     0xfffaaaab,
2101     0x00555555,
2102     0xff600000,
2103     0xfff55555,
2104     0x00155555,
2105     0x00055555,
2106     0xffeaaaab,
2107     0x00200000,
2108     0x00005102,//header
2109     0x0001d727,//input gain
2110     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
2111     0x00e55557, 0xffcadd5b, 0x003d80ba,
2112     0x00d13397, 0xfff232f8, 0x00683337,
2113     0x00000001//output gain
2114 };
2115
2116 static u32 coef_88to44[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2117     0x00005102,//header
2118     0x0001d727,//input gain
2119     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
2120     0x00e55557, 0xffcadd5b, 0x003d80ba,
2121     0x00d13397, 0xfff232f8, 0x00683337,
2122     0x00000001//output gain
2123 };
2124
2125 static u32 coef_88to48[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2126     0x000c6102,//header
2127     0x00001685,//input gain
2128     0x00f53ae9, 0xff52f196, 0x003e3e08,
2129     0x00b9f857, 0xff5d8985, 0x0050070a,
2130     0x008c3e86, 0xff6053f0, 0x006d98ef,
2131     0x00000002,//output gain
2132     0x00175204,//farrow
2133     0x000aaaab,
2134     0xffaaaaab,
2135     0xfffaaaab,
2136     0x00555555,
2137     0xff600000,
2138     0xfff55555,
2139     0x00155555,
2140     0x00055555,
2141     0xffeaaaab,
2142     0x00200000,
2143     0x00005102,//header
2144     0x0001d727,//input gain
2145     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
2146     0x00e55557, 0xffcadd5b, 0x003d80ba,
2147     0x00d13397, 0xfff232f8, 0x00683337,
2148     0x00000001//output gain
2149 };
2150
2151 static u32 coef_88to96[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2152     0x000c6102,//header
2153     0x000013d9,//input gain
2154     0x00ebd477, 0xff4ce383, 0x0042049d,
2155     0x0089c278, 0xff54414d, 0x00531ded,
2156     0x004a5e07, 0xff53cf41, 0x006efbdc,
2157     0x00000002,//output gain
2158     0x00005204,//farrow
2159     0x000aaaab,
2160     0xffaaaaab,
2161     0xfffaaaab,
2162     0x00555555,
2163     0xff600000,
2164     0xfff55555,
2165     0x00155555,
2166     0x00055555,
2167     0xffeaaaab,
2168     0x00200000
2169 };
2170
2171 static u32 coef_88to176[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2172     0x00006102,//header
2173     0x000013d9,//input gain
2174     0x00ebd477, 0xff4ce383, 0x0042049d,
2175     0x0089c278, 0xff54414d, 0x00531ded,
2176     0x004a5e07, 0xff53cf41, 0x006efbdc,
2177     0x00000002//output gain
2178 };
2179
2180 static u32 coef_88to192[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2181     0x000c6102,//header
2182     0x000013d9,//input gain
2183     0x00ebd477, 0xff4ce383, 0x0042049d,
2184     0x0089c278, 0xff54414d, 0x00531ded,
2185     0x004a5e07, 0xff53cf41, 0x006efbdc,
2186     0x00000002,//output gain
2187     0x00186102,//header
2188     0x0000010a,//input gain
2189     0x00c93dc4, 0xff26f5f6, 0x005d1041,
2190     0x001002c4, 0xff245b76, 0x00666002,
2191     0xffc30a45, 0xff1baecd, 0x00765921,
2192     0x00000002,//output gain
2193     0x00005204,//farrow
2194     0x000aaaab,
2195     0xffaaaaab,
2196     0xfffaaaab,
2197     0x00555555,
2198     0xff600000,
2199     0xfff55555,
2200     0x00155555,
2201     0x00055555,
2202     0xffeaaaab,
2203     0x00200000
2204 };
2205
2206 static u32 coef_96to8[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2207     0x000c9102,//header
2208     0x0000007d,//input gain
2209     0x007d1f20, 0xff1a540e, 0x00678bf9,
2210     0xff916625, 0xff16b0ff, 0x006e433a,
2211     0xff5af660, 0xff0eb91f, 0x00797356,
2212     0x00000001,//output gain
2213     0x00185102,//header
2214     0x000013d9,//input gain
2215     0x00ebd477, 0xff4ce383, 0x0042049d,
2216     0x0089c278, 0xff54414d, 0x00531ded,
2217     0x004a5e07, 0xff53cf41, 0x006efbdc,
2218     0x00000001,//output gain
2219     0x00005102,//header
2220     0x0001d727,//input gain
2221     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
2222     0x00e55557, 0xffcadd5b, 0x003d80ba,
2223     0x00d13397, 0xfff232f8, 0x00683337,
2224     0x00000001//output gain
2225 };
2226
2227 static u32 coef_96to11[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2228     0x000c0102,//header
2229     0x000000af,//input gain
2230     0x00c65663, 0xff23d2ce, 0x005f97d6,
2231     0x00086ad6, 0xff20ec4f, 0x00683201,
2232     0xffbbbef6, 0xff184447, 0x00770963,
2233     0x00000001,//output gain
2234     0x00175204,//farrow
2235     0x000aaaab,
2236     0xffaaaaab,
2237     0xfffaaaab,
2238     0x00555555,
2239     0xff600000,
2240     0xfff55555,
2241     0x00155555,
2242     0x00055555,
2243     0xffeaaaab,
2244     0x00200000,
2245     0x00235102,//header
2246     0x000013d9,//input gain
2247     0x00ebd477, 0xff4ce383, 0x0042049d,
2248     0x0089c278, 0xff54414d, 0x00531ded,
2249     0x004a5e07, 0xff53cf41, 0x006efbdc,
2250     0x00000001,//output gain
2251     0x00005102,//header
2252     0x0001d727,//input gain
2253     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
2254     0x00e55557, 0xffcadd5b, 0x003d80ba,
2255     0x00d13397, 0xfff232f8, 0x00683337,
2256     0x00000001//output gain
2257 };
2258
2259 static u32 coef_96to16[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2260     0x000c9102,//header
2261     0x000005d6,//input gain
2262     0x00c6543e, 0xff342935, 0x0052f116,
2263     0x000a1d78, 0xff3330c0, 0x005f88a3,
2264     0xffbee7c0, 0xff2b5ba5, 0x0073eb26,
2265     0x00000001,//output gain
2266     0x00005102,//header
2267     0x0001d727,//input gain
2268     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
2269     0x00e55557, 0xffcadd5b, 0x003d80ba,
2270     0x00d13397, 0xfff232f8, 0x00683337,
2271     0x00000001//output gain
2272 };
2273
2274 static u32 coef_96to22[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2275     0x000c6102,//header
2276     0x000000af,//input gain
2277     0x00c65663, 0xff23d2ce, 0x005f97d6,
2278     0x00086ad6, 0xff20ec4f, 0x00683201,
2279     0xffbbbef6, 0xff184447, 0x00770963,
2280     0x00000002,//output gain
2281     0x00175204,//farrow
2282     0x000aaaab,
2283     0xffaaaaab,
2284     0xfffaaaab,
2285     0x00555555,
2286     0xff600000,
2287     0xfff55555,
2288     0x00155555,
2289     0x00055555,
2290     0xffeaaaab,
2291     0x00200000,
2292     0x00235102,//header
2293     0x000013d9,//input gain
2294     0x00ebd477, 0xff4ce383, 0x0042049d,
2295     0x0089c278, 0xff54414d, 0x00531ded,
2296     0x004a5e07, 0xff53cf41, 0x006efbdc,
2297     0x00000001,//output gain
2298     0x00005102,//header
2299     0x0001d727,//input gain
2300     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
2301     0x00e55557, 0xffcadd5b, 0x003d80ba,
2302     0x00d13397, 0xfff232f8, 0x00683337,
2303     0x00000001//output gain
2304 };
2305
2306 static u32 coef_96to24[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2307     0x000c5102,//header
2308     0x000013d9,//input gain
2309     0x00ebd477, 0xff4ce383, 0x0042049d,
2310     0x0089c278, 0xff54414d, 0x00531ded,
2311     0x004a5e07, 0xff53cf41, 0x006efbdc,
2312     0x00000001,//output gain
2313     0x00005102,//header
2314     0x0001d727,//input gain
2315     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
2316     0x00e55557, 0xffcadd5b, 0x003d80ba,
2317     0x00d13397, 0xfff232f8, 0x00683337,
2318     0x00000001//output gain
2319 };
2320
2321 static u32 coef_96to32[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2322     0x00009105,//header
2323     0x00000292,//input gain
2324     0x00e4320a, 0xff41d2d9, 0x004911ac,
2325     0x005dd9e3, 0xff4c7d80, 0x0052103e,
2326     0xfff8ebef, 0xff5b6fab, 0x005f0a0d,
2327     0xffc4b414, 0xff68582c, 0x006b38e5,
2328     0xffabb861, 0xff704bec, 0x0074de52,
2329     0xffa19f4c, 0xff729059, 0x007c7e90,
2330     0x00000001//output gain
2331 };
2332
2333 static u32 coef_96to44[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2334     0x000f6103,//header
2335     0x000001e0,//input gain
2336     0x00de44c0, 0xff380b7f, 0x004ffc73,
2337     0x00494b44, 0xff3d493a, 0x005908bf,
2338     0xffe9a3c8, 0xff425647, 0x006745f7,
2339     0xffc42d61, 0xff40a6c7, 0x00776709,
2340     0x00000002,//output gain
2341     0x001a5204,//farrow
2342     0x000aaaab,
2343     0xffaaaaab,
2344     0xfffaaaab,
2345     0x00555555,
2346     0xff600000,
2347     0xfff55555,
2348     0x00155555,
2349     0x00055555,
2350     0xffeaaaab,
2351     0x00200000,
2352     0x00005102,//header
2353     0x0001d727,//input gain
2354     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
2355     0x00e55557, 0xffcadd5b, 0x003d80ba,
2356     0x00d13397, 0xfff232f8, 0x00683337,
2357     0x00000001//output gain
2358 };
2359
2360 static u32 coef_96to48[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2361     0x00005102,//header
2362     0x0001d727,//input gain
2363     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
2364     0x00e55557, 0xffcadd5b, 0x003d80ba,
2365     0x00d13397, 0xfff232f8, 0x00683337,
2366     0x00000001//output gain
2367 };
2368
2369 static u32 coef_96to88[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2370     0x000f6103,//header
2371     0x000001e0,//input gain
2372     0x00de44c0, 0xff380b7f, 0x004ffc73,
2373     0x00494b44, 0xff3d493a, 0x005908bf,
2374     0xffe9a3c8, 0xff425647, 0x006745f7,
2375     0xffc42d61, 0xff40a6c7, 0x00776709,
2376     0x00000002,//output gain
2377     0x001a0204,//farrow
2378     0x000aaaab,
2379     0xffaaaaab,
2380     0xfffaaaab,
2381     0x00555555,
2382     0xff600000,
2383     0xfff55555,
2384     0x00155555,
2385     0x00055555,
2386     0xffeaaaab,
2387     0x00200000,
2388     0x00005102,//header
2389     0x000013d9,//input gain
2390     0x00ebd477, 0xff4ce383, 0x0042049d,
2391     0x0089c278, 0xff54414d, 0x00531ded,
2392     0x004a5e07, 0xff53cf41, 0x006efbdc,
2393     0x00000001//output gain
2394 };
2395
2396 static u32 coef_96to176[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2397     0x000f6103,//header
2398     0x000001e0,//input gain
2399     0x00de44c0, 0xff380b7f, 0x004ffc73,
2400     0x00494b44, 0xff3d493a, 0x005908bf,
2401     0xffe9a3c8, 0xff425647, 0x006745f7,
2402     0xffc42d61, 0xff40a6c7, 0x00776709,
2403     0x00000002,//output gain
2404     0x001b6102,//header
2405     0x000000af,//input gain
2406     0x00c65663, 0xff23d2ce, 0x005f97d6,
2407     0x00086ad6, 0xff20ec4f, 0x00683201,
2408     0xffbbbef6, 0xff184447, 0x00770963,
2409     0x00000002,//output gain
2410     0x00260204,//farrow
2411     0x000aaaab,
2412     0xffaaaaab,
2413     0xfffaaaab,
2414     0x00555555,
2415     0xff600000,
2416     0xfff55555,
2417     0x00155555,
2418     0x00055555,
2419     0xffeaaaab,
2420     0x00200000,
2421     0x00005102,//header
2422     0x0000010a,//input gain
2423     0x00c93dc4, 0xff26f5f6, 0x005d1041,
2424     0x001002c4, 0xff245b76, 0x00666002,
2425     0xffc30a45, 0xff1baecd, 0x00765921,
2426     0x00000001//output gain
2427 };
2428
2429 static u32 coef_96to192[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2430     0x00006103,//header
2431     0x000001e0,//input gain
2432     0x00de44c0, 0xff380b7f, 0x004ffc73,
2433     0x00494b44, 0xff3d493a, 0x005908bf,
2434     0xffe9a3c8, 0xff425647, 0x006745f7,
2435     0xffc42d61, 0xff40a6c7, 0x00776709,
2436     0x00000002//output gain
2437 };
2438
2439 static u32 coef_176to16[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2440     0x000c0102,//header
2441     0x00000057,//input gain
2442     0x00a8e717, 0xff1c748d, 0x0065b976,
2443     0xffcbccab, 0xff190aff, 0x006cc1cf,
2444     0xff871ce1, 0xff10d878, 0x0078cfc5,
2445     0x00000001,//output gain
2446     0x00179204,//farrow
2447     0x000aaaab,
2448     0xffaaaaab,
2449     0xfffaaaab,
2450     0x00555555,
2451     0xff600000,
2452     0xfff55555,
2453     0x00155555,
2454     0x00055555,
2455     0xffeaaaab,
2456     0x00200000,
2457     0x00235102,//header
2458     0x000013d9,//input gain
2459     0x00ebd477, 0xff4ce383, 0x0042049d,
2460     0x0089c278, 0xff54414d, 0x00531ded,
2461     0x004a5e07, 0xff53cf41, 0x006efbdc,
2462     0x00000001,//output gain
2463     0x00005102,//header
2464     0x0001d727,//input gain
2465     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
2466     0x00e55557, 0xffcadd5b, 0x003d80ba,
2467     0x00d13397, 0xfff232f8, 0x00683337,
2468     0x00000001//output gain
2469 };
2470
2471 static u32 coef_176to22[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2472     0x000c5102,//header
2473     0x0000010a,//input gain
2474     0x00c93dc4, 0xff26f5f6, 0x005d1041,
2475     0x001002c4, 0xff245b76, 0x00666002,
2476     0xffc30a45, 0xff1baecd, 0x00765921,
2477     0x00000001,//output gain
2478     0x00185102,//header
2479     0x000013d9,//input gain
2480     0x00ebd477, 0xff4ce383, 0x0042049d,
2481     0x0089c278, 0xff54414d, 0x00531ded,
2482     0x004a5e07, 0xff53cf41, 0x006efbdc,
2483     0x00000001,//output gain
2484     0x00005102,//header
2485     0x0001d727,//input gain
2486     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
2487     0x00e55557, 0xffcadd5b, 0x003d80ba,
2488     0x00d13397, 0xfff232f8, 0x00683337,
2489     0x00000001//output gain
2490 };
2491
2492 static u32 coef_176to24[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2493     0x000c0102,//header
2494     0x00000138,//input gain
2495     0x00d5d232, 0xff2a3bf8, 0x005a785c,
2496     0x0034001b, 0xff283109, 0x006462a6,
2497     0xffe6746a, 0xff1fb09c, 0x00758a91,
2498     0x00000001,//output gain
2499     0x00175204,//farrow
2500     0x000aaaab,
2501     0xffaaaaab,
2502     0xfffaaaab,
2503     0x00555555,
2504     0xff600000,
2505     0xfff55555,
2506     0x00155555,
2507     0x00055555,
2508     0xffeaaaab,
2509     0x00200000,
2510     0x00235102,//header
2511     0x000013d9,//input gain
2512     0x00ebd477, 0xff4ce383, 0x0042049d,
2513     0x0089c278, 0xff54414d, 0x00531ded,
2514     0x004a5e07, 0xff53cf41, 0x006efbdc,
2515     0x00000001,//output gain
2516     0x00005102,//header
2517     0x0001d727,//input gain
2518     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
2519     0x00e55557, 0xffcadd5b, 0x003d80ba,
2520     0x00d13397, 0xfff232f8, 0x00683337,
2521     0x00000001//output gain
2522 };
2523
2524 static u32 coef_176to32[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2525     0x000c0102,//header
2526     0x000005f3,//input gain
2527     0x00d816d6, 0xff385383, 0x004fe566,
2528     0x003c548d, 0xff38c23d, 0x005d0b1c,
2529     0xfff02f7d, 0xff31e983, 0x0072d65d,
2530     0x00000001,//output gain
2531     0x00179204,//farrow
2532     0x000aaaab,
2533     0xffaaaaab,
2534     0xfffaaaab,
2535     0x00555555,
2536     0xff600000,
2537     0xfff55555,
2538     0x00155555,
2539     0x00055555,
2540     0xffeaaaab,
2541     0x00200000,
2542     0x00005102,//header
2543     0x0001d727,//input gain
2544     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
2545     0x00e55557, 0xffcadd5b, 0x003d80ba,
2546     0x00d13397, 0xfff232f8, 0x00683337,
2547     0x00000001//output gain
2548 };
2549
2550 static u32 coef_176to44[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2551     0x000c5102,//header
2552     0x000013d9,//input gain
2553     0x00ebd477, 0xff4ce383, 0x0042049d,
2554     0x0089c278, 0xff54414d, 0x00531ded,
2555     0x004a5e07, 0xff53cf41, 0x006efbdc,
2556     0x00000001,//output gain
2557     0x00005102,//header
2558     0x0001d727,//input gain
2559     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
2560     0x00e55557, 0xffcadd5b, 0x003d80ba,
2561     0x00d13397, 0xfff232f8, 0x00683337,
2562     0x00000001//output gain
2563 };
2564
2565 static u32 coef_176to48[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2566     0x000c0102,//header
2567     0x00001685,//input gain
2568     0x00f53ae9, 0xff52f196, 0x003e3e08,
2569     0x00b9f857, 0xff5d8985, 0x0050070a,
2570     0x008c3e86, 0xff6053f0, 0x006d98ef,
2571     0x00000001,//output gain
2572     0x00175204,//farrow
2573     0x000aaaab,
2574     0xffaaaaab,
2575     0xfffaaaab,
2576     0x00555555,
2577     0xff600000,
2578     0xfff55555,
2579     0x00155555,
2580     0x00055555,
2581     0xffeaaaab,
2582     0x00200000,
2583     0x00005102,//header
2584     0x0001d727,//input gain
2585     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
2586     0x00e55557, 0xffcadd5b, 0x003d80ba,
2587     0x00d13397, 0xfff232f8, 0x00683337,
2588     0x00000001//output gain
2589 };
2590
2591 static u32 coef_176to88[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2592     0x00005102,//header
2593     0x000013d9,//input gain
2594     0x00ebd477, 0xff4ce383, 0x0042049d,
2595     0x0089c278, 0xff54414d, 0x00531ded,
2596     0x004a5e07, 0xff53cf41, 0x006efbdc,
2597     0x00000001//output gain
2598 };
2599
2600 static u32 coef_176to96[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2601     0x000c6102,//header
2602     0x0000010a,//input gain
2603     0x00c93dc4, 0xff26f5f6, 0x005d1041,
2604     0x001002c4, 0xff245b76, 0x00666002,
2605     0xffc30a45, 0xff1baecd, 0x00765921,
2606     0x00000002,//output gain
2607     0x00175204,//farrow
2608     0x000aaaab,
2609     0xffaaaaab,
2610     0xfffaaaab,
2611     0x00555555,
2612     0xff600000,
2613     0xfff55555,
2614     0x00155555,
2615     0x00055555,
2616     0xffeaaaab,
2617     0x00200000,
2618     0x00005103,//header
2619     0x000001e0,//input gain
2620     0x00de44c0, 0xff380b7f, 0x004ffc73,
2621     0x00494b44, 0xff3d493a, 0x005908bf,
2622     0xffe9a3c8, 0xff425647, 0x006745f7,
2623     0xffc42d61, 0xff40a6c7, 0x00776709,
2624     0x00000001//output gain
2625 };
2626
2627 static u32 coef_176to192[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2628     0x000c6102,//header
2629     0x0000010a,//input gain
2630     0x00c93dc4, 0xff26f5f6, 0x005d1041,
2631     0x001002c4, 0xff245b76, 0x00666002,
2632     0xffc30a45, 0xff1baecd, 0x00765921,
2633     0x00000002,//output gain
2634     0x00005204,//farrow
2635     0x000aaaab,
2636     0xffaaaaab,
2637     0xfffaaaab,
2638     0x00555555,
2639     0xff600000,
2640     0xfff55555,
2641     0x00155555,
2642     0x00055555,
2643     0xffeaaaab,
2644     0x00200000
2645 };
2646
2647 static u32 coef_192to16[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2648     0x000c9102,//header
2649     0x0000007d,//input gain
2650     0x007d1f20, 0xff1a540e, 0x00678bf9,
2651     0xff916625, 0xff16b0ff, 0x006e433a,
2652     0xff5af660, 0xff0eb91f, 0x00797356,
2653     0x00000001,//output gain
2654     0x00185102,//header
2655     0x000013d9,//input gain
2656     0x00ebd477, 0xff4ce383, 0x0042049d,
2657     0x0089c278, 0xff54414d, 0x00531ded,
2658     0x004a5e07, 0xff53cf41, 0x006efbdc,
2659     0x00000001,//output gain
2660     0x00005102,//header
2661     0x0001d727,//input gain
2662     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
2663     0x00e55557, 0xffcadd5b, 0x003d80ba,
2664     0x00d13397, 0xfff232f8, 0x00683337,
2665     0x00000001//output gain
2666 };
2667
2668 static u32 coef_192to22[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2669     0x000c0102,//header
2670     0x000000af,//input gain
2671     0x00c65663, 0xff23d2ce, 0x005f97d6,
2672     0x00086ad6, 0xff20ec4f, 0x00683201,
2673     0xffbbbef6, 0xff184447, 0x00770963,
2674     0x00000001,//output gain
2675     0x00175204,//farrow
2676     0x000aaaab,
2677     0xffaaaaab,
2678     0xfffaaaab,
2679     0x00555555,
2680     0xff600000,
2681     0xfff55555,
2682     0x00155555,
2683     0x00055555,
2684     0xffeaaaab,
2685     0x00200000,
2686     0x00235102,//header
2687     0x000013d9,//input gain
2688     0x00ebd477, 0xff4ce383, 0x0042049d,
2689     0x0089c278, 0xff54414d, 0x00531ded,
2690     0x004a5e07, 0xff53cf41, 0x006efbdc,
2691     0x00000001,//output gain
2692     0x00005102,//header
2693     0x0001d727,//input gain
2694     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
2695     0x00e55557, 0xffcadd5b, 0x003d80ba,
2696     0x00d13397, 0xfff232f8, 0x00683337,
2697     0x00000001//output gain
2698 };
2699
2700 static u32 coef_192to24[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2701     0x000c5102,//header
2702     0x0000010a,//input gain
2703     0x00c93dc4, 0xff26f5f6, 0x005d1041,
2704     0x001002c4, 0xff245b76, 0x00666002,
2705     0xffc30a45, 0xff1baecd, 0x00765921,
2706     0x00000001,//output gain
2707     0x00185102,//header
2708     0x000013d9,//input gain
2709     0x00ebd477, 0xff4ce383, 0x0042049d,
2710     0x0089c278, 0xff54414d, 0x00531ded,
2711     0x004a5e07, 0xff53cf41, 0x006efbdc,
2712     0x00000001,//output gain
2713     0x00005102,//header
2714     0x0001d727,//input gain
2715     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
2716     0x00e55557, 0xffcadd5b, 0x003d80ba,
2717     0x00d13397, 0xfff232f8, 0x00683337,
2718     0x00000001//output gain
2719 };
2720
2721 static u32 coef_192to32[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2722     0x000c9102,//header
2723     0x000005d6,//input gain
2724     0x00c6543e, 0xff342935, 0x0052f116,
2725     0x000a1d78, 0xff3330c0, 0x005f88a3,
2726     0xffbee7c0, 0xff2b5ba5, 0x0073eb26,
2727     0x00000001,//output gain
2728     0x00005102,//header
2729     0x0001d727,//input gain
2730     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
2731     0x00e55557, 0xffcadd5b, 0x003d80ba,
2732     0x00d13397, 0xfff232f8, 0x00683337,
2733     0x00000001//output gain
2734 };
2735
2736 static u32 coef_192to44[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2737     0x000c6102,//header
2738     0x000000af,//input gain
2739     0x00c65663, 0xff23d2ce, 0x005f97d6,
2740     0x00086ad6, 0xff20ec4f, 0x00683201,
2741     0xffbbbef6, 0xff184447, 0x00770963,
2742     0x00000002,//output gain
2743     0x00175204,//farrow
2744     0x000aaaab,
2745     0xffaaaaab,
2746     0xfffaaaab,
2747     0x00555555,
2748     0xff600000,
2749     0xfff55555,
2750     0x00155555,
2751     0x00055555,
2752     0xffeaaaab,
2753     0x00200000,
2754     0x00235102,//header
2755     0x000013d9,//input gain
2756     0x00ebd477, 0xff4ce383, 0x0042049d,
2757     0x0089c278, 0xff54414d, 0x00531ded,
2758     0x004a5e07, 0xff53cf41, 0x006efbdc,
2759     0x00000001,//output gain
2760     0x00005102,//header
2761     0x0001d727,//input gain
2762     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
2763     0x00e55557, 0xffcadd5b, 0x003d80ba,
2764     0x00d13397, 0xfff232f8, 0x00683337,
2765     0x00000001//output gain
2766 };
2767
2768 static u32 coef_192to48[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2769     0x000c5102,//header
2770     0x000013d9,//input gain
2771     0x00ebd477, 0xff4ce383, 0x0042049d,
2772     0x0089c278, 0xff54414d, 0x00531ded,
2773     0x004a5e07, 0xff53cf41, 0x006efbdc,
2774     0x00000001,//output gain
2775     0x00005102,//header
2776     0x0001d727,//input gain
2777     0x00fc2fc7, 0xff9bb27b, 0x001c564c,
2778     0x00e55557, 0xffcadd5b, 0x003d80ba,
2779     0x00d13397, 0xfff232f8, 0x00683337,
2780     0x00000001//output gain
2781 };
2782
2783 static u32 coef_192to88[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2784     0x000c6102,//header
2785     0x000000af,//input gain
2786     0x00c65663, 0xff23d2ce, 0x005f97d6,
2787     0x00086ad6, 0xff20ec4f, 0x00683201,
2788     0xffbbbef6, 0xff184447, 0x00770963,
2789     0x00000002,//output gain
2790     0x00175204,//farrow
2791     0x000aaaab,
2792     0xffaaaaab,
2793     0xfffaaaab,
2794     0x00555555,
2795     0xff600000,
2796     0xfff55555,
2797     0x00155555,
2798     0x00055555,
2799     0xffeaaaab,
2800     0x00200000,
2801     0x00005102,//header
2802     0x000013d9,//input gain
2803     0x00ebd477, 0xff4ce383, 0x0042049d,
2804     0x0089c278, 0xff54414d, 0x00531ded,
2805     0x004a5e07, 0xff53cf41, 0x006efbdc,
2806     0x00000001//output gain
2807 };
2808
2809 static u32 coef_192to96[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2810     0x00005103,//header
2811     0x000001e0,//input gain
2812     0x00de44c0, 0xff380b7f, 0x004ffc73,
2813     0x00494b44, 0xff3d493a, 0x005908bf,
2814     0xffe9a3c8, 0xff425647, 0x006745f7,
2815     0xffc42d61, 0xff40a6c7, 0x00776709,
2816     0x00000001//output gain
2817 };
2818
2819 static u32 coef_192to176[TEGRA210_SFC_COEF_RAM_DEPTH] = {
2820     0x000c6102,//header
2821     0x000000af,//input gain
2822     0x00c65663, 0xff23d2ce, 0x005f97d6,
2823     0x00086ad6, 0xff20ec4f, 0x00683201,
2824     0xffbbbef6, 0xff184447, 0x00770963,
2825     0x00000002,//output gain
2826     0x00170204,//farrow
2827     0x000aaaab,
2828     0xffaaaaab,
2829     0xfffaaaab,
2830     0x00555555,
2831     0xff600000,
2832     0xfff55555,
2833     0x00155555,
2834     0x00055555,
2835     0xffeaaaab,
2836     0x00200000,
2837     0x00005102,//header
2838     0x0000010a,//input gain
2839     0x00c93dc4, 0xff26f5f6, 0x005d1041,
2840     0x001002c4, 0xff245b76, 0x00666002,
2841     0xffc30a45, 0xff1baecd, 0x00765921,
2842     0x00000001//output gain
2843 };
2844
2845 /*
2846  * Coefficient table for various sample rate conversions. The sample
2847  * rates available are as per tegra210_sfc_rates[].
2848  */
2849 static s32 *coef_addr_table[TEGRA210_SFC_NUM_RATES][TEGRA210_SFC_NUM_RATES] = {
2850     /* Convertions from 8 kHz */
2851     {
2852         BYPASS_CONV,
2853         coef_8to11,
2854         coef_8to16,
2855         coef_8to22,
2856         coef_8to24,
2857         coef_8to32,
2858         coef_8to44,
2859         coef_8to48,
2860         coef_8to88,
2861         coef_8to96,
2862         UNSUPP_CONV,
2863         UNSUPP_CONV,
2864     },
2865     /* Convertions from 11.025 kHz */
2866     {
2867         coef_11to8,
2868         BYPASS_CONV,
2869         coef_11to16,
2870         coef_11to22,
2871         coef_11to24,
2872         coef_11to32,
2873         coef_11to44,
2874         coef_11to48,
2875         coef_11to88,
2876         coef_11to96,
2877         UNSUPP_CONV,
2878         UNSUPP_CONV,
2879     },
2880     /* Convertions from 16 kHz */
2881     {
2882         coef_16to8,
2883         coef_16to11,
2884         BYPASS_CONV,
2885         coef_16to22,
2886         coef_16to24,
2887         coef_16to32,
2888         coef_16to44,
2889         coef_16to48,
2890         coef_16to88,
2891         coef_16to96,
2892         coef_16to176,
2893         coef_16to192,
2894     },
2895     /* Convertions from 22.05 kHz */
2896     {
2897         coef_22to8,
2898         coef_22to11,
2899         coef_22to16,
2900         BYPASS_CONV,
2901         coef_22to24,
2902         coef_22to32,
2903         coef_22to44,
2904         coef_22to48,
2905         coef_22to88,
2906         coef_22to96,
2907         coef_22to176,
2908         coef_22to192,
2909     },
2910     /* Convertions from 24 kHz */
2911     {
2912         coef_24to8,
2913         coef_24to11,
2914         coef_24to16,
2915         coef_24to22,
2916         BYPASS_CONV,
2917         coef_24to32,
2918         coef_24to44,
2919         coef_24to48,
2920         coef_24to88,
2921         coef_24to96,
2922         coef_24to176,
2923         coef_24to192,
2924     },
2925     /* Convertions from 32 kHz */
2926     {
2927         coef_32to8,
2928         coef_32to11,
2929         coef_32to16,
2930         coef_32to22,
2931         coef_32to24,
2932         BYPASS_CONV,
2933         coef_32to44,
2934         coef_32to48,
2935         coef_32to88,
2936         coef_32to96,
2937         coef_32to176,
2938         coef_32to192,
2939     },
2940     /* Convertions from 44.1 kHz */
2941     {
2942         coef_44to8,
2943         coef_44to11,
2944         coef_44to16,
2945         coef_44to22,
2946         coef_44to24,
2947         coef_44to32,
2948         BYPASS_CONV,
2949         coef_44to48,
2950         coef_44to88,
2951         coef_44to96,
2952         coef_44to176,
2953         coef_44to192,
2954     },
2955     /* Convertions from 48 kHz */
2956     {
2957         coef_48to8,
2958         coef_48to11,
2959         coef_48to16,
2960         coef_48to22,
2961         coef_48to24,
2962         coef_48to32,
2963         coef_48to44,
2964         BYPASS_CONV,
2965         coef_48to88,
2966         coef_48to96,
2967         coef_48to176,
2968         coef_48to192,
2969     },
2970     /* Convertions from 88.2 kHz */
2971     {
2972         coef_88to8,
2973         coef_88to11,
2974         coef_88to16,
2975         coef_88to22,
2976         coef_88to24,
2977         coef_88to32,
2978         coef_88to44,
2979         coef_88to48,
2980         BYPASS_CONV,
2981         coef_88to96,
2982         coef_88to176,
2983         coef_88to192,
2984     },
2985     /* Convertions from 96 kHz */
2986     {   coef_96to8,
2987         coef_96to11,
2988         coef_96to16,
2989         coef_96to22,
2990         coef_96to24,
2991         coef_96to32,
2992         coef_96to44,
2993         coef_96to48,
2994         coef_96to88,
2995         BYPASS_CONV,
2996         coef_96to176,
2997         coef_96to192,
2998     },
2999     /* Convertions from 176.4 kHz */
3000     {
3001         UNSUPP_CONV,
3002         UNSUPP_CONV,
3003         coef_176to16,
3004         coef_176to22,
3005         coef_176to24,
3006         coef_176to32,
3007         coef_176to44,
3008         coef_176to48,
3009         coef_176to88,
3010         coef_176to96,
3011         BYPASS_CONV,
3012         coef_176to192,
3013     },
3014     /* Convertions from 192 kHz */
3015     {
3016         UNSUPP_CONV,
3017         UNSUPP_CONV,
3018         coef_192to16,
3019         coef_192to22,
3020         coef_192to24,
3021         coef_192to32,
3022         coef_192to44,
3023         coef_192to48,
3024         coef_192to88,
3025         coef_192to96,
3026         coef_192to176,
3027         BYPASS_CONV,
3028     },
3029 };
3030
3031 static int __maybe_unused tegra210_sfc_runtime_suspend(struct device *dev)
3032 {
3033     struct tegra210_sfc *sfc = dev_get_drvdata(dev);
3034
3035     regcache_cache_only(sfc->regmap, true);
3036     regcache_mark_dirty(sfc->regmap);
3037
3038     return 0;
3039 }
3040
3041 static int __maybe_unused tegra210_sfc_runtime_resume(struct device *dev)
3042 {
3043     struct tegra210_sfc *sfc = dev_get_drvdata(dev);
3044
3045     regcache_cache_only(sfc->regmap, false);
3046     regcache_sync(sfc->regmap);
3047
3048     return 0;
3049 }
3050
3051 static inline void tegra210_sfc_write_ram(struct regmap *regmap,
3052                       s32 *data)
3053 {
3054     int i;
3055
3056     regmap_write(regmap, TEGRA210_SFC_CFG_RAM_CTRL,
3057              TEGRA210_SFC_RAM_CTRL_SEQ_ACCESS_EN |
3058              TEGRA210_SFC_RAM_CTRL_ADDR_INIT_EN |
3059              TEGRA210_SFC_RAM_CTRL_RW_WRITE);
3060
3061     for (i = 0; i < TEGRA210_SFC_COEF_RAM_DEPTH; i++)
3062         regmap_write(regmap, TEGRA210_SFC_CFG_RAM_DATA, data[i]);
3063 }
3064
3065 static int tegra210_sfc_write_coeff_ram(struct snd_soc_component *cmpnt)
3066 {
3067     struct tegra210_sfc *sfc = dev_get_drvdata(cmpnt->dev);
3068     s32 *coeff_ram;
3069
3070     /* Bypass */
3071     if (sfc->srate_in == sfc->srate_out)
3072         return 0;
3073
3074     coeff_ram = coef_addr_table[sfc->srate_in][sfc->srate_out];
3075     if (IS_ERR_OR_NULL(coeff_ram)) {
3076         dev_err(cmpnt->dev,
3077             "Conversion from %d to %d Hz is not supported\n",
3078             sfc->srate_in, sfc->srate_out);
3079
3080         return PTR_ERR_OR_ZERO(coeff_ram);
3081     }
3082
3083     tegra210_sfc_write_ram(sfc->regmap, coeff_ram);
3084
3085     regmap_update_bits(sfc->regmap,
3086                TEGRA210_SFC_COEF_RAM,
3087                TEGRA210_SFC_COEF_RAM_EN,
3088                TEGRA210_SFC_COEF_RAM_EN);
3089
3090     return 0;
3091 }
3092
3093 static int tegra210_sfc_set_audio_cif(struct tegra210_sfc *sfc,
3094                       struct snd_pcm_hw_params *params,
3095                       unsigned int reg)
3096 {
3097     unsigned int channels, audio_bits, path;
3098     struct tegra_cif_conf cif_conf;
3099
3100     memset(&cif_conf, 0, sizeof(struct tegra_cif_conf));
3101
3102     channels = params_channels(params);
3103
3104     switch (params_format(params)) {
3105     case SNDRV_PCM_FORMAT_S16_LE:
3106         audio_bits = TEGRA_ACIF_BITS_16;
3107         break;
3108     case SNDRV_PCM_FORMAT_S32_LE:
3109         audio_bits = TEGRA_ACIF_BITS_32;
3110         break;
3111     default:
3112         return -EOPNOTSUPP;
3113     }
3114
3115     cif_conf.audio_ch = channels;
3116     cif_conf.client_ch = channels;
3117     cif_conf.audio_bits = audio_bits;
3118     cif_conf.client_bits = TEGRA_ACIF_BITS_32;
3119
3120     if (reg == TEGRA210_SFC_RX_CIF_CTRL)
3121         path = SFC_RX_PATH;
3122     else
3123         path = SFC_TX_PATH;
3124
3125     cif_conf.stereo_conv = sfc->stereo_to_mono[path];
3126     cif_conf.mono_conv = sfc->mono_to_stereo[path];
3127
3128     tegra_set_cif(sfc->regmap, reg, &cif_conf);
3129
3130     return 0;
3131 }
3132
3133 static int tegra210_sfc_soft_reset(struct tegra210_sfc *sfc)
3134 {
3135     u32 val;
3136
3137     /*
3138      * Soft Reset: Below performs module soft reset which clears
3139      * all FSM logic, flushes flow control of FIFO and resets the
3140      * state register. It also brings module back to disabled
3141      * state (without flushing the data in the pipe).
3142      */
3143     regmap_update_bits(sfc->regmap, TEGRA210_SFC_SOFT_RESET,
3144                TEGRA210_SFC_SOFT_RESET_EN, 1);
3145
3146     return regmap_read_poll_timeout(sfc->regmap,
3147                     TEGRA210_SFC_SOFT_RESET,
3148                     val,
3149                     !(val & TEGRA210_SFC_SOFT_RESET_EN),
3150                     10, 10000);
3151 }
3152
3153 static int tegra210_sfc_rate_to_idx(struct device *dev, int rate,
3154                     int *rate_idx)
3155 {
3156     int i;
3157
3158     for (i = 0; i < ARRAY_SIZE(tegra210_sfc_rates); i++) {
3159         if (rate == tegra210_sfc_rates[i]) {
3160             *rate_idx = i;
3161
3162             return 0;
3163         }
3164     }
3165
3166     dev_err(dev, "Sample rate %d Hz is not supported\n", rate);
3167
3168     return -EOPNOTSUPP;
3169 }
3170
3171 static int tegra210_sfc_startup(struct snd_pcm_substream *substream,
3172                 struct snd_soc_dai *dai)
3173 {
3174     struct tegra210_sfc *sfc = snd_soc_dai_get_drvdata(dai);
3175     int err;
3176
3177     regmap_update_bits(sfc->regmap, TEGRA210_SFC_COEF_RAM,
3178                TEGRA210_SFC_COEF_RAM_EN, 0);
3179
3180     err = tegra210_sfc_soft_reset(sfc);
3181     if (err < 0) {
3182         dev_err(dai->dev, "Failed to reset SFC in %s, err = %d\n",
3183             __func__, err);
3184
3185         return err;
3186     }
3187
3188     return 0;
3189 }
3190
3191 static int tegra210_sfc_in_hw_params(struct snd_pcm_substream *substream,
3192                      struct snd_pcm_hw_params *params,
3193                      struct snd_soc_dai *dai)
3194 {
3195     struct tegra210_sfc *sfc = snd_soc_dai_get_drvdata(dai);
3196     struct device *dev = dai->dev;
3197     int err;
3198
3199     err = tegra210_sfc_rate_to_idx(dev, params_rate(params),
3200                        &sfc->srate_in);
3201     if (err < 0)
3202         return err;
3203
3204     err = tegra210_sfc_set_audio_cif(sfc, params, TEGRA210_SFC_RX_CIF_CTRL);
3205     if (err < 0) {
3206         dev_err(dev, "Can't set SFC RX CIF: %d\n", err);
3207         return err;
3208     }
3209
3210     regmap_write(sfc->regmap, TEGRA210_SFC_RX_FREQ, sfc->srate_in);
3211
3212     return err;
3213 }
3214
3215 static int tegra210_sfc_out_hw_params(struct snd_pcm_substream *substream,
3216                       struct snd_pcm_hw_params *params,
3217                       struct snd_soc_dai *dai)
3218 {
3219     struct tegra210_sfc *sfc = snd_soc_dai_get_drvdata(dai);
3220     struct device *dev = dai->dev;
3221     int err;
3222
3223     err = tegra210_sfc_rate_to_idx(dev, params_rate(params),
3224                        &sfc->srate_out);
3225     if (err < 0)
3226         return err;
3227
3228     err = tegra210_sfc_set_audio_cif(sfc, params, TEGRA210_SFC_TX_CIF_CTRL);
3229     if (err < 0) {
3230         dev_err(dev, "Can't set SFC TX CIF: %d\n", err);
3231         return err;
3232     }
3233
3234     regmap_write(sfc->regmap, TEGRA210_SFC_TX_FREQ, sfc->srate_out);
3235
3236     return 0;
3237 }
3238
3239 static int tegra210_sfc_init(struct snd_soc_dapm_widget *w,
3240                  struct snd_kcontrol *kcontrol, int event)
3241 {
3242     struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
3243
3244     return tegra210_sfc_write_coeff_ram(cmpnt);
3245 }
3246
3247 static int tegra210_sfc_iget_stereo_to_mono(struct snd_kcontrol *kcontrol,
3248                     struct snd_ctl_elem_value *ucontrol)
3249 {
3250     struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
3251     struct tegra210_sfc *sfc = snd_soc_component_get_drvdata(cmpnt);
3252
3253     ucontrol->value.enumerated.item[0] = sfc->stereo_to_mono[SFC_RX_PATH];
3254
3255     return 0;
3256 }
3257
3258 static int tegra210_sfc_iput_stereo_to_mono(struct snd_kcontrol *kcontrol,
3259                     struct snd_ctl_elem_value *ucontrol)
3260 {
3261     struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
3262     struct tegra210_sfc *sfc = snd_soc_component_get_drvdata(cmpnt);
3263     unsigned int value = ucontrol->value.enumerated.item[0];
3264
3265     if (value == sfc->stereo_to_mono[SFC_RX_PATH])
3266         return 0;
3267
3268     sfc->stereo_to_mono[SFC_RX_PATH] = value;
3269
3270     return 1;
3271 }
3272
3273 static int tegra210_sfc_iget_mono_to_stereo(struct snd_kcontrol *kcontrol,
3274                     struct snd_ctl_elem_value *ucontrol)
3275 {
3276     struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
3277     struct tegra210_sfc *sfc = snd_soc_component_get_drvdata(cmpnt);
3278
3279     ucontrol->value.enumerated.item[0] = sfc->mono_to_stereo[SFC_RX_PATH];
3280
3281     return 0;
3282 }
3283
3284 static int tegra210_sfc_iput_mono_to_stereo(struct snd_kcontrol *kcontrol,
3285                     struct snd_ctl_elem_value *ucontrol)
3286 {
3287     struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
3288     struct tegra210_sfc *sfc = snd_soc_component_get_drvdata(cmpnt);
3289     unsigned int value = ucontrol->value.enumerated.item[0];
3290
3291     if (value == sfc->mono_to_stereo[SFC_RX_PATH])
3292         return 0;
3293
3294     sfc->mono_to_stereo[SFC_RX_PATH] = value;
3295
3296     return 1;
3297 }
3298
3299 static int tegra210_sfc_oget_stereo_to_mono(struct snd_kcontrol *kcontrol,
3300                     struct snd_ctl_elem_value *ucontrol)
3301 {
3302     struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
3303     struct tegra210_sfc *sfc = snd_soc_component_get_drvdata(cmpnt);
3304
3305     ucontrol->value.enumerated.item[0] = sfc->stereo_to_mono[SFC_TX_PATH];
3306
3307     return 0;
3308 }
3309
3310 static int tegra210_sfc_oput_stereo_to_mono(struct snd_kcontrol *kcontrol,
3311                     struct snd_ctl_elem_value *ucontrol)
3312 {
3313     struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
3314     struct tegra210_sfc *sfc = snd_soc_component_get_drvdata(cmpnt);
3315     unsigned int value = ucontrol->value.enumerated.item[0];
3316
3317     if (value == sfc->stereo_to_mono[SFC_TX_PATH])
3318         return 0;
3319
3320     sfc->stereo_to_mono[SFC_TX_PATH] = value;
3321
3322     return 1;
3323 }
3324
3325 static int tegra210_sfc_oget_mono_to_stereo(struct snd_kcontrol *kcontrol,
3326                     struct snd_ctl_elem_value *ucontrol)
3327 {
3328     struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
3329     struct tegra210_sfc *sfc = snd_soc_component_get_drvdata(cmpnt);
3330
3331     ucontrol->value.enumerated.item[0] = sfc->mono_to_stereo[SFC_TX_PATH];
3332
3333     return 0;
3334 }
3335
3336 static int tegra210_sfc_oput_mono_to_stereo(struct snd_kcontrol *kcontrol,
3337                     struct snd_ctl_elem_value *ucontrol)
3338 {
3339     struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
3340     struct tegra210_sfc *sfc = snd_soc_component_get_drvdata(cmpnt);
3341     unsigned int value = ucontrol->value.enumerated.item[0];
3342
3343     if (value == sfc->mono_to_stereo[SFC_TX_PATH])
3344         return 0;
3345
3346     sfc->mono_to_stereo[SFC_TX_PATH] = value;
3347
3348     return 1;
3349 }
3350
3351 static const struct snd_soc_dai_ops tegra210_sfc_in_dai_ops = {
3352     .hw_params  = tegra210_sfc_in_hw_params,
3353     .startup    = tegra210_sfc_startup,
3354 };
3355
3356 static const struct snd_soc_dai_ops tegra210_sfc_out_dai_ops = {
3357     .hw_params  = tegra210_sfc_out_hw_params,
3358 };
3359
3360 static struct snd_soc_dai_driver tegra210_sfc_dais[] = {
3361     {
3362         .name = "SFC-RX-CIF",
3363         .playback = {
3364             .stream_name = "RX-CIF-Playback",
3365             .channels_min = 1,
3366             .channels_max = 2,
3367             .rates = SNDRV_PCM_RATE_8000_192000,
3368             .formats = SNDRV_PCM_FMTBIT_S8 |
3369                 SNDRV_PCM_FMTBIT_S16_LE |
3370                 SNDRV_PCM_FMTBIT_S32_LE,
3371         },
3372         .capture = {
3373             .stream_name = "RX-CIF-Capture",
3374             .channels_min = 1,
3375             .channels_max = 2,
3376             .rates = SNDRV_PCM_RATE_8000_192000,
3377             .formats = SNDRV_PCM_FMTBIT_S8 |
3378                 SNDRV_PCM_FMTBIT_S16_LE |
3379                 SNDRV_PCM_FMTBIT_S32_LE,
3380         },
3381         .ops = &tegra210_sfc_in_dai_ops,
3382     },
3383     {
3384         .name = "SFC-TX-CIF",
3385         .playback = {
3386             .stream_name = "TX-CIF-Playback",
3387             .channels_min = 1,
3388             .channels_max = 2,
3389             .rates = SNDRV_PCM_RATE_8000_192000,
3390             .formats = SNDRV_PCM_FMTBIT_S8 |
3391                 SNDRV_PCM_FMTBIT_S16_LE |
3392                 SNDRV_PCM_FMTBIT_S32_LE,
3393         },
3394         .capture = {
3395             .stream_name = "TX-CIF-Capture",
3396             .channels_min = 1,
3397             .channels_max = 2,
3398             .rates = SNDRV_PCM_RATE_8000_192000,
3399             .formats = SNDRV_PCM_FMTBIT_S8 |
3400                 SNDRV_PCM_FMTBIT_S16_LE |
3401                 SNDRV_PCM_FMTBIT_S32_LE,
3402         },
3403         .ops = &tegra210_sfc_out_dai_ops,
3404     },
3405 };
3406
3407 static const struct snd_soc_dapm_widget tegra210_sfc_widgets[] = {
3408     SND_SOC_DAPM_AIF_IN("RX", NULL, 0, SND_SOC_NOPM, 0, 0),
3409     SND_SOC_DAPM_AIF_OUT_E("TX", NULL, 0, TEGRA210_SFC_ENABLE,
3410                    TEGRA210_SFC_EN_SHIFT, 0,
3411                    tegra210_sfc_init, SND_SOC_DAPM_PRE_PMU),
3412 };
3413
3414 #define RESAMPLE_ROUTE(sname)                   \
3415     { "RX XBAR-" sname, NULL,   "XBAR-TX" },        \
3416     { "RX-CIF-" sname,  NULL,   "RX XBAR-" sname }, \
3417     { "RX",         NULL,   "RX-CIF-" sname },  \
3418     { "TX-CIF-" sname,  NULL,   "TX" },         \
3419     { "TX XBAR-" sname, NULL,   "TX-CIF-" sname },  \
3420     { "XBAR-RX",        NULL,   "TX XBAR-" sname }
3421
3422 static const struct snd_soc_dapm_route tegra210_sfc_routes[] = {
3423     { "TX", NULL, "RX" },
3424     RESAMPLE_ROUTE("Playback"),
3425     RESAMPLE_ROUTE("Capture"),
3426 };
3427
3428 static const char * const tegra210_sfc_stereo_conv_text[] = {
3429     "CH0", "CH1", "AVG",
3430 };
3431
3432 static const char * const tegra210_sfc_mono_conv_text[] = {
3433     "Zero", "Copy",
3434 };
3435
3436 static const struct soc_enum tegra210_sfc_stereo_conv_enum =
3437     SOC_ENUM_SINGLE(SND_SOC_NOPM, 0,
3438             ARRAY_SIZE(tegra210_sfc_stereo_conv_text),
3439             tegra210_sfc_stereo_conv_text);
3440
3441 static const struct soc_enum tegra210_sfc_mono_conv_enum =
3442     SOC_ENUM_SINGLE(SND_SOC_NOPM, 0,
3443             ARRAY_SIZE(tegra210_sfc_mono_conv_text),
3444             tegra210_sfc_mono_conv_text);
3445
3446 static const struct snd_kcontrol_new tegra210_sfc_controls[] = {
3447     SOC_ENUM_EXT("Input Stereo To Mono", tegra210_sfc_stereo_conv_enum,
3448              tegra210_sfc_iget_stereo_to_mono,
3449              tegra210_sfc_iput_stereo_to_mono),
3450     SOC_ENUM_EXT("Input Mono To Stereo", tegra210_sfc_mono_conv_enum,
3451              tegra210_sfc_iget_mono_to_stereo,
3452              tegra210_sfc_iput_mono_to_stereo),
3453     SOC_ENUM_EXT("Output Stereo To Mono", tegra210_sfc_stereo_conv_enum,
3454              tegra210_sfc_oget_stereo_to_mono,
3455              tegra210_sfc_oput_stereo_to_mono),
3456     SOC_ENUM_EXT("Output Mono To Stereo", tegra210_sfc_mono_conv_enum,
3457              tegra210_sfc_oget_mono_to_stereo,
3458              tegra210_sfc_oput_mono_to_stereo),
3459 };
3460
3461 static const struct snd_soc_component_driver tegra210_sfc_cmpnt = {
3462     .dapm_widgets       = tegra210_sfc_widgets,
3463     .num_dapm_widgets   = ARRAY_SIZE(tegra210_sfc_widgets),
3464     .dapm_routes        = tegra210_sfc_routes,
3465     .num_dapm_routes    = ARRAY_SIZE(tegra210_sfc_routes),
3466     .controls       = tegra210_sfc_controls,
3467     .num_controls       = ARRAY_SIZE(tegra210_sfc_controls),
3468 };
3469
3470 static bool tegra210_sfc_wr_reg(struct device *dev, unsigned int reg)
3471 {
3472     switch (reg) {
3473     case TEGRA210_SFC_RX_INT_MASK ... TEGRA210_SFC_RX_FREQ:
3474     case TEGRA210_SFC_TX_INT_MASK ... TEGRA210_SFC_TX_FREQ:
3475     case TEGRA210_SFC_ENABLE ... TEGRA210_SFC_CG:
3476     case TEGRA210_SFC_COEF_RAM ... TEGRA210_SFC_CFG_RAM_DATA:
3477         return true;
3478     default:
3479         return false;
3480     }
3481 }
3482
3483 static bool tegra210_sfc_rd_reg(struct device *dev, unsigned int reg)
3484 {
3485     switch (reg) {
3486     case TEGRA210_SFC_RX_STATUS ... TEGRA210_SFC_RX_FREQ:
3487     case TEGRA210_SFC_TX_STATUS ... TEGRA210_SFC_TX_FREQ:
3488     case TEGRA210_SFC_ENABLE ... TEGRA210_SFC_INT_STATUS:
3489     case TEGRA210_SFC_COEF_RAM ... TEGRA210_SFC_CFG_RAM_DATA:
3490         return true;
3491     default:
3492         return false;
3493     }
3494 }
3495
3496 static bool tegra210_sfc_volatile_reg(struct device *dev, unsigned int reg)
3497 {
3498     switch (reg) {
3499     case TEGRA210_SFC_RX_STATUS:
3500     case TEGRA210_SFC_RX_INT_STATUS:
3501     case TEGRA210_SFC_RX_INT_SET:
3502
3503     case TEGRA210_SFC_TX_STATUS:
3504     case TEGRA210_SFC_TX_INT_STATUS:
3505     case TEGRA210_SFC_TX_INT_SET:
3506
3507     case TEGRA210_SFC_SOFT_RESET:
3508     case TEGRA210_SFC_STATUS:
3509     case TEGRA210_SFC_INT_STATUS:
3510     case TEGRA210_SFC_CFG_RAM_CTRL:
3511     case TEGRA210_SFC_CFG_RAM_DATA:
3512         return true;
3513     default:
3514         return false;
3515     }
3516 }
3517
3518 static bool tegra210_sfc_precious_reg(struct device *dev, unsigned int reg)
3519 {
3520     switch (reg) {
3521     case TEGRA210_SFC_CFG_RAM_DATA:
3522         return true;
3523     default:
3524         return false;
3525     }
3526 }
3527
3528 static const struct regmap_config tegra210_sfc_regmap_config = {
3529     .reg_bits       = 32,
3530     .reg_stride     = 4,
3531     .val_bits       = 32,
3532     .max_register       = TEGRA210_SFC_CFG_RAM_DATA,
3533     .writeable_reg      = tegra210_sfc_wr_reg,
3534     .readable_reg       = tegra210_sfc_rd_reg,
3535     .volatile_reg       = tegra210_sfc_volatile_reg,
3536     .precious_reg       = tegra210_sfc_precious_reg,
3537     .reg_defaults       = tegra210_sfc_reg_defaults,
3538     .num_reg_defaults   = ARRAY_SIZE(tegra210_sfc_reg_defaults),
3539     .cache_type     = REGCACHE_FLAT,
3540 };
3541
3542 static const struct of_device_id tegra210_sfc_of_match[] = {
3543     { .compatible = "nvidia,tegra210-sfc" },
3544     {},
3545 };
3546 MODULE_DEVICE_TABLE(of, tegra210_sfc_of_match);
3547
3548 static int tegra210_sfc_platform_probe(struct platform_device *pdev)
3549 {
3550     struct device *dev = &pdev->dev;
3551     struct tegra210_sfc *sfc;
3552     void __iomem *regs;
3553     int err;
3554
3555     sfc = devm_kzalloc(dev, sizeof(*sfc), GFP_KERNEL);
3556     if (!sfc)
3557         return -ENOMEM;
3558
3559     dev_set_drvdata(dev, sfc);
3560
3561     regs = devm_platform_ioremap_resource(pdev, 0);
3562     if (IS_ERR(regs))
3563         return PTR_ERR(regs);
3564
3565     sfc->regmap = devm_regmap_init_mmio(dev, regs,
3566                         &tegra210_sfc_regmap_config);
3567     if (IS_ERR(sfc->regmap)) {
3568         dev_err(dev, "regmap init failed\n");
3569         return PTR_ERR(sfc->regmap);
3570     }
3571
3572     regcache_cache_only(sfc->regmap, true);
3573
3574     err = devm_snd_soc_register_component(dev, &tegra210_sfc_cmpnt,
3575                           tegra210_sfc_dais,
3576                           ARRAY_SIZE(tegra210_sfc_dais));
3577     if (err) {
3578         dev_err(dev, "can't register SFC component, err: %d\n", err);
3579         return err;
3580     }
3581
3582     pm_runtime_enable(&pdev->dev);
3583
3584     return 0;
3585 }
3586
3587 static int tegra210_sfc_platform_remove(struct platform_device *pdev)
3588 {
3589     pm_runtime_disable(&pdev->dev);
3590
3591     return 0;
3592 }
3593
3594 static const struct dev_pm_ops tegra210_sfc_pm_ops = {
3595     SET_RUNTIME_PM_OPS(tegra210_sfc_runtime_suspend,
3596                tegra210_sfc_runtime_resume, NULL)
3597     SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
3598                 pm_runtime_force_resume)
3599 };
3600
3601 static struct platform_driver tegra210_sfc_driver = {
3602     .driver = {
3603         .name = "tegra210-sfc",
3604         .of_match_table = tegra210_sfc_of_match,
3605         .pm = &tegra210_sfc_pm_ops,
3606     },
3607     .probe = tegra210_sfc_platform_probe,
3608     .remove = tegra210_sfc_platform_remove,
3609 };
3610 module_platform_driver(tegra210_sfc_driver)
3611
3612 MODULE_AUTHOR("Arun Shamanna Lakshmi <aruns@nvidia.com>");
3613 MODULE_DESCRIPTION("Tegra210 SFC ASoC driver");
3614 MODULE_LICENSE("GPL v2");