soc/tegra/tegra210_peq.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * tegra210_peq.h - Definitions for Tegra210 PEQ driver
0004  *
0005  * Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
0006  *
0007  */
0008
0009 #ifndef __TEGRA210_PEQ_H__
0010 #define __TEGRA210_PEQ_H__
0011
0012 #include <linux/platform_device.h>
0013 #include <linux/regmap.h>
0014 #include <sound/soc.h>
0015
0016 /* Register offsets from PEQ base */
0017 #define TEGRA210_PEQ_SOFT_RESET             0x0
0018 #define TEGRA210_PEQ_CG                 0x4
0019 #define TEGRA210_PEQ_STATUS             0x8
0020 #define TEGRA210_PEQ_CFG                0xc
0021 #define TEGRA210_PEQ_CFG_RAM_CTRL           0x10
0022 #define TEGRA210_PEQ_CFG_RAM_DATA           0x14
0023 #define TEGRA210_PEQ_CFG_RAM_SHIFT_CTRL         0x18
0024 #define TEGRA210_PEQ_CFG_RAM_SHIFT_DATA         0x1c
0025
0026 /* Fields in TEGRA210_PEQ_CFG */
0027 #define TEGRA210_PEQ_CFG_BIQUAD_STAGES_SHIFT        2
0028 #define TEGRA210_PEQ_CFG_BIQUAD_STAGES_MASK     (0xf << TEGRA210_PEQ_CFG_BIQUAD_STAGES_SHIFT)
0029
0030 #define TEGRA210_PEQ_CFG_MODE_SHIFT         0
0031 #define TEGRA210_PEQ_CFG_MODE_MASK          (0x1 << TEGRA210_PEQ_CFG_MODE_SHIFT)
0032
0033 #define TEGRA210_PEQ_RAM_CTRL_RW_READ           0
0034 #define TEGRA210_PEQ_RAM_CTRL_RW_WRITE          (1 << 14)
0035 #define TEGRA210_PEQ_RAM_CTRL_ADDR_INIT_EN      (1 << 13)
0036 #define TEGRA210_PEQ_RAM_CTRL_SEQ_ACCESS_EN     (1 << 12)
0037 #define TEGRA210_PEQ_RAM_CTRL_RAM_ADDR_MASK     0x1ff
0038
0039 /* PEQ register definition ends here */
0040 #define TEGRA210_PEQ_MAX_BIQUAD_STAGES          12
0041
0042 #define TEGRA210_PEQ_MAX_CHANNELS           8
0043
0044 #define TEGRA210_PEQ_BIQUAD_INIT_STAGE          5
0045
0046 #define TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH (2 + TEGRA210_PEQ_MAX_BIQUAD_STAGES * 5)
0047 #define TEGRA210_PEQ_SHIFT_PARAM_SIZE_PER_CH (2 + TEGRA210_PEQ_MAX_BIQUAD_STAGES)
0048
0049 int tegra210_peq_regmap_init(struct platform_device *pdev);
0050 int tegra210_peq_component_init(struct snd_soc_component *cmpnt);
0051 void tegra210_peq_restore(struct regmap *regmap, u32 *biquad_gains,
0052               u32 *biquad_shifts);
0053 void tegra210_peq_save(struct regmap *regmap, u32 *biquad_gains,
0054                u32 *biquad_shifts);
0055
0056 #endif