soc/tegra/tegra210_mvc.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * tegra210_mvc.h - Definitions for Tegra210 MVC driver
0004  *
0005  * Copyright (c) 2021 NVIDIA CORPORATION.  All rights reserved.
0006  *
0007  */
0008
0009 #ifndef __TEGRA210_MVC_H__
0010 #define __TEGRA210_MVC_H__
0011
0012 /*
0013  * MVC_RX registers are with respect to XBAR.
0014  * The data comes from XBAR to MVC.
0015  */
0016 #define TEGRA210_MVC_RX_STATUS          0x0c
0017 #define TEGRA210_MVC_RX_INT_STATUS      0x10
0018 #define TEGRA210_MVC_RX_INT_MASK        0x14
0019 #define TEGRA210_MVC_RX_INT_SET         0x18
0020 #define TEGRA210_MVC_RX_INT_CLEAR       0x1c
0021 #define TEGRA210_MVC_RX_CIF_CTRL        0x20
0022
0023 /*
0024  * MVC_TX registers are with respect to XBAR.
0025  * The data goes out of MVC.
0026  */
0027 #define TEGRA210_MVC_TX_STATUS          0x4c
0028 #define TEGRA210_MVC_TX_INT_STATUS      0x50
0029 #define TEGRA210_MVC_TX_INT_MASK        0x54
0030 #define TEGRA210_MVC_TX_INT_SET         0x58
0031 #define TEGRA210_MVC_TX_INT_CLEAR       0x5c
0032 #define TEGRA210_MVC_TX_CIF_CTRL        0x60
0033
0034 /* Register offsets from TEGRA210_MVC*_BASE */
0035 #define TEGRA210_MVC_ENABLE         0x80
0036 #define TEGRA210_MVC_SOFT_RESET         0x84
0037 #define TEGRA210_MVC_CG             0x88
0038 #define TEGRA210_MVC_STATUS         0x90
0039 #define TEGRA210_MVC_INT_STATUS         0x94
0040 #define TEGRA210_MVC_CTRL           0xa8
0041 #define TEGRA210_MVC_SWITCH         0xac
0042 #define TEGRA210_MVC_INIT_VOL           0xb0
0043 #define TEGRA210_MVC_TARGET_VOL         0xd0
0044 #define TEGRA210_MVC_DURATION           0xf0
0045 #define TEGRA210_MVC_DURATION_INV       0xf4
0046 #define TEGRA210_MVC_POLY_N1            0xf8
0047 #define TEGRA210_MVC_POLY_N2            0xfc
0048 #define TEGRA210_MVC_PEAK_CTRL          0x100
0049 #define TEGRA210_MVC_CFG_RAM_CTRL       0x104
0050 #define TEGRA210_MVC_CFG_RAM_DATA       0x108
0051 #define TEGRA210_MVC_PEAK_VALUE         0x10c
0052 #define TEGRA210_MVC_CONFIG_ERR_TYPE        0x12c
0053
0054 /* Fields in TEGRA210_MVC_ENABLE */
0055 #define TEGRA210_MVC_EN_SHIFT           0
0056 #define TEGRA210_MVC_EN             (1 << TEGRA210_MVC_EN_SHIFT)
0057
0058 #define TEGRA210_MVC_MUTE_SHIFT         8
0059 #define TEGRA210_MUTE_MASK_EN           0xff
0060 #define TEGRA210_MVC_MUTE_MASK          (TEGRA210_MUTE_MASK_EN << TEGRA210_MVC_MUTE_SHIFT)
0061 #define TEGRA210_MVC_MUTE_EN            (TEGRA210_MUTE_MASK_EN << TEGRA210_MVC_MUTE_SHIFT)
0062 #define TEGRA210_MVC_CH0_MUTE_EN        1
0063
0064 #define TEGRA210_MVC_PER_CHAN_CTRL_EN_SHIFT 30
0065 #define TEGRA210_MVC_PER_CHAN_CTRL_EN_MASK  (1 << TEGRA210_MVC_PER_CHAN_CTRL_EN_SHIFT)
0066 #define TEGRA210_MVC_PER_CHAN_CTRL_EN       (1 << TEGRA210_MVC_PER_CHAN_CTRL_EN_SHIFT)
0067
0068 #define TEGRA210_MVC_CURVE_TYPE_SHIFT       1
0069 #define TEGRA210_MVC_CURVE_TYPE_MASK        (1 << TEGRA210_MVC_CURVE_TYPE_SHIFT)
0070
0071 #define TEGRA210_MVC_VOLUME_SWITCH_SHIFT    2
0072 #define TEGRA210_MVC_VOLUME_SWITCH_MASK     (1 << TEGRA210_MVC_VOLUME_SWITCH_SHIFT)
0073 #define TEGRA210_MVC_VOLUME_SWITCH_TRIGGER  (1 << TEGRA210_MVC_VOLUME_SWITCH_SHIFT)
0074 #define TEGRA210_MVC_CTRL_DEFAULT   0x40000003
0075
0076 #define TEGRA210_MVC_INIT_VOL_DEFAULT_POLY  0x01000000
0077 #define TEGRA210_MVC_INIT_VOL_DEFAULT_LINEAR    0x00000000
0078
0079 /* Fields in TEGRA210_MVC ram ctrl */
0080 #define TEGRA210_MVC_CFG_RAM_CTRL_RW_SHIFT      14
0081 #define TEGRA210_MVC_CFG_RAM_CTRL_RW_WRITE      (1 << TEGRA210_MVC_CFG_RAM_CTRL_RW_SHIFT)
0082
0083 #define TEGRA210_MVC_CFG_RAM_CTRL_ADDR_INIT_EN_SHIFT    13
0084 #define TEGRA210_MVC_CFG_RAM_CTRL_ADDR_INIT_EN      (1 << TEGRA210_MVC_CFG_RAM_CTRL_ADDR_INIT_EN_SHIFT)
0085
0086 #define TEGRA210_MVC_CFG_RAM_CTRL_SEQ_ACCESS_EN_SHIFT   12
0087 #define TEGRA210_MVC_CFG_RAM_CTRL_SEQ_ACCESS_EN     (1 << TEGRA210_MVC_CFG_RAM_CTRL_SEQ_ACCESS_EN_SHIFT)
0088
0089 #define TEGRA210_MVC_CFG_RAM_CTRL_ADDR_SHIFT        0
0090 #define TEGRA210_MVC_CFG_RAM_CTRL_ADDR_MASK     (0x1ff << TEGRA210_MVC_CFG_RAM_CTRL_ADDR_SHIFT)
0091
0092 #define REG_SIZE 4
0093 #define TEGRA210_MVC_MAX_CHAN_COUNT 8
0094 #define TEGRA210_MVC_REG_OFFSET(reg, i) (reg + (REG_SIZE * i))
0095
0096 #define TEGRA210_MVC_GET_CHAN(reg, base) (((reg) - (base)) / REG_SIZE)
0097
0098 #define TEGRA210_GET_MUTE_VAL(val) (((val) >> TEGRA210_MVC_MUTE_SHIFT) & TEGRA210_MUTE_MASK_EN)
0099
0100 #define NUM_GAIN_POLY_COEFFS 9
0101
0102 enum {
0103     CURVE_POLY,
0104     CURVE_LINEAR,
0105 };
0106
0107 struct tegra210_mvc_gain_params {
0108     int poly_coeff[NUM_GAIN_POLY_COEFFS];
0109     int poly_n1;
0110     int poly_n2;
0111     int duration;
0112     int duration_inv;
0113 };
0114
0115 struct tegra210_mvc {
0116     int volume[TEGRA210_MVC_MAX_CHAN_COUNT];
0117     unsigned int curve_type;
0118     unsigned int ctrl_value;
0119     struct regmap *regmap;
0120 };
0121
0122 #endif