soc/tegra/tegra210_mixer.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * tegra210_mixer.h - Definitions for Tegra210 MIXER driver
0004  *
0005  * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
0006  *
0007  */
0008
0009 #ifndef __TEGRA210_MIXER_H__
0010 #define __TEGRA210_MIXER_H__
0011
0012 /* XBAR_RX related MIXER offsets */
0013 #define TEGRA210_MIXER_RX1_SOFT_RESET   0x04
0014 #define TEGRA210_MIXER_RX1_STATUS   0x10
0015 #define TEGRA210_MIXER_RX1_CIF_CTRL 0x24
0016 #define TEGRA210_MIXER_RX1_CTRL     0x28
0017 #define TEGRA210_MIXER_RX1_PEAK_CTRL    0x2c
0018 #define TEGRA210_MIXER_RX1_SAMPLE_COUNT 0x30
0019
0020 /* XBAR_TX related MIXER offsets */
0021 #define TEGRA210_MIXER_TX1_ENABLE   0x280
0022 #define TEGRA210_MIXER_TX1_SOFT_RESET   0x284
0023 #define TEGRA210_MIXER_TX1_STATUS   0x290
0024 #define TEGRA210_MIXER_TX1_INT_STATUS   0x294
0025 #define TEGRA210_MIXER_TX1_INT_MASK 0x298
0026 #define TEGRA210_MIXER_TX1_INT_SET  0x29c
0027 #define TEGRA210_MIXER_TX1_INT_CLEAR    0x2a0
0028 #define TEGRA210_MIXER_TX1_CIF_CTRL 0x2a4
0029 #define TEGRA210_MIXER_TX1_ADDER_CONFIG 0x2a8
0030
0031 /* MIXER related offsets */
0032 #define TEGRA210_MIXER_ENABLE           0x400
0033 #define TEGRA210_MIXER_SOFT_RESET       0x404
0034 #define TEGRA210_MIXER_CG           0x408
0035 #define TEGRA210_MIXER_STATUS           0x410
0036 #define TEGRA210_MIXER_INT_STATUS       0x414
0037 #define TEGRA210_MIXER_GAIN_CFG_RAM_CTRL    0x42c
0038 #define TEGRA210_MIXER_GAIN_CFG_RAM_DATA    0x430
0039 #define TEGRA210_MIXER_PEAKM_RAM_CTRL       0x434
0040 #define TEGRA210_MIXER_PEAKM_RAM_DATA       0x438
0041 #define TEGRA210_MIXER_CTRL         0x43c
0042
0043 #define TEGRA210_MIXER_TX2_ADDER_CONFIG (TEGRA210_MIXER_TX1_ADDER_CONFIG + TEGRA210_MIXER_REG_STRIDE)
0044 #define TEGRA210_MIXER_TX3_ADDER_CONFIG (TEGRA210_MIXER_TX2_ADDER_CONFIG + TEGRA210_MIXER_REG_STRIDE)
0045 #define TEGRA210_MIXER_TX4_ADDER_CONFIG (TEGRA210_MIXER_TX3_ADDER_CONFIG + TEGRA210_MIXER_REG_STRIDE)
0046 #define TEGRA210_MIXER_TX5_ADDER_CONFIG (TEGRA210_MIXER_TX4_ADDER_CONFIG + TEGRA210_MIXER_REG_STRIDE)
0047
0048 #define TEGRA210_MIXER_TX2_ENABLE   (TEGRA210_MIXER_TX1_ENABLE + TEGRA210_MIXER_REG_STRIDE)
0049 #define TEGRA210_MIXER_TX3_ENABLE   (TEGRA210_MIXER_TX2_ENABLE + TEGRA210_MIXER_REG_STRIDE)
0050 #define TEGRA210_MIXER_TX4_ENABLE   (TEGRA210_MIXER_TX3_ENABLE + TEGRA210_MIXER_REG_STRIDE)
0051 #define TEGRA210_MIXER_TX5_ENABLE   (TEGRA210_MIXER_TX4_ENABLE + TEGRA210_MIXER_REG_STRIDE)
0052
0053 /* Fields in TEGRA210_MIXER_ENABLE */
0054 #define TEGRA210_MIXER_ENABLE_SHIFT 0
0055 #define TEGRA210_MIXER_ENABLE_MASK  (1 << TEGRA210_MIXER_ENABLE_SHIFT)
0056 #define TEGRA210_MIXER_EN       (1 << TEGRA210_MIXER_ENABLE_SHIFT)
0057
0058 /* Fields in TEGRA210_MIXER_GAIN_CFG_RAM_CTRL */
0059 #define TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_0      0x0
0060 #define TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_STRIDE     0x10
0061
0062 #define TEGRA210_MIXER_GAIN_CFG_RAM_RW_SHIFT        14
0063 #define TEGRA210_MIXER_GAIN_CFG_RAM_RW_MASK     (1 << TEGRA210_MIXER_GAIN_CFG_RAM_RW_SHIFT)
0064 #define TEGRA210_MIXER_GAIN_CFG_RAM_RW_WRITE        (1 << TEGRA210_MIXER_GAIN_CFG_RAM_RW_SHIFT)
0065
0066 #define TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_INIT_EN_SHIFT  13
0067 #define TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_INIT_EN_MASK   (1 << TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_INIT_EN_SHIFT)
0068 #define TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_INIT_EN    (1 << TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_INIT_EN_SHIFT)
0069
0070 #define TEGRA210_MIXER_GAIN_CFG_RAM_SEQ_ACCESS_EN_SHIFT 12
0071 #define TEGRA210_MIXER_GAIN_CFG_RAM_SEQ_ACCESS_EN_MASK  (1 << TEGRA210_MIXER_GAIN_CFG_RAM_SEQ_ACCESS_EN_SHIFT)
0072 #define TEGRA210_MIXER_GAIN_CFG_RAM_SEQ_ACCESS_EN   (1 << TEGRA210_MIXER_GAIN_CFG_RAM_SEQ_ACCESS_EN_SHIFT)
0073
0074 #define TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_SHIFT      0
0075 #define TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_MASK       (0x1ff << TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_SHIFT)
0076
0077 #define TEGRA210_MIXER_REG_STRIDE   0x40
0078 #define TEGRA210_MIXER_RX_MAX       10
0079 #define TEGRA210_MIXER_RX_LIMIT     (TEGRA210_MIXER_RX_MAX * TEGRA210_MIXER_REG_STRIDE)
0080 #define TEGRA210_MIXER_TX_MAX       5
0081 #define TEGRA210_MIXER_TX_LIMIT     (TEGRA210_MIXER_RX_LIMIT + (TEGRA210_MIXER_TX_MAX * TEGRA210_MIXER_REG_STRIDE))
0082
0083 #define REG_CFG_DONE_TRIGGER    0xf
0084 #define VAL_CFG_DONE_TRIGGER    0x1
0085
0086 #define NUM_GAIN_POLY_COEFFS 9
0087 #define NUM_DURATION_PARMS 4
0088
0089 struct tegra210_mixer_gain_params {
0090     int poly_coeff[NUM_GAIN_POLY_COEFFS];
0091     int gain_value;
0092     int duration[NUM_DURATION_PARMS];
0093 };
0094
0095 struct tegra210_mixer {
0096     int gain_value[TEGRA210_MIXER_RX_MAX];
0097     struct regmap *regmap;
0098 };
0099
0100 #endif