soc/tegra/tegra210_mbdrc.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * tegra210_mbdrc.h - Definitions for Tegra210 MBDRC driver
0004  *
0005  * Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
0006  *
0007  */
0008
0009 #ifndef __TEGRA210_MBDRC_H__
0010 #define __TEGRA210_MBDRC_H__
0011
0012 #include <linux/platform_device.h>
0013 #include <sound/soc.h>
0014
0015 /* Register offsets from TEGRA210_MBDRC*_BASE */
0016 #define TEGRA210_MBDRC_SOFT_RESET           0x4
0017 #define TEGRA210_MBDRC_CG               0x8
0018 #define TEGRA210_MBDRC_STATUS               0xc
0019 #define TEGRA210_MBDRC_CFG              0x28
0020 #define TEGRA210_MBDRC_CHANNEL_MASK         0x2c
0021 #define TEGRA210_MBDRC_MASTER_VOL           0x30
0022 #define TEGRA210_MBDRC_FAST_FACTOR          0x34
0023
0024 #define TEGRA210_MBDRC_FILTER_COUNT         3
0025 #define TEGRA210_MBDRC_FILTER_PARAM_STRIDE      0x4
0026
0027 #define TEGRA210_MBDRC_IIR_CFG              0x38
0028 #define TEGRA210_MBDRC_IN_ATTACK            0x44
0029 #define TEGRA210_MBDRC_IN_RELEASE           0x50
0030 #define TEGRA210_MBDRC_FAST_ATTACK          0x5c
0031 #define TEGRA210_MBDRC_IN_THRESHOLD         0x68
0032 #define TEGRA210_MBDRC_OUT_THRESHOLD            0x74
0033 #define TEGRA210_MBDRC_RATIO_1ST            0x80
0034 #define TEGRA210_MBDRC_RATIO_2ND            0x8c
0035 #define TEGRA210_MBDRC_RATIO_3RD            0x98
0036 #define TEGRA210_MBDRC_RATIO_4TH            0xa4
0037 #define TEGRA210_MBDRC_RATIO_5TH            0xb0
0038 #define TEGRA210_MBDRC_MAKEUP_GAIN          0xbc
0039 #define TEGRA210_MBDRC_INIT_GAIN            0xc8
0040 #define TEGRA210_MBDRC_GAIN_ATTACK          0xd4
0041 #define TEGRA210_MBDRC_GAIN_RELEASE         0xe0
0042 #define TEGRA210_MBDRC_FAST_RELEASE         0xec
0043 #define TEGRA210_MBDRC_CFG_RAM_CTRL         0xf8
0044 #define TEGRA210_MBDRC_CFG_RAM_DATA         0x104
0045
0046 #define TEGRA210_MBDRC_MAX_REG              (TEGRA210_MBDRC_CFG_RAM_DATA +      \
0047                              (TEGRA210_MBDRC_FILTER_PARAM_STRIDE *  \
0048                               (TEGRA210_MBDRC_FILTER_COUNT - 1)))
0049
0050 /* Fields for TEGRA210_MBDRC_CFG */
0051 #define TEGRA210_MBDRC_CFG_RMS_OFFSET_SHIFT     16
0052 #define TEGRA210_MBDRC_CFG_RMS_OFFSET_MASK      (0x1ff << TEGRA210_MBDRC_CFG_RMS_OFFSET_SHIFT)
0053
0054 #define TEGRA210_MBDRC_CFG_PEAK_RMS_SHIFT       14
0055 #define TEGRA210_MBDRC_CFG_PEAK_RMS_MASK        (0x1 << TEGRA210_MBDRC_CFG_PEAK_RMS_SHIFT)
0056 #define TEGRA210_MBDRC_CFG_PEAK             (1 << TEGRA210_MBDRC_CFG_PEAK_RMS_SHIFT)
0057
0058 #define TEGRA210_MBDRC_CFG_FILTER_STRUCTURE_SHIFT   13
0059 #define TEGRA210_MBDRC_CFG_FILTER_STRUCTURE_MASK    (0x1 << TEGRA210_MBDRC_CFG_FILTER_STRUCTURE_SHIFT)
0060 #define TEGRA210_MBDRC_CFG_FILTER_STRUCTURE_FLEX    (1 << TEGRA210_MBDRC_CFG_FILTER_STRUCTURE_SHIFT)
0061
0062 #define TEGRA210_MBDRC_CFG_SHIFT_CTRL_SHIFT     8
0063 #define TEGRA210_MBDRC_CFG_SHIFT_CTRL_MASK      (0x1f << TEGRA210_MBDRC_CFG_SHIFT_CTRL_SHIFT)
0064
0065 #define TEGRA210_MBDRC_CFG_FRAME_SIZE_SHIFT     4
0066 #define TEGRA210_MBDRC_CFG_FRAME_SIZE_MASK      (0xf << TEGRA210_MBDRC_CFG_FRAME_SIZE_SHIFT)
0067
0068 #define TEGRA210_MBDRC_CFG_MBDRC_MODE_SHIFT     0
0069 #define TEGRA210_MBDRC_CFG_MBDRC_MODE_MASK      (0x3 << TEGRA210_MBDRC_CFG_MBDRC_MODE_SHIFT)
0070 #define TEGRA210_MBDRC_CFG_MBDRC_MODE_BYPASS        (0 << TEGRA210_MBDRC_CFG_MBDRC_MODE_SHIFT)
0071
0072 /* Fields for TEGRA210_MBDRC_CHANNEL_MASK */
0073 #define TEGRA210_MBDRC_CHANNEL_MASK_SHIFT       0
0074 #define TEGRA210_MBDRC_CHANNEL_MASK_MASK        (0xff << TEGRA210_MBDRC_CHANNEL_MASK_SHIFT)
0075
0076 /* Fields for TEGRA210_MBDRC_MASTER_VOL */
0077 #define TEGRA210_MBDRC_MASTER_VOL_SHIFT         23
0078 #define TEGRA210_MBDRC_MASTER_VOL_MIN           -256
0079 #define TEGRA210_MBDRC_MASTER_VOL_MAX           256
0080
0081 /* Fields for TEGRA210_MBDRC_FAST_FACTOR */
0082 #define TEGRA210_MBDRC_FAST_FACTOR_RELEASE_SHIFT    16
0083 #define TEGRA210_MBDRC_FAST_FACTOR_RELEASE_MASK     (0xffff << TEGRA210_MBDRC_FAST_FACTOR_RELEASE_SHIFT)
0084
0085 #define TEGRA210_MBDRC_FAST_FACTOR_ATTACK_SHIFT     0
0086 #define TEGRA210_MBDRC_FAST_FACTOR_ATTACK_MASK      (0xffff << TEGRA210_MBDRC_FAST_FACTOR_ATTACK_SHIFT)
0087
0088 /* Fields for TEGRA210_MBDRC_IIR_CFG */
0089 #define TEGRA210_MBDRC_IIR_CFG_NUM_STAGES_SHIFT     0
0090 #define TEGRA210_MBDRC_IIR_CFG_NUM_STAGES_MASK      (0xf << TEGRA210_MBDRC_IIR_CFG_NUM_STAGES_SHIFT)
0091
0092 /* Fields for TEGRA210_MBDRC_IN_ATTACK */
0093 #define TEGRA210_MBDRC_IN_ATTACK_TC_SHIFT       0
0094 #define TEGRA210_MBDRC_IN_ATTACK_TC_MASK        (0xffffffff << TEGRA210_MBDRC_IN_ATTACK_TC_SHIFT)
0095
0096 /* Fields for TEGRA210_MBDRC_IN_RELEASE */
0097 #define TEGRA210_MBDRC_IN_RELEASE_TC_SHIFT      0
0098 #define TEGRA210_MBDRC_IN_RELEASE_TC_MASK       (0xffffffff << TEGRA210_MBDRC_IN_RELEASE_TC_SHIFT)
0099
0100 /* Fields for TEGRA210_MBDRC_FAST_ATTACK */
0101 #define TEGRA210_MBDRC_FAST_ATTACK_TC_SHIFT     0
0102 #define TEGRA210_MBDRC_FAST_ATTACK_TC_MASK      (0xffffffff << TEGRA210_MBDRC_FAST_ATTACK_TC_SHIFT)
0103
0104 /* Fields for TEGRA210_MBDRC_IN_THRESHOLD / TEGRA210_MBDRC_OUT_THRESHOLD */
0105 #define TEGRA210_MBDRC_THRESH_4TH_SHIFT         24
0106 #define TEGRA210_MBDRC_THRESH_4TH_MASK          (0xff << TEGRA210_MBDRC_THRESH_4TH_SHIFT)
0107
0108 #define TEGRA210_MBDRC_THRESH_3RD_SHIFT         16
0109 #define TEGRA210_MBDRC_THRESH_3RD_MASK          (0xff << TEGRA210_MBDRC_THRESH_3RD_SHIFT)
0110
0111 #define TEGRA210_MBDRC_THRESH_2ND_SHIFT         8
0112 #define TEGRA210_MBDRC_THRESH_2ND_MASK          (0xff << TEGRA210_MBDRC_THRESH_2ND_SHIFT)
0113
0114 #define TEGRA210_MBDRC_THRESH_1ST_SHIFT         0
0115 #define TEGRA210_MBDRC_THRESH_1ST_MASK          (0xff << TEGRA210_MBDRC_THRESH_1ST_SHIFT)
0116
0117 /* Fields for TEGRA210_MBDRC_RATIO_1ST */
0118 #define TEGRA210_MBDRC_RATIO_1ST_SHIFT          0
0119 #define TEGRA210_MBDRC_RATIO_1ST_MASK           (0xffff << TEGRA210_MBDRC_RATIO_1ST_SHIFT)
0120
0121 /* Fields for TEGRA210_MBDRC_RATIO_2ND */
0122 #define TEGRA210_MBDRC_RATIO_2ND_SHIFT          0
0123 #define TEGRA210_MBDRC_RATIO_2ND_MASK           (0xffff << TEGRA210_MBDRC_RATIO_2ND_SHIFT)
0124
0125 /* Fields for TEGRA210_MBDRC_RATIO_3RD */
0126 #define TEGRA210_MBDRC_RATIO_3RD_SHIFT          0
0127 #define TEGRA210_MBDRC_RATIO_3RD_MASK           (0xffff << TEGRA210_MBDRC_RATIO_3RD_SHIFT)
0128
0129 /* Fields for TEGRA210_MBDRC_RATIO_4TH */
0130 #define TEGRA210_MBDRC_RATIO_4TH_SHIFT          0
0131 #define TEGRA210_MBDRC_RATIO_4TH_MASK           (0xffff << TEGRA210_MBDRC_RATIO_4TH_SHIFT)
0132
0133 /* Fields for TEGRA210_MBDRC_RATIO_5TH */
0134 #define TEGRA210_MBDRC_RATIO_5TH_SHIFT          0
0135 #define TEGRA210_MBDRC_RATIO_5TH_MASK           (0xffff << TEGRA210_MBDRC_RATIO_5TH_SHIFT)
0136
0137 /* Fields for TEGRA210_MBDRC_MAKEUP_GAIN */
0138 #define TEGRA210_MBDRC_MAKEUP_GAIN_SHIFT        0
0139 #define TEGRA210_MBDRC_MAKEUP_GAIN_MASK         (0x3f << TEGRA210_MBDRC_MAKEUP_GAIN_SHIFT)
0140
0141 /* Fields for TEGRA210_MBDRC_INIT_GAIN */
0142 #define TEGRA210_MBDRC_INIT_GAIN_SHIFT          0
0143 #define TEGRA210_MBDRC_INIT_GAIN_MASK           (0xffffffff << TEGRA210_MBDRC_INIT_GAIN_SHIFT)
0144
0145 /* Fields for TEGRA210_MBDRC_GAIN_ATTACK */
0146 #define TEGRA210_MBDRC_GAIN_ATTACK_SHIFT        0
0147 #define TEGRA210_MBDRC_GAIN_ATTACK_MASK         (0xffffffff << TEGRA210_MBDRC_GAIN_ATTACK_SHIFT)
0148
0149 /* Fields for TEGRA210_MBDRC_GAIN_RELEASE */
0150 #define TEGRA210_MBDRC_GAIN_RELEASE_SHIFT       0
0151 #define TEGRA210_MBDRC_GAIN_RELEASE_MASK        (0xffffffff << TEGRA210_MBDRC_GAIN_RELEASE_SHIFT)
0152
0153 /* Fields for TEGRA210_MBDRC_FAST_RELEASE */
0154 #define TEGRA210_MBDRC_FAST_RELEASE_SHIFT       0
0155 #define TEGRA210_MBDRC_FAST_RELEASE_MASK        (0xffffffff << TEGRA210_MBDRC_FAST_RELEASE_SHIFT)
0156
0157 #define TEGRA210_MBDRC_RAM_CTRL_RW_READ         0
0158 #define TEGRA210_MBDRC_RAM_CTRL_RW_WRITE        (1 << 14)
0159 #define TEGRA210_MBDRC_RAM_CTRL_ADDR_INIT_EN        (1 << 13)
0160 #define TEGRA210_MBDRC_RAM_CTRL_SEQ_ACCESS_EN       (1 << 12)
0161 #define TEGRA210_MBDRC_RAM_CTRL_RAM_ADDR_MASK       0x1ff
0162
0163 /*
0164  * Order and size of each structure element for following structures should not
0165  * be altered size order of elements and their size are based on PEQ co-eff ram
0166  * and shift ram layout.
0167  */
0168 #define TEGRA210_MBDRC_THRESHOLD_NUM                4
0169 #define TEGRA210_MBDRC_RATIO_NUM                (TEGRA210_MBDRC_THRESHOLD_NUM + 1)
0170 #define TEGRA210_MBDRC_MAX_BIQUAD_STAGES            8
0171
0172 /* Order of these enums are same as the order of band specific hw registers */
0173 enum {
0174     MBDRC_LOW_BAND,
0175     MBDRC_MID_BAND,
0176     MBDRC_HIGH_BAND,
0177     MBDRC_NUM_BAND,
0178 };
0179
0180 struct tegra210_mbdrc_band_params {
0181     u32 band;
0182     u32 iir_stages;
0183     u32 in_attack_tc;
0184     u32 in_release_tc;
0185     u32 fast_attack_tc;
0186     u32 in_threshold[TEGRA210_MBDRC_THRESHOLD_NUM];
0187     u32 out_threshold[TEGRA210_MBDRC_THRESHOLD_NUM];
0188     u32 ratio[TEGRA210_MBDRC_RATIO_NUM];
0189     u32 makeup_gain;
0190     u32 gain_init;
0191     u32 gain_attack_tc;
0192     u32 gain_release_tc;
0193     u32 fast_release_tc;
0194     /* For biquad_params[][5] order of coeff is b0, b1, a0, a1, a2 */
0195     u32 biquad_params[TEGRA210_MBDRC_MAX_BIQUAD_STAGES * 5];
0196 };
0197
0198 struct tegra210_mbdrc_config {
0199     unsigned int mode;
0200     unsigned int rms_off;
0201     unsigned int peak_rms_mode;
0202     unsigned int fliter_structure;
0203     unsigned int shift_ctrl;
0204     unsigned int frame_size;
0205     unsigned int channel_mask;
0206     unsigned int fa_factor; /* Fast attack factor */
0207     unsigned int fr_factor; /* Fast release factor */
0208     struct tegra210_mbdrc_band_params band_params[MBDRC_NUM_BAND];
0209 };
0210
0211 int tegra210_mbdrc_regmap_init(struct platform_device *pdev);
0212 int tegra210_mbdrc_component_init(struct snd_soc_component *cmpnt);
0213 int tegra210_mbdrc_hw_params(struct snd_soc_component *cmpnt);
0214
0215 #endif