soc/tegra/tegra210_i2s.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * tegra210_i2s.h - Definitions for Tegra210 I2S driver
0004  *
0005  * Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved.
0006  *
0007  */
0008
0009 #ifndef __TEGRA210_I2S_H__
0010 #define __TEGRA210_I2S_H__
0011
0012 /* Register offsets from I2S*_BASE */
0013 #define TEGRA210_I2S_RX_ENABLE          0x0
0014 #define TEGRA210_I2S_RX_SOFT_RESET      0x4
0015 #define TEGRA210_I2S_RX_STATUS          0x0c
0016 #define TEGRA210_I2S_RX_INT_STATUS      0x10
0017 #define TEGRA210_I2S_RX_INT_MASK        0x14
0018 #define TEGRA210_I2S_RX_INT_SET         0x18
0019 #define TEGRA210_I2S_RX_INT_CLEAR       0x1c
0020 #define TEGRA210_I2S_RX_CIF_CTRL        0x20
0021 #define TEGRA210_I2S_RX_CTRL            0x24
0022 #define TEGRA210_I2S_RX_SLOT_CTRL       0x28
0023 #define TEGRA210_I2S_RX_CLK_TRIM        0x2c
0024 #define TEGRA210_I2S_RX_CYA         0x30
0025 #define TEGRA210_I2S_RX_CIF_FIFO_STATUS     0x34
0026 #define TEGRA210_I2S_TX_ENABLE          0x40
0027 #define TEGRA210_I2S_TX_SOFT_RESET      0x44
0028 #define TEGRA210_I2S_TX_STATUS          0x4c
0029 #define TEGRA210_I2S_TX_INT_STATUS      0x50
0030 #define TEGRA210_I2S_TX_INT_MASK        0x54
0031 #define TEGRA210_I2S_TX_INT_SET         0x58
0032 #define TEGRA210_I2S_TX_INT_CLEAR       0x5c
0033 #define TEGRA210_I2S_TX_CIF_CTRL        0x60
0034 #define TEGRA210_I2S_TX_CTRL            0x64
0035 #define TEGRA210_I2S_TX_SLOT_CTRL       0x68
0036 #define TEGRA210_I2S_TX_CLK_TRIM        0x6c
0037 #define TEGRA210_I2S_TX_CYA         0x70
0038 #define TEGRA210_I2S_TX_CIF_FIFO_STATUS     0x74
0039 #define TEGRA210_I2S_ENABLE         0x80
0040 #define TEGRA210_I2S_SOFT_RESET         0x84
0041 #define TEGRA210_I2S_CG             0x88
0042 #define TEGRA210_I2S_STATUS         0x8c
0043 #define TEGRA210_I2S_INT_STATUS         0x90
0044 #define TEGRA210_I2S_CTRL           0xa0
0045 #define TEGRA210_I2S_TIMING         0xa4
0046 #define TEGRA210_I2S_SLOT_CTRL          0xa8
0047 #define TEGRA210_I2S_CLK_TRIM           0xac
0048 #define TEGRA210_I2S_CYA            0xb0
0049
0050 /* Bit fields, shifts and masks */
0051 #define I2S_DATA_SHIFT              8
0052 #define I2S_CTRL_DATA_OFFSET_MASK       (0x7ff << I2S_DATA_SHIFT)
0053
0054 #define I2S_EN_SHIFT                0
0055 #define I2S_EN_MASK             BIT(I2S_EN_SHIFT)
0056 #define I2S_EN                  BIT(I2S_EN_SHIFT)
0057
0058 #define I2S_FSYNC_WIDTH_SHIFT           24
0059 #define I2S_CTRL_FSYNC_WIDTH_MASK       (0xff << I2S_FSYNC_WIDTH_SHIFT)
0060
0061 #define I2S_POS_EDGE                0
0062 #define I2S_NEG_EDGE                1
0063 #define I2S_EDGE_SHIFT              20
0064 #define I2S_CTRL_EDGE_CTRL_MASK         BIT(I2S_EDGE_SHIFT)
0065 #define I2S_CTRL_EDGE_CTRL_POS_EDGE     (I2S_POS_EDGE << I2S_EDGE_SHIFT)
0066 #define I2S_CTRL_EDGE_CTRL_NEG_EDGE     (I2S_NEG_EDGE << I2S_EDGE_SHIFT)
0067
0068 #define I2S_FMT_LRCK                0
0069 #define I2S_FMT_FSYNC               1
0070 #define I2S_FMT_SHIFT               12
0071 #define I2S_CTRL_FRAME_FMT_MASK         (7 << I2S_FMT_SHIFT)
0072 #define I2S_CTRL_FRAME_FMT_LRCK_MODE        (I2S_FMT_LRCK << I2S_FMT_SHIFT)
0073 #define I2S_CTRL_FRAME_FMT_FSYNC_MODE       (I2S_FMT_FSYNC << I2S_FMT_SHIFT)
0074
0075 #define I2S_CTRL_MASTER_EN_SHIFT        10
0076 #define I2S_CTRL_MASTER_EN_MASK         BIT(I2S_CTRL_MASTER_EN_SHIFT)
0077 #define I2S_CTRL_MASTER_EN          BIT(I2S_CTRL_MASTER_EN_SHIFT)
0078
0079 #define I2S_CTRL_LRCK_POL_SHIFT         9
0080 #define I2S_CTRL_LRCK_POL_MASK          BIT(I2S_CTRL_LRCK_POL_SHIFT)
0081 #define I2S_CTRL_LRCK_POL_LOW           (0 << I2S_CTRL_LRCK_POL_SHIFT)
0082 #define I2S_CTRL_LRCK_POL_HIGH          BIT(I2S_CTRL_LRCK_POL_SHIFT)
0083
0084 #define I2S_CTRL_LPBK_SHIFT         8
0085 #define I2S_CTRL_LPBK_MASK          BIT(I2S_CTRL_LPBK_SHIFT)
0086 #define I2S_CTRL_LPBK_EN            BIT(I2S_CTRL_LPBK_SHIFT)
0087
0088 #define I2S_BITS_8              1
0089 #define I2S_BITS_16             3
0090 #define I2S_BITS_32             7
0091 #define I2S_CTRL_BIT_SIZE_MASK          0x7
0092
0093 #define I2S_TIMING_CH_BIT_CNT_MASK      0x7ff
0094 #define I2S_TIMING_CH_BIT_CNT_SHIFT     0
0095
0096 #define I2S_SOFT_RESET_SHIFT            0
0097 #define I2S_SOFT_RESET_MASK         BIT(I2S_SOFT_RESET_SHIFT)
0098 #define I2S_SOFT_RESET_EN           BIT(I2S_SOFT_RESET_SHIFT)
0099
0100 #define I2S_RX_FIFO_DEPTH           64
0101 #define DEFAULT_I2S_RX_FIFO_THRESHOLD       3
0102
0103 #define DEFAULT_I2S_SLOT_MASK           0xffff
0104
0105 enum tegra210_i2s_path {
0106     I2S_RX_PATH,
0107     I2S_TX_PATH,
0108     I2S_PATHS,
0109 };
0110
0111 struct tegra210_i2s {
0112     struct clk *clk_i2s;
0113     struct clk *clk_sync_input;
0114     struct regmap *regmap;
0115     unsigned int stereo_to_mono[I2S_PATHS];
0116     unsigned int mono_to_stereo[I2S_PATHS];
0117     unsigned int dai_fmt;
0118     unsigned int fsync_width;
0119     unsigned int bclk_ratio;
0120     unsigned int tx_mask;
0121     unsigned int rx_mask;
0122     unsigned int rx_fifo_th;
0123     bool loopback;
0124 };
0125
0126 #endif