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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 //
0003 // tegra210_i2s.c - Tegra210 I2S driver
0004 //
0005 // Copyright (c) 2020 NVIDIA CORPORATION.  All rights reserved.
0006 
0007 #include <linux/clk.h>
0008 #include <linux/device.h>
0009 #include <linux/module.h>
0010 #include <linux/of_device.h>
0011 #include <linux/platform_device.h>
0012 #include <linux/pm_runtime.h>
0013 #include <linux/regmap.h>
0014 #include <sound/core.h>
0015 #include <sound/pcm_params.h>
0016 #include <sound/soc.h>
0017 #include "tegra210_i2s.h"
0018 #include "tegra_cif.h"
0019 
0020 static const struct reg_default tegra210_i2s_reg_defaults[] = {
0021     { TEGRA210_I2S_RX_INT_MASK, 0x00000003 },
0022     { TEGRA210_I2S_RX_CIF_CTRL, 0x00007700 },
0023     { TEGRA210_I2S_TX_INT_MASK, 0x00000003 },
0024     { TEGRA210_I2S_TX_CIF_CTRL, 0x00007700 },
0025     { TEGRA210_I2S_CG, 0x1 },
0026     { TEGRA210_I2S_TIMING, 0x0000001f },
0027     { TEGRA210_I2S_ENABLE, 0x1 },
0028     /*
0029      * Below update does not have any effect on Tegra186 and Tegra194.
0030      * On Tegra210, I2S4 has "i2s4a" and "i2s4b" pins and below update
0031      * is required to select i2s4b for it to be functional for I2S
0032      * operation.
0033      */
0034     { TEGRA210_I2S_CYA, 0x1 },
0035 };
0036 
0037 static void tegra210_i2s_set_slot_ctrl(struct regmap *regmap,
0038                        unsigned int total_slots,
0039                        unsigned int tx_slot_mask,
0040                        unsigned int rx_slot_mask)
0041 {
0042     regmap_write(regmap, TEGRA210_I2S_SLOT_CTRL, total_slots - 1);
0043     regmap_write(regmap, TEGRA210_I2S_TX_SLOT_CTRL, tx_slot_mask);
0044     regmap_write(regmap, TEGRA210_I2S_RX_SLOT_CTRL, rx_slot_mask);
0045 }
0046 
0047 static int tegra210_i2s_set_clock_rate(struct device *dev,
0048                        unsigned int clock_rate)
0049 {
0050     struct tegra210_i2s *i2s = dev_get_drvdata(dev);
0051     unsigned int val;
0052     int err;
0053 
0054     regmap_read(i2s->regmap, TEGRA210_I2S_CTRL, &val);
0055 
0056     /* No need to set rates if I2S is being operated in slave */
0057     if (!(val & I2S_CTRL_MASTER_EN))
0058         return 0;
0059 
0060     err = clk_set_rate(i2s->clk_i2s, clock_rate);
0061     if (err) {
0062         dev_err(dev, "can't set I2S bit clock rate %u, err: %d\n",
0063             clock_rate, err);
0064         return err;
0065     }
0066 
0067     if (!IS_ERR(i2s->clk_sync_input)) {
0068         /*
0069          * Other I/O modules in AHUB can use i2s bclk as reference
0070          * clock. Below sets sync input clock rate as per bclk,
0071          * which can be used as input to other I/O modules.
0072          */
0073         err = clk_set_rate(i2s->clk_sync_input, clock_rate);
0074         if (err) {
0075             dev_err(dev,
0076                 "can't set I2S sync input rate %u, err = %d\n",
0077                 clock_rate, err);
0078             return err;
0079         }
0080     }
0081 
0082     return 0;
0083 }
0084 
0085 static int tegra210_i2s_sw_reset(struct snd_soc_component *compnt,
0086                  bool is_playback)
0087 {
0088     struct device *dev = compnt->dev;
0089     struct tegra210_i2s *i2s = dev_get_drvdata(dev);
0090     unsigned int reset_mask = I2S_SOFT_RESET_MASK;
0091     unsigned int reset_en = I2S_SOFT_RESET_EN;
0092     unsigned int reset_reg, cif_reg, stream_reg;
0093     unsigned int cif_ctrl, stream_ctrl, i2s_ctrl, val;
0094     int err;
0095 
0096     if (is_playback) {
0097         reset_reg = TEGRA210_I2S_RX_SOFT_RESET;
0098         cif_reg = TEGRA210_I2S_RX_CIF_CTRL;
0099         stream_reg = TEGRA210_I2S_RX_CTRL;
0100     } else {
0101         reset_reg = TEGRA210_I2S_TX_SOFT_RESET;
0102         cif_reg = TEGRA210_I2S_TX_CIF_CTRL;
0103         stream_reg = TEGRA210_I2S_TX_CTRL;
0104     }
0105 
0106     /* Store CIF and I2S control values */
0107     regmap_read(i2s->regmap, cif_reg, &cif_ctrl);
0108     regmap_read(i2s->regmap, stream_reg, &stream_ctrl);
0109     regmap_read(i2s->regmap, TEGRA210_I2S_CTRL, &i2s_ctrl);
0110 
0111     /* Reset to make sure the previous transactions are clean */
0112     regmap_update_bits(i2s->regmap, reset_reg, reset_mask, reset_en);
0113 
0114     err = regmap_read_poll_timeout(i2s->regmap, reset_reg, val,
0115                        !(val & reset_mask & reset_en),
0116                        10, 10000);
0117     if (err) {
0118         dev_err(dev, "timeout: failed to reset I2S for %s\n",
0119             is_playback ? "playback" : "capture");
0120         return err;
0121     }
0122 
0123     /* Restore CIF and I2S control values */
0124     regmap_write(i2s->regmap, cif_reg, cif_ctrl);
0125     regmap_write(i2s->regmap, stream_reg, stream_ctrl);
0126     regmap_write(i2s->regmap, TEGRA210_I2S_CTRL, i2s_ctrl);
0127 
0128     return 0;
0129 }
0130 
0131 static int tegra210_i2s_init(struct snd_soc_dapm_widget *w,
0132                  struct snd_kcontrol *kcontrol, int event)
0133 {
0134     struct snd_soc_component *compnt = snd_soc_dapm_to_component(w->dapm);
0135     struct device *dev = compnt->dev;
0136     struct tegra210_i2s *i2s = dev_get_drvdata(dev);
0137     unsigned int val, status_reg;
0138     bool is_playback;
0139     int err;
0140 
0141     switch (w->reg) {
0142     case TEGRA210_I2S_RX_ENABLE:
0143         is_playback = true;
0144         status_reg = TEGRA210_I2S_RX_STATUS;
0145         break;
0146     case TEGRA210_I2S_TX_ENABLE:
0147         is_playback = false;
0148         status_reg = TEGRA210_I2S_TX_STATUS;
0149         break;
0150     default:
0151         return -EINVAL;
0152     }
0153 
0154     /* Ensure I2S is in disabled state before new session */
0155     err = regmap_read_poll_timeout(i2s->regmap, status_reg, val,
0156                        !(val & I2S_EN_MASK & I2S_EN),
0157                        10, 10000);
0158     if (err) {
0159         dev_err(dev, "timeout: previous I2S %s is still active\n",
0160             is_playback ? "playback" : "capture");
0161         return err;
0162     }
0163 
0164     return tegra210_i2s_sw_reset(compnt, is_playback);
0165 }
0166 
0167 static int __maybe_unused tegra210_i2s_runtime_suspend(struct device *dev)
0168 {
0169     struct tegra210_i2s *i2s = dev_get_drvdata(dev);
0170 
0171     regcache_cache_only(i2s->regmap, true);
0172     regcache_mark_dirty(i2s->regmap);
0173 
0174     clk_disable_unprepare(i2s->clk_i2s);
0175 
0176     return 0;
0177 }
0178 
0179 static int __maybe_unused tegra210_i2s_runtime_resume(struct device *dev)
0180 {
0181     struct tegra210_i2s *i2s = dev_get_drvdata(dev);
0182     int err;
0183 
0184     err = clk_prepare_enable(i2s->clk_i2s);
0185     if (err) {
0186         dev_err(dev, "failed to enable I2S bit clock, err: %d\n", err);
0187         return err;
0188     }
0189 
0190     regcache_cache_only(i2s->regmap, false);
0191     regcache_sync(i2s->regmap);
0192 
0193     return 0;
0194 }
0195 
0196 static void tegra210_i2s_set_data_offset(struct tegra210_i2s *i2s,
0197                      unsigned int data_offset)
0198 {
0199     /* Capture path */
0200     regmap_update_bits(i2s->regmap, TEGRA210_I2S_TX_CTRL,
0201                I2S_CTRL_DATA_OFFSET_MASK,
0202                data_offset << I2S_DATA_SHIFT);
0203 
0204     /* Playback path */
0205     regmap_update_bits(i2s->regmap, TEGRA210_I2S_RX_CTRL,
0206                I2S_CTRL_DATA_OFFSET_MASK,
0207                data_offset << I2S_DATA_SHIFT);
0208 }
0209 
0210 static int tegra210_i2s_set_fmt(struct snd_soc_dai *dai,
0211                 unsigned int fmt)
0212 {
0213     struct tegra210_i2s *i2s = snd_soc_dai_get_drvdata(dai);
0214     unsigned int mask, val;
0215 
0216     mask = I2S_CTRL_MASTER_EN_MASK;
0217     switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
0218     case SND_SOC_DAIFMT_BC_FC:
0219         val = 0;
0220         break;
0221     case SND_SOC_DAIFMT_BP_FP:
0222         val = I2S_CTRL_MASTER_EN;
0223         break;
0224     default:
0225         return -EINVAL;
0226     }
0227 
0228     mask |= I2S_CTRL_FRAME_FMT_MASK | I2S_CTRL_LRCK_POL_MASK;
0229     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0230     case SND_SOC_DAIFMT_DSP_A:
0231         val |= I2S_CTRL_FRAME_FMT_FSYNC_MODE;
0232         val |= I2S_CTRL_LRCK_POL_HIGH;
0233         tegra210_i2s_set_data_offset(i2s, 1);
0234         break;
0235     case SND_SOC_DAIFMT_DSP_B:
0236         val |= I2S_CTRL_FRAME_FMT_FSYNC_MODE;
0237         val |= I2S_CTRL_LRCK_POL_HIGH;
0238         tegra210_i2s_set_data_offset(i2s, 0);
0239         break;
0240     /* I2S mode has data offset of 1 */
0241     case SND_SOC_DAIFMT_I2S:
0242         val |= I2S_CTRL_FRAME_FMT_LRCK_MODE;
0243         val |= I2S_CTRL_LRCK_POL_LOW;
0244         tegra210_i2s_set_data_offset(i2s, 1);
0245         break;
0246     /*
0247      * For RJ mode data offset is dependent on the sample size
0248      * and the bclk ratio, and so is set when hw_params is called.
0249      */
0250     case SND_SOC_DAIFMT_RIGHT_J:
0251         val |= I2S_CTRL_FRAME_FMT_LRCK_MODE;
0252         val |= I2S_CTRL_LRCK_POL_HIGH;
0253         break;
0254     case SND_SOC_DAIFMT_LEFT_J:
0255         val |= I2S_CTRL_FRAME_FMT_LRCK_MODE;
0256         val |= I2S_CTRL_LRCK_POL_HIGH;
0257         tegra210_i2s_set_data_offset(i2s, 0);
0258         break;
0259     default:
0260         return -EINVAL;
0261     }
0262 
0263     mask |= I2S_CTRL_EDGE_CTRL_MASK;
0264     switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
0265     case SND_SOC_DAIFMT_NB_NF:
0266         val |= I2S_CTRL_EDGE_CTRL_POS_EDGE;
0267         break;
0268     case SND_SOC_DAIFMT_NB_IF:
0269         val |= I2S_CTRL_EDGE_CTRL_POS_EDGE;
0270         val ^= I2S_CTRL_LRCK_POL_MASK;
0271         break;
0272     case SND_SOC_DAIFMT_IB_NF:
0273         val |= I2S_CTRL_EDGE_CTRL_NEG_EDGE;
0274         break;
0275     case SND_SOC_DAIFMT_IB_IF:
0276         val |= I2S_CTRL_EDGE_CTRL_NEG_EDGE;
0277         val ^= I2S_CTRL_LRCK_POL_MASK;
0278         break;
0279     default:
0280         return -EINVAL;
0281     }
0282 
0283     regmap_update_bits(i2s->regmap, TEGRA210_I2S_CTRL, mask, val);
0284 
0285     i2s->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
0286 
0287     return 0;
0288 }
0289 
0290 static int tegra210_i2s_set_tdm_slot(struct snd_soc_dai *dai,
0291                      unsigned int tx_mask, unsigned int rx_mask,
0292                      int slots, int slot_width)
0293 {
0294     struct tegra210_i2s *i2s = snd_soc_dai_get_drvdata(dai);
0295 
0296     /* Copy the required tx and rx mask */
0297     i2s->tx_mask = (tx_mask > DEFAULT_I2S_SLOT_MASK) ?
0298                DEFAULT_I2S_SLOT_MASK : tx_mask;
0299     i2s->rx_mask = (rx_mask > DEFAULT_I2S_SLOT_MASK) ?
0300                DEFAULT_I2S_SLOT_MASK : rx_mask;
0301 
0302     return 0;
0303 }
0304 
0305 static int tegra210_i2s_get_loopback(struct snd_kcontrol *kcontrol,
0306                      struct snd_ctl_elem_value *ucontrol)
0307 {
0308     struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
0309     struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
0310 
0311     ucontrol->value.integer.value[0] = i2s->loopback;
0312 
0313     return 0;
0314 }
0315 
0316 static int tegra210_i2s_put_loopback(struct snd_kcontrol *kcontrol,
0317                      struct snd_ctl_elem_value *ucontrol)
0318 {
0319     struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
0320     struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
0321     int value = ucontrol->value.integer.value[0];
0322 
0323     if (value == i2s->loopback)
0324         return 0;
0325 
0326     i2s->loopback = value;
0327 
0328     regmap_update_bits(i2s->regmap, TEGRA210_I2S_CTRL, I2S_CTRL_LPBK_MASK,
0329                i2s->loopback << I2S_CTRL_LPBK_SHIFT);
0330 
0331     return 1;
0332 }
0333 
0334 static int tegra210_i2s_get_fsync_width(struct snd_kcontrol *kcontrol,
0335                     struct snd_ctl_elem_value *ucontrol)
0336 {
0337     struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
0338     struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
0339 
0340     ucontrol->value.integer.value[0] = i2s->fsync_width;
0341 
0342     return 0;
0343 }
0344 
0345 static int tegra210_i2s_put_fsync_width(struct snd_kcontrol *kcontrol,
0346                     struct snd_ctl_elem_value *ucontrol)
0347 {
0348     struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
0349     struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
0350     int value = ucontrol->value.integer.value[0];
0351 
0352     if (value == i2s->fsync_width)
0353         return 0;
0354 
0355     i2s->fsync_width = value;
0356 
0357     /*
0358      * Frame sync width is used only for FSYNC modes and not
0359      * applicable for LRCK modes. Reset value for this field is "0",
0360      * which means the width is one bit clock wide.
0361      * The width requirement may depend on the codec and in such
0362      * cases mixer control is used to update custom values. A value
0363      * of "N" here means, width is "N + 1" bit clock wide.
0364      */
0365     regmap_update_bits(i2s->regmap, TEGRA210_I2S_CTRL,
0366                I2S_CTRL_FSYNC_WIDTH_MASK,
0367                i2s->fsync_width << I2S_FSYNC_WIDTH_SHIFT);
0368 
0369     return 1;
0370 }
0371 
0372 static int tegra210_i2s_cget_stereo_to_mono(struct snd_kcontrol *kcontrol,
0373                         struct snd_ctl_elem_value *ucontrol)
0374 {
0375     struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
0376     struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
0377 
0378     ucontrol->value.enumerated.item[0] = i2s->stereo_to_mono[I2S_TX_PATH];
0379 
0380     return 0;
0381 }
0382 
0383 static int tegra210_i2s_cput_stereo_to_mono(struct snd_kcontrol *kcontrol,
0384                         struct snd_ctl_elem_value *ucontrol)
0385 {
0386     struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
0387     struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
0388     unsigned int value = ucontrol->value.enumerated.item[0];
0389 
0390     if (value == i2s->stereo_to_mono[I2S_TX_PATH])
0391         return 0;
0392 
0393     i2s->stereo_to_mono[I2S_TX_PATH] = value;
0394 
0395     return 1;
0396 }
0397 
0398 static int tegra210_i2s_cget_mono_to_stereo(struct snd_kcontrol *kcontrol,
0399                         struct snd_ctl_elem_value *ucontrol)
0400 {
0401     struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
0402     struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
0403 
0404     ucontrol->value.enumerated.item[0] = i2s->mono_to_stereo[I2S_TX_PATH];
0405 
0406     return 0;
0407 }
0408 
0409 static int tegra210_i2s_cput_mono_to_stereo(struct snd_kcontrol *kcontrol,
0410                         struct snd_ctl_elem_value *ucontrol)
0411 {
0412     struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
0413     struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
0414     unsigned int value = ucontrol->value.enumerated.item[0];
0415 
0416     if (value == i2s->mono_to_stereo[I2S_TX_PATH])
0417         return 0;
0418 
0419     i2s->mono_to_stereo[I2S_TX_PATH] = value;
0420 
0421     return 1;
0422 }
0423 
0424 static int tegra210_i2s_pget_stereo_to_mono(struct snd_kcontrol *kcontrol,
0425                         struct snd_ctl_elem_value *ucontrol)
0426 {
0427     struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
0428     struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
0429 
0430     ucontrol->value.enumerated.item[0] = i2s->stereo_to_mono[I2S_RX_PATH];
0431 
0432     return 0;
0433 }
0434 
0435 static int tegra210_i2s_pput_stereo_to_mono(struct snd_kcontrol *kcontrol,
0436                         struct snd_ctl_elem_value *ucontrol)
0437 {
0438     struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
0439     struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
0440     unsigned int value = ucontrol->value.enumerated.item[0];
0441 
0442     if (value == i2s->stereo_to_mono[I2S_RX_PATH])
0443         return 0;
0444 
0445     i2s->stereo_to_mono[I2S_RX_PATH] = value;
0446 
0447     return 1;
0448 }
0449 
0450 static int tegra210_i2s_pget_mono_to_stereo(struct snd_kcontrol *kcontrol,
0451                         struct snd_ctl_elem_value *ucontrol)
0452 {
0453     struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
0454     struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
0455 
0456     ucontrol->value.enumerated.item[0] = i2s->mono_to_stereo[I2S_RX_PATH];
0457 
0458     return 0;
0459 }
0460 
0461 static int tegra210_i2s_pput_mono_to_stereo(struct snd_kcontrol *kcontrol,
0462                         struct snd_ctl_elem_value *ucontrol)
0463 {
0464     struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
0465     struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
0466     unsigned int value = ucontrol->value.enumerated.item[0];
0467 
0468     if (value == i2s->mono_to_stereo[I2S_RX_PATH])
0469         return 0;
0470 
0471     i2s->mono_to_stereo[I2S_RX_PATH] = value;
0472 
0473     return 1;
0474 }
0475 
0476 static int tegra210_i2s_pget_fifo_th(struct snd_kcontrol *kcontrol,
0477                      struct snd_ctl_elem_value *ucontrol)
0478 {
0479     struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
0480     struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
0481 
0482     ucontrol->value.integer.value[0] = i2s->rx_fifo_th;
0483 
0484     return 0;
0485 }
0486 
0487 static int tegra210_i2s_pput_fifo_th(struct snd_kcontrol *kcontrol,
0488                      struct snd_ctl_elem_value *ucontrol)
0489 {
0490     struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
0491     struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
0492     int value = ucontrol->value.integer.value[0];
0493 
0494     if (value == i2s->rx_fifo_th)
0495         return 0;
0496 
0497     i2s->rx_fifo_th = value;
0498 
0499     return 1;
0500 }
0501 
0502 static int tegra210_i2s_get_bclk_ratio(struct snd_kcontrol *kcontrol,
0503                        struct snd_ctl_elem_value *ucontrol)
0504 {
0505     struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
0506     struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
0507 
0508     ucontrol->value.integer.value[0] = i2s->bclk_ratio;
0509 
0510     return 0;
0511 }
0512 
0513 static int tegra210_i2s_put_bclk_ratio(struct snd_kcontrol *kcontrol,
0514                        struct snd_ctl_elem_value *ucontrol)
0515 {
0516     struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
0517     struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
0518     int value = ucontrol->value.integer.value[0];
0519 
0520     if (value == i2s->bclk_ratio)
0521         return 0;
0522 
0523     i2s->bclk_ratio = value;
0524 
0525     return 1;
0526 }
0527 
0528 static int tegra210_i2s_set_dai_bclk_ratio(struct snd_soc_dai *dai,
0529                        unsigned int ratio)
0530 {
0531     struct tegra210_i2s *i2s = snd_soc_dai_get_drvdata(dai);
0532 
0533     i2s->bclk_ratio = ratio;
0534 
0535     return 0;
0536 }
0537 
0538 static int tegra210_i2s_set_timing_params(struct device *dev,
0539                       unsigned int sample_size,
0540                       unsigned int srate,
0541                       unsigned int channels)
0542 {
0543     struct tegra210_i2s *i2s = dev_get_drvdata(dev);
0544     unsigned int val, bit_count, bclk_rate, num_bclk = sample_size;
0545     int err;
0546 
0547     if (i2s->bclk_ratio)
0548         num_bclk *= i2s->bclk_ratio;
0549 
0550     if (i2s->dai_fmt == SND_SOC_DAIFMT_RIGHT_J)
0551         tegra210_i2s_set_data_offset(i2s, num_bclk - sample_size);
0552 
0553     /* I2S bit clock rate */
0554     bclk_rate = srate * channels * num_bclk;
0555 
0556     err = tegra210_i2s_set_clock_rate(dev, bclk_rate);
0557     if (err) {
0558         dev_err(dev, "can't set I2S bit clock rate %u, err: %d\n",
0559             bclk_rate, err);
0560         return err;
0561     }
0562 
0563     regmap_read(i2s->regmap, TEGRA210_I2S_CTRL, &val);
0564 
0565     /*
0566      * For LRCK mode, channel bit count depends on number of bit clocks
0567      * on the left channel, where as for FSYNC mode bit count depends on
0568      * the number of bit clocks in both left and right channels for DSP
0569      * mode or the number of bit clocks in one TDM frame.
0570      *
0571      */
0572     switch (val & I2S_CTRL_FRAME_FMT_MASK) {
0573     case I2S_CTRL_FRAME_FMT_LRCK_MODE:
0574         bit_count = (bclk_rate / (srate * 2)) - 1;
0575         break;
0576     case I2S_CTRL_FRAME_FMT_FSYNC_MODE:
0577         bit_count = (bclk_rate / srate) - 1;
0578 
0579         tegra210_i2s_set_slot_ctrl(i2s->regmap, channels,
0580                        i2s->tx_mask, i2s->rx_mask);
0581         break;
0582     default:
0583         dev_err(dev, "invalid I2S frame format\n");
0584         return -EINVAL;
0585     }
0586 
0587     if (bit_count > I2S_TIMING_CH_BIT_CNT_MASK) {
0588         dev_err(dev, "invalid I2S channel bit count %u\n", bit_count);
0589         return -EINVAL;
0590     }
0591 
0592     regmap_write(i2s->regmap, TEGRA210_I2S_TIMING,
0593              bit_count << I2S_TIMING_CH_BIT_CNT_SHIFT);
0594 
0595     return 0;
0596 }
0597 
0598 static int tegra210_i2s_hw_params(struct snd_pcm_substream *substream,
0599                   struct snd_pcm_hw_params *params,
0600                   struct snd_soc_dai *dai)
0601 {
0602     struct device *dev = dai->dev;
0603     struct tegra210_i2s *i2s = snd_soc_dai_get_drvdata(dai);
0604     unsigned int sample_size, channels, srate, val, reg, path;
0605     struct tegra_cif_conf cif_conf;
0606 
0607     memset(&cif_conf, 0, sizeof(struct tegra_cif_conf));
0608 
0609     channels = params_channels(params);
0610     if (channels < 1) {
0611         dev_err(dev, "invalid I2S %d channel configuration\n",
0612             channels);
0613         return -EINVAL;
0614     }
0615 
0616     cif_conf.audio_ch = channels;
0617     cif_conf.client_ch = channels;
0618 
0619     switch (params_format(params)) {
0620     case SNDRV_PCM_FORMAT_S8:
0621         val = I2S_BITS_8;
0622         sample_size = 8;
0623         cif_conf.audio_bits = TEGRA_ACIF_BITS_8;
0624         cif_conf.client_bits = TEGRA_ACIF_BITS_8;
0625         break;
0626     case SNDRV_PCM_FORMAT_S16_LE:
0627         val = I2S_BITS_16;
0628         sample_size = 16;
0629         cif_conf.audio_bits = TEGRA_ACIF_BITS_16;
0630         cif_conf.client_bits = TEGRA_ACIF_BITS_16;
0631         break;
0632     case SNDRV_PCM_FORMAT_S32_LE:
0633         val = I2S_BITS_32;
0634         sample_size = 32;
0635         cif_conf.audio_bits = TEGRA_ACIF_BITS_32;
0636         cif_conf.client_bits = TEGRA_ACIF_BITS_32;
0637         break;
0638     default:
0639         dev_err(dev, "unsupported format!\n");
0640         return -EOPNOTSUPP;
0641     }
0642 
0643     /* Program sample size */
0644     regmap_update_bits(i2s->regmap, TEGRA210_I2S_CTRL,
0645                I2S_CTRL_BIT_SIZE_MASK, val);
0646 
0647     srate = params_rate(params);
0648 
0649     /* For playback I2S RX-CIF and for capture TX-CIF is used */
0650     if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
0651         path = I2S_RX_PATH;
0652     else
0653         path = I2S_TX_PATH;
0654 
0655     if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
0656         unsigned int max_th;
0657 
0658         /* FIFO threshold in terms of frames */
0659         max_th = (I2S_RX_FIFO_DEPTH / cif_conf.audio_ch) - 1;
0660 
0661         if (i2s->rx_fifo_th > max_th)
0662             i2s->rx_fifo_th = max_th;
0663 
0664         cif_conf.threshold = i2s->rx_fifo_th;
0665 
0666         reg = TEGRA210_I2S_RX_CIF_CTRL;
0667     } else {
0668         reg = TEGRA210_I2S_TX_CIF_CTRL;
0669     }
0670 
0671     cif_conf.mono_conv = i2s->mono_to_stereo[path];
0672     cif_conf.stereo_conv = i2s->stereo_to_mono[path];
0673 
0674     tegra_set_cif(i2s->regmap, reg, &cif_conf);
0675 
0676     return tegra210_i2s_set_timing_params(dev, sample_size, srate,
0677                           cif_conf.client_ch);
0678 }
0679 
0680 static const struct snd_soc_dai_ops tegra210_i2s_dai_ops = {
0681     .set_fmt    = tegra210_i2s_set_fmt,
0682     .hw_params  = tegra210_i2s_hw_params,
0683     .set_bclk_ratio = tegra210_i2s_set_dai_bclk_ratio,
0684     .set_tdm_slot   = tegra210_i2s_set_tdm_slot,
0685 };
0686 
0687 static struct snd_soc_dai_driver tegra210_i2s_dais[] = {
0688     {
0689         .name = "I2S-CIF",
0690         .playback = {
0691             .stream_name = "CIF-Playback",
0692             .channels_min = 1,
0693             .channels_max = 16,
0694             .rates = SNDRV_PCM_RATE_8000_192000,
0695             .formats = SNDRV_PCM_FMTBIT_S8 |
0696                 SNDRV_PCM_FMTBIT_S16_LE |
0697                 SNDRV_PCM_FMTBIT_S32_LE,
0698         },
0699         .capture = {
0700             .stream_name = "CIF-Capture",
0701             .channels_min = 1,
0702             .channels_max = 16,
0703             .rates = SNDRV_PCM_RATE_8000_192000,
0704             .formats = SNDRV_PCM_FMTBIT_S8 |
0705                 SNDRV_PCM_FMTBIT_S16_LE |
0706                 SNDRV_PCM_FMTBIT_S32_LE,
0707         },
0708     },
0709     {
0710         .name = "I2S-DAP",
0711         .playback = {
0712             .stream_name = "DAP-Playback",
0713             .channels_min = 1,
0714             .channels_max = 16,
0715             .rates = SNDRV_PCM_RATE_8000_192000,
0716             .formats = SNDRV_PCM_FMTBIT_S8 |
0717                 SNDRV_PCM_FMTBIT_S16_LE |
0718                 SNDRV_PCM_FMTBIT_S32_LE,
0719         },
0720         .capture = {
0721             .stream_name = "DAP-Capture",
0722             .channels_min = 1,
0723             .channels_max = 16,
0724             .rates = SNDRV_PCM_RATE_8000_192000,
0725             .formats = SNDRV_PCM_FMTBIT_S8 |
0726                 SNDRV_PCM_FMTBIT_S16_LE |
0727                 SNDRV_PCM_FMTBIT_S32_LE,
0728         },
0729         .ops = &tegra210_i2s_dai_ops,
0730         .symmetric_rate = 1,
0731     },
0732 };
0733 
0734 static const char * const tegra210_i2s_stereo_conv_text[] = {
0735     "CH0", "CH1", "AVG",
0736 };
0737 
0738 static const char * const tegra210_i2s_mono_conv_text[] = {
0739     "Zero", "Copy",
0740 };
0741 
0742 static const struct soc_enum tegra210_i2s_mono_conv_enum =
0743     SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(tegra210_i2s_mono_conv_text),
0744             tegra210_i2s_mono_conv_text);
0745 
0746 static const struct soc_enum tegra210_i2s_stereo_conv_enum =
0747     SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(tegra210_i2s_stereo_conv_text),
0748             tegra210_i2s_stereo_conv_text);
0749 
0750 static const struct snd_kcontrol_new tegra210_i2s_controls[] = {
0751     SOC_SINGLE_EXT("Loopback", 0, 0, 1, 0, tegra210_i2s_get_loopback,
0752                tegra210_i2s_put_loopback),
0753     SOC_SINGLE_EXT("FSYNC Width", 0, 0, 255, 0,
0754                tegra210_i2s_get_fsync_width,
0755                tegra210_i2s_put_fsync_width),
0756     SOC_ENUM_EXT("Capture Stereo To Mono", tegra210_i2s_stereo_conv_enum,
0757              tegra210_i2s_cget_stereo_to_mono,
0758              tegra210_i2s_cput_stereo_to_mono),
0759     SOC_ENUM_EXT("Capture Mono To Stereo", tegra210_i2s_mono_conv_enum,
0760              tegra210_i2s_cget_mono_to_stereo,
0761              tegra210_i2s_cput_mono_to_stereo),
0762     SOC_ENUM_EXT("Playback Stereo To Mono", tegra210_i2s_stereo_conv_enum,
0763              tegra210_i2s_pget_mono_to_stereo,
0764              tegra210_i2s_pput_mono_to_stereo),
0765     SOC_ENUM_EXT("Playback Mono To Stereo", tegra210_i2s_mono_conv_enum,
0766              tegra210_i2s_pget_stereo_to_mono,
0767              tegra210_i2s_pput_stereo_to_mono),
0768     SOC_SINGLE_EXT("Playback FIFO Threshold", 0, 0, I2S_RX_FIFO_DEPTH - 1,
0769                0, tegra210_i2s_pget_fifo_th, tegra210_i2s_pput_fifo_th),
0770     SOC_SINGLE_EXT("BCLK Ratio", 0, 0, INT_MAX, 0,
0771                tegra210_i2s_get_bclk_ratio,
0772                tegra210_i2s_put_bclk_ratio),
0773 };
0774 
0775 static const struct snd_soc_dapm_widget tegra210_i2s_widgets[] = {
0776     SND_SOC_DAPM_AIF_IN_E("RX", NULL, 0, TEGRA210_I2S_RX_ENABLE,
0777                   0, 0, tegra210_i2s_init, SND_SOC_DAPM_PRE_PMU),
0778     SND_SOC_DAPM_AIF_OUT_E("TX", NULL, 0, TEGRA210_I2S_TX_ENABLE,
0779                    0, 0, tegra210_i2s_init, SND_SOC_DAPM_PRE_PMU),
0780     SND_SOC_DAPM_MIC("MIC", NULL),
0781     SND_SOC_DAPM_SPK("SPK", NULL),
0782 };
0783 
0784 static const struct snd_soc_dapm_route tegra210_i2s_routes[] = {
0785     /* Playback route from XBAR */
0786     { "XBAR-Playback",  NULL,   "XBAR-TX" },
0787     { "CIF-Playback",   NULL,   "XBAR-Playback" },
0788     { "RX",         NULL,   "CIF-Playback" },
0789     { "DAP-Playback",   NULL,   "RX" },
0790     { "SPK",        NULL,   "DAP-Playback" },
0791     /* Capture route to XBAR */
0792     { "XBAR-RX",        NULL,   "XBAR-Capture" },
0793     { "XBAR-Capture",   NULL,   "CIF-Capture" },
0794     { "CIF-Capture",    NULL,   "TX" },
0795     { "TX",         NULL,   "DAP-Capture" },
0796     { "DAP-Capture",    NULL,   "MIC" },
0797 };
0798 
0799 static const struct snd_soc_component_driver tegra210_i2s_cmpnt = {
0800     .dapm_widgets       = tegra210_i2s_widgets,
0801     .num_dapm_widgets   = ARRAY_SIZE(tegra210_i2s_widgets),
0802     .dapm_routes        = tegra210_i2s_routes,
0803     .num_dapm_routes    = ARRAY_SIZE(tegra210_i2s_routes),
0804     .controls       = tegra210_i2s_controls,
0805     .num_controls       = ARRAY_SIZE(tegra210_i2s_controls),
0806 };
0807 
0808 static bool tegra210_i2s_wr_reg(struct device *dev, unsigned int reg)
0809 {
0810     switch (reg) {
0811     case TEGRA210_I2S_RX_ENABLE ... TEGRA210_I2S_RX_SOFT_RESET:
0812     case TEGRA210_I2S_RX_INT_MASK ... TEGRA210_I2S_RX_CLK_TRIM:
0813     case TEGRA210_I2S_TX_ENABLE ... TEGRA210_I2S_TX_SOFT_RESET:
0814     case TEGRA210_I2S_TX_INT_MASK ... TEGRA210_I2S_TX_CLK_TRIM:
0815     case TEGRA210_I2S_ENABLE ... TEGRA210_I2S_CG:
0816     case TEGRA210_I2S_CTRL ... TEGRA210_I2S_CYA:
0817         return true;
0818     default:
0819         return false;
0820     }
0821 }
0822 
0823 static bool tegra210_i2s_rd_reg(struct device *dev, unsigned int reg)
0824 {
0825     if (tegra210_i2s_wr_reg(dev, reg))
0826         return true;
0827 
0828     switch (reg) {
0829     case TEGRA210_I2S_RX_STATUS:
0830     case TEGRA210_I2S_RX_INT_STATUS:
0831     case TEGRA210_I2S_RX_CIF_FIFO_STATUS:
0832     case TEGRA210_I2S_TX_STATUS:
0833     case TEGRA210_I2S_TX_INT_STATUS:
0834     case TEGRA210_I2S_TX_CIF_FIFO_STATUS:
0835     case TEGRA210_I2S_STATUS:
0836     case TEGRA210_I2S_INT_STATUS:
0837         return true;
0838     default:
0839         return false;
0840     }
0841 }
0842 
0843 static bool tegra210_i2s_volatile_reg(struct device *dev, unsigned int reg)
0844 {
0845     switch (reg) {
0846     case TEGRA210_I2S_RX_STATUS:
0847     case TEGRA210_I2S_RX_INT_STATUS:
0848     case TEGRA210_I2S_RX_CIF_FIFO_STATUS:
0849     case TEGRA210_I2S_TX_STATUS:
0850     case TEGRA210_I2S_TX_INT_STATUS:
0851     case TEGRA210_I2S_TX_CIF_FIFO_STATUS:
0852     case TEGRA210_I2S_STATUS:
0853     case TEGRA210_I2S_INT_STATUS:
0854     case TEGRA210_I2S_RX_SOFT_RESET:
0855     case TEGRA210_I2S_TX_SOFT_RESET:
0856         return true;
0857     default:
0858         return false;
0859     }
0860 }
0861 
0862 static const struct regmap_config tegra210_i2s_regmap_config = {
0863     .reg_bits       = 32,
0864     .reg_stride     = 4,
0865     .val_bits       = 32,
0866     .max_register       = TEGRA210_I2S_CYA,
0867     .writeable_reg      = tegra210_i2s_wr_reg,
0868     .readable_reg       = tegra210_i2s_rd_reg,
0869     .volatile_reg       = tegra210_i2s_volatile_reg,
0870     .reg_defaults       = tegra210_i2s_reg_defaults,
0871     .num_reg_defaults   = ARRAY_SIZE(tegra210_i2s_reg_defaults),
0872     .cache_type     = REGCACHE_FLAT,
0873 };
0874 
0875 static int tegra210_i2s_probe(struct platform_device *pdev)
0876 {
0877     struct device *dev = &pdev->dev;
0878     struct tegra210_i2s *i2s;
0879     void __iomem *regs;
0880     int err;
0881 
0882     i2s = devm_kzalloc(dev, sizeof(*i2s), GFP_KERNEL);
0883     if (!i2s)
0884         return -ENOMEM;
0885 
0886     i2s->rx_fifo_th = DEFAULT_I2S_RX_FIFO_THRESHOLD;
0887     i2s->tx_mask = DEFAULT_I2S_SLOT_MASK;
0888     i2s->rx_mask = DEFAULT_I2S_SLOT_MASK;
0889     i2s->loopback = false;
0890 
0891     dev_set_drvdata(dev, i2s);
0892 
0893     i2s->clk_i2s = devm_clk_get(dev, "i2s");
0894     if (IS_ERR(i2s->clk_i2s)) {
0895         dev_err(dev, "can't retrieve I2S bit clock\n");
0896         return PTR_ERR(i2s->clk_i2s);
0897     }
0898 
0899     /*
0900      * Not an error, as this clock is needed only when some other I/O
0901      * requires input clock from current I2S instance, which is
0902      * configurable from DT.
0903      */
0904     i2s->clk_sync_input = devm_clk_get(dev, "sync_input");
0905     if (IS_ERR(i2s->clk_sync_input))
0906         dev_dbg(dev, "can't retrieve I2S sync input clock\n");
0907 
0908     regs = devm_platform_ioremap_resource(pdev, 0);
0909     if (IS_ERR(regs))
0910         return PTR_ERR(regs);
0911 
0912     i2s->regmap = devm_regmap_init_mmio(dev, regs,
0913                         &tegra210_i2s_regmap_config);
0914     if (IS_ERR(i2s->regmap)) {
0915         dev_err(dev, "regmap init failed\n");
0916         return PTR_ERR(i2s->regmap);
0917     }
0918 
0919     regcache_cache_only(i2s->regmap, true);
0920 
0921     err = devm_snd_soc_register_component(dev, &tegra210_i2s_cmpnt,
0922                           tegra210_i2s_dais,
0923                           ARRAY_SIZE(tegra210_i2s_dais));
0924     if (err) {
0925         dev_err(dev, "can't register I2S component, err: %d\n", err);
0926         return err;
0927     }
0928 
0929     pm_runtime_enable(dev);
0930 
0931     return 0;
0932 }
0933 
0934 static int tegra210_i2s_remove(struct platform_device *pdev)
0935 {
0936     pm_runtime_disable(&pdev->dev);
0937 
0938     return 0;
0939 }
0940 
0941 static const struct dev_pm_ops tegra210_i2s_pm_ops = {
0942     SET_RUNTIME_PM_OPS(tegra210_i2s_runtime_suspend,
0943                tegra210_i2s_runtime_resume, NULL)
0944     SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
0945                 pm_runtime_force_resume)
0946 };
0947 
0948 static const struct of_device_id tegra210_i2s_of_match[] = {
0949     { .compatible = "nvidia,tegra210-i2s" },
0950     {},
0951 };
0952 MODULE_DEVICE_TABLE(of, tegra210_i2s_of_match);
0953 
0954 static struct platform_driver tegra210_i2s_driver = {
0955     .driver = {
0956         .name = "tegra210-i2s",
0957         .of_match_table = tegra210_i2s_of_match,
0958         .pm = &tegra210_i2s_pm_ops,
0959     },
0960     .probe = tegra210_i2s_probe,
0961     .remove = tegra210_i2s_remove,
0962 };
0963 module_platform_driver(tegra210_i2s_driver)
0964 
0965 MODULE_AUTHOR("Songhee Baek <sbaek@nvidia.com>");
0966 MODULE_DESCRIPTION("Tegra210 ASoC I2S driver");
0967 MODULE_LICENSE("GPL v2");
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