soc/tegra/tegra210_dmic.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * tegra210_dmic.h - Definitions for Tegra210 DMIC driver
0004  *
0005  * Copyright (c) 2020 NVIDIA CORPORATION.  All rights reserved.
0006  *
0007  */
0008
0009 #ifndef __TEGRA210_DMIC_H__
0010 #define __TEGRA210_DMIC_H__
0011
0012 /* Register offsets from DMIC BASE */
0013 #define TEGRA210_DMIC_TX_STATUS             0x0c
0014 #define TEGRA210_DMIC_TX_INT_STATUS         0x10
0015 #define TEGRA210_DMIC_TX_INT_MASK           0x14
0016 #define TEGRA210_DMIC_TX_INT_SET            0x18
0017 #define TEGRA210_DMIC_TX_INT_CLEAR          0x1c
0018 #define TEGRA210_DMIC_TX_CIF_CTRL           0x20
0019 #define TEGRA210_DMIC_ENABLE                0x40
0020 #define TEGRA210_DMIC_SOFT_RESET            0x44
0021 #define TEGRA210_DMIC_CG                0x48
0022 #define TEGRA210_DMIC_STATUS                0x4c
0023 #define TEGRA210_DMIC_INT_STATUS            0x50
0024 #define TEGRA210_DMIC_CTRL              0x64
0025 #define TEGRA210_DMIC_DBG_CTRL              0x70
0026 #define TEGRA210_DMIC_DCR_BIQUAD_0_COEF_4       0x88
0027 #define TEGRA210_DMIC_LP_FILTER_GAIN            0x8c
0028 #define TEGRA210_DMIC_LP_BIQUAD_0_COEF_0        0x90
0029 #define TEGRA210_DMIC_LP_BIQUAD_0_COEF_1        0x94
0030 #define TEGRA210_DMIC_LP_BIQUAD_0_COEF_2        0x98
0031 #define TEGRA210_DMIC_LP_BIQUAD_0_COEF_3        0x9c
0032 #define TEGRA210_DMIC_LP_BIQUAD_0_COEF_4        0xa0
0033 #define TEGRA210_DMIC_LP_BIQUAD_1_COEF_0        0xa4
0034 #define TEGRA210_DMIC_LP_BIQUAD_1_COEF_1        0xa8
0035 #define TEGRA210_DMIC_LP_BIQUAD_1_COEF_2        0xac
0036 #define TEGRA210_DMIC_LP_BIQUAD_1_COEF_3        0xb0
0037 #define TEGRA210_DMIC_LP_BIQUAD_1_COEF_4        0xb4
0038
0039 /* Fields in TEGRA210_DMIC_CTRL */
0040 #define CH_SEL_SHIFT                    8
0041 #define TEGRA210_DMIC_CTRL_CHANNEL_SELECT_MASK      (0x3 << CH_SEL_SHIFT)
0042 #define LRSEL_POL_SHIFT                 4
0043 #define TEGRA210_DMIC_CTRL_LRSEL_POLARITY_MASK      (0x1 << LRSEL_POL_SHIFT)
0044 #define OSR_SHIFT                   0
0045 #define TEGRA210_DMIC_CTRL_OSR_MASK         (0x3 << OSR_SHIFT)
0046
0047 #define DMIC_OSR_FACTOR                 64
0048
0049 #define DEFAULT_GAIN_Q23                0x800000
0050
0051 /* Max boost gain factor used for mixer control */
0052 #define MAX_BOOST_GAIN 25599
0053
0054 enum tegra_dmic_ch_select {
0055     DMIC_CH_SELECT_LEFT,
0056     DMIC_CH_SELECT_RIGHT,
0057     DMIC_CH_SELECT_STEREO,
0058 };
0059
0060 enum tegra_dmic_osr {
0061     DMIC_OSR_64,
0062     DMIC_OSR_128,
0063     DMIC_OSR_256,
0064 };
0065
0066 enum tegra_dmic_lrsel {
0067     DMIC_LRSEL_LEFT,
0068     DMIC_LRSEL_RIGHT,
0069 };
0070
0071 struct tegra210_dmic {
0072     struct clk *clk_dmic;
0073     struct regmap *regmap;
0074     unsigned int mono_to_stereo;
0075     unsigned int stereo_to_mono;
0076     unsigned int boost_gain;
0077     unsigned int ch_select;
0078     unsigned int osr_val;
0079     unsigned int lrsel;
0080 };
0081
0082 #endif