soc/tegra/tegra210_amx.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * tegra210_amx.h - Definitions for Tegra210 AMX driver
0004  *
0005  * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
0006  *
0007  */
0008
0009 #ifndef __TEGRA210_AMX_H__
0010 #define __TEGRA210_AMX_H__
0011
0012 /* Register offsets from TEGRA210_AMX*_BASE */
0013 #define TEGRA210_AMX_RX_STATUS          0x0c
0014 #define TEGRA210_AMX_RX_INT_STATUS      0x10
0015 #define TEGRA210_AMX_RX_INT_MASK        0x14
0016 #define TEGRA210_AMX_RX_INT_SET         0x18
0017 #define TEGRA210_AMX_RX_INT_CLEAR       0x1c
0018 #define TEGRA210_AMX_RX1_CIF_CTRL       0x20
0019 #define TEGRA210_AMX_RX2_CIF_CTRL       0x24
0020 #define TEGRA210_AMX_RX3_CIF_CTRL       0x28
0021 #define TEGRA210_AMX_RX4_CIF_CTRL       0x2c
0022 #define TEGRA210_AMX_TX_STATUS          0x4c
0023 #define TEGRA210_AMX_TX_INT_STATUS      0x50
0024 #define TEGRA210_AMX_TX_INT_MASK        0x54
0025 #define TEGRA210_AMX_TX_INT_SET         0x58
0026 #define TEGRA210_AMX_TX_INT_CLEAR       0x5c
0027 #define TEGRA210_AMX_TX_CIF_CTRL        0x60
0028 #define TEGRA210_AMX_ENABLE         0x80
0029 #define TEGRA210_AMX_SOFT_RESET         0x84
0030 #define TEGRA210_AMX_CG             0x88
0031 #define TEGRA210_AMX_STATUS         0x8c
0032 #define TEGRA210_AMX_INT_STATUS         0x90
0033 #define TEGRA210_AMX_CTRL           0xa4
0034 #define TEGRA210_AMX_OUT_BYTE_EN0       0xa8
0035 #define TEGRA210_AMX_OUT_BYTE_EN1       0xac
0036 #define TEGRA210_AMX_CYA            0xb0
0037 #define TEGRA210_AMX_CFG_RAM_CTRL       0xb8
0038 #define TEGRA210_AMX_CFG_RAM_DATA       0xbc
0039
0040 #define TEGRA194_AMX_RX1_FRAME_PERIOD       0xc0
0041 #define TEGRA194_AMX_RX4_FRAME_PERIOD       0xcc
0042 #define TEGRA194_AMX_RX4_LAST_FRAME_PERIOD  0xdc
0043
0044 /* Fields in TEGRA210_AMX_ENABLE */
0045 #define TEGRA210_AMX_ENABLE_SHIFT           0
0046
0047 /* Fields in TEGRA210_AMX_CTRL */
0048 #define TEGRA210_AMX_CTRL_MSTR_RX_NUM_SHIFT     14
0049 #define TEGRA210_AMX_CTRL_MSTR_RX_NUM_MASK      (3 << TEGRA210_AMX_CTRL_MSTR_RX_NUM_SHIFT)
0050
0051 #define TEGRA210_AMX_CTRL_RX_DEP_SHIFT          12
0052 #define TEGRA210_AMX_CTRL_RX_DEP_MASK           (3 << TEGRA210_AMX_CTRL_RX_DEP_SHIFT)
0053
0054 /* Fields in TEGRA210_AMX_CFG_RAM_CTRL */
0055 #define TEGRA210_AMX_CFG_RAM_CTRL_RW_SHIFT      14
0056 #define TEGRA210_AMX_CFG_RAM_CTRL_RW_WRITE      (1 << TEGRA210_AMX_CFG_RAM_CTRL_RW_SHIFT)
0057
0058 #define TEGRA210_AMX_CFG_RAM_CTRL_ADDR_INIT_EN_SHIFT    13
0059 #define TEGRA210_AMX_CFG_RAM_CTRL_ADDR_INIT_EN      (1 << TEGRA210_AMX_CFG_RAM_CTRL_ADDR_INIT_EN_SHIFT)
0060
0061 #define TEGRA210_AMX_CFG_RAM_CTRL_SEQ_ACCESS_EN_SHIFT   12
0062 #define TEGRA210_AMX_CFG_RAM_CTRL_SEQ_ACCESS_EN     (1 << TEGRA210_AMX_CFG_RAM_CTRL_SEQ_ACCESS_EN_SHIFT)
0063
0064 #define TEGRA210_AMX_CFG_CTRL_RAM_ADDR_SHIFT        0
0065
0066 /* Fields in TEGRA210_AMX_SOFT_RESET */
0067 #define TEGRA210_AMX_SOFT_RESET_SOFT_EN         1
0068 #define TEGRA210_AMX_SOFT_RESET_SOFT_RESET_MASK     TEGRA210_AMX_SOFT_RESET_SOFT_EN
0069
0070 #define TEGRA210_AMX_AUDIOCIF_CH_STRIDE     4
0071 #define TEGRA210_AMX_RAM_DEPTH          16
0072 #define TEGRA210_AMX_MAP_STREAM_NUM_SHIFT   6
0073 #define TEGRA210_AMX_MAP_WORD_NUM_SHIFT     2
0074 #define TEGRA210_AMX_MAP_BYTE_NUM_SHIFT     0
0075
0076 enum {
0077     TEGRA210_AMX_WAIT_ON_ALL,
0078     TEGRA210_AMX_WAIT_ON_ANY,
0079 };
0080
0081 struct tegra210_amx_soc_data {
0082     const struct regmap_config *regmap_conf;
0083     bool auto_disable;
0084 };
0085
0086 struct tegra210_amx {
0087     const struct tegra210_amx_soc_data *soc_data;
0088     unsigned int map[TEGRA210_AMX_RAM_DEPTH];
0089     struct regmap *regmap;
0090     unsigned int byte_mask[2];
0091 };
0092
0093 #endif