soc/tegra/tegra210_ahub.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * tegra210_ahub.h - TEGRA210 AHUB
0004  *
0005  * Copyright (c) 2020-2022, NVIDIA CORPORATION.  All rights reserved.
0006  *
0007  */
0008
0009 #ifndef __TEGRA210_AHUB__H__
0010 #define __TEGRA210_AHUB__H__
0011
0012 /* Tegra210 specific */
0013 #define TEGRA210_XBAR_PART1_RX              0x200
0014 #define TEGRA210_XBAR_PART2_RX              0x400
0015 #define TEGRA210_XBAR_RX_STRIDE             0x4
0016 #define TEGRA210_XBAR_AUDIO_RX_COUNT            90
0017 #define TEGRA210_XBAR_REG_MASK_0            0xf1f03ff
0018 #define TEGRA210_XBAR_REG_MASK_1            0x3f30031f
0019 #define TEGRA210_XBAR_REG_MASK_2            0xff1cf313
0020 #define TEGRA210_XBAR_REG_MASK_3            0x0
0021 #define TEGRA210_XBAR_UPDATE_MAX_REG            3
0022 /* Tegra186 specific */
0023 #define TEGRA186_XBAR_PART3_RX              0x600
0024 #define TEGRA186_XBAR_AUDIO_RX_COUNT            115
0025 #define TEGRA186_XBAR_REG_MASK_0            0xf3fffff
0026 #define TEGRA186_XBAR_REG_MASK_1            0x3f310f1f
0027 #define TEGRA186_XBAR_REG_MASK_2            0xff3cf311
0028 #define TEGRA186_XBAR_REG_MASK_3            0x3f0f00ff
0029 #define TEGRA186_XBAR_UPDATE_MAX_REG            4
0030
0031 #define TEGRA_XBAR_UPDATE_MAX_REG (TEGRA186_XBAR_UPDATE_MAX_REG)
0032
0033 #define TEGRA186_MAX_REGISTER_ADDR (TEGRA186_XBAR_PART3_RX +        \
0034     (TEGRA210_XBAR_RX_STRIDE * (TEGRA186_XBAR_AUDIO_RX_COUNT - 1)))
0035
0036 #define TEGRA210_MAX_REGISTER_ADDR (TEGRA210_XBAR_PART2_RX +        \
0037     (TEGRA210_XBAR_RX_STRIDE * (TEGRA210_XBAR_AUDIO_RX_COUNT - 1)))
0038
0039 #define MUX_REG(id) (TEGRA210_XBAR_RX_STRIDE * (id))
0040
0041 #define MUX_VALUE(npart, nbit) (1 + (nbit) + (npart) * 32)
0042
0043 #define SOC_VALUE_ENUM_WIDE(xreg, shift, xmax, xtexts, xvalues)     \
0044     {                               \
0045         .reg = xreg,                        \
0046         .shift_l = shift,                   \
0047         .shift_r = shift,                   \
0048         .items = xmax,                      \
0049         .texts = xtexts,                    \
0050         .values = xvalues,                  \
0051         .mask = xmax ? roundup_pow_of_two(xmax) - 1 : 0     \
0052     }
0053
0054 #define SOC_VALUE_ENUM_WIDE_DECL(name, xreg, shift, xtexts, xvalues)    \
0055     static struct soc_enum name =                   \
0056         SOC_VALUE_ENUM_WIDE(xreg, shift, ARRAY_SIZE(xtexts),    \
0057                     xtexts, xvalues)
0058
0059 #define MUX_ENUM_CTRL_DECL(ename, id)                   \
0060     SOC_VALUE_ENUM_WIDE_DECL(ename##_enum, MUX_REG(id), 0,      \
0061                  tegra210_ahub_mux_texts,       \
0062                  tegra210_ahub_mux_values);     \
0063     static const struct snd_kcontrol_new ename##_control =      \
0064         SOC_DAPM_ENUM_EXT("Route", ename##_enum,        \
0065                   tegra_ahub_get_value_enum,        \
0066                   tegra_ahub_put_value_enum)
0067
0068 #define MUX_ENUM_CTRL_DECL_186(ename, id)               \
0069     SOC_VALUE_ENUM_WIDE_DECL(ename##_enum, MUX_REG(id), 0,      \
0070                  tegra186_ahub_mux_texts,       \
0071                  tegra186_ahub_mux_values);     \
0072     static const struct snd_kcontrol_new ename##_control =      \
0073         SOC_DAPM_ENUM_EXT("Route", ename##_enum,        \
0074                   tegra_ahub_get_value_enum,        \
0075                   tegra_ahub_put_value_enum)
0076
0077 #define MUX_ENUM_CTRL_DECL_234(ename, id) MUX_ENUM_CTRL_DECL_186(ename, id)
0078
0079 #define WIDGETS(sname, ename)                            \
0080     SND_SOC_DAPM_AIF_IN(sname " XBAR-RX", NULL, 0, SND_SOC_NOPM, 0, 0),  \
0081     SND_SOC_DAPM_AIF_OUT(sname " XBAR-TX", NULL, 0, SND_SOC_NOPM, 0, 0), \
0082     SND_SOC_DAPM_MUX(sname " Mux", SND_SOC_NOPM, 0, 0,           \
0083              &ename##_control)
0084
0085 #define TX_WIDGETS(sname)                           \
0086     SND_SOC_DAPM_AIF_IN(sname " XBAR-RX", NULL, 0, SND_SOC_NOPM, 0, 0), \
0087     SND_SOC_DAPM_AIF_OUT(sname " XBAR-TX", NULL, 0, SND_SOC_NOPM, 0, 0)
0088
0089 #define DAI(sname)                          \
0090     {                               \
0091         .name = "XBAR-" #sname,                 \
0092         .playback = {                       \
0093             .stream_name = #sname " XBAR-Playback",     \
0094             .channels_min = 1,              \
0095             .channels_max = 16,             \
0096             .rates = SNDRV_PCM_RATE_8000_192000,        \
0097             .formats = SNDRV_PCM_FMTBIT_S8 |        \
0098                 SNDRV_PCM_FMTBIT_S16_LE |       \
0099                 SNDRV_PCM_FMTBIT_S24_LE |       \
0100                 SNDRV_PCM_FMTBIT_S32_LE,        \
0101         },                          \
0102         .capture = {                        \
0103             .stream_name = #sname " XBAR-Capture",      \
0104             .channels_min = 1,              \
0105             .channels_max = 16,             \
0106             .rates = SNDRV_PCM_RATE_8000_192000,        \
0107             .formats = SNDRV_PCM_FMTBIT_S8 |        \
0108                 SNDRV_PCM_FMTBIT_S16_LE |       \
0109                 SNDRV_PCM_FMTBIT_S24_LE |       \
0110                 SNDRV_PCM_FMTBIT_S32_LE,        \
0111         },                          \
0112     }
0113
0114 struct tegra_ahub_soc_data {
0115     const struct regmap_config *regmap_config;
0116     const struct snd_soc_component_driver *cmpnt_drv;
0117     struct snd_soc_dai_driver *dai_drv;
0118     unsigned int mask[4];
0119     unsigned int reg_count;
0120     unsigned int num_dais;
0121 };
0122
0123 struct tegra_ahub {
0124     const struct tegra_ahub_soc_data *soc_data;
0125     struct regmap *regmap;
0126     struct clk *clk;
0127 };
0128
0129 #endif