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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 //
0003 // tegra210_ahub.c - Tegra210 AHUB driver
0004 //
0005 // Copyright (c) 2020-2022, NVIDIA CORPORATION.  All rights reserved.
0006 
0007 #include <linux/clk.h>
0008 #include <linux/device.h>
0009 #include <linux/module.h>
0010 #include <linux/of_platform.h>
0011 #include <linux/platform_device.h>
0012 #include <linux/pm_runtime.h>
0013 #include <linux/regmap.h>
0014 #include <sound/soc.h>
0015 #include "tegra210_ahub.h"
0016 
0017 static int tegra_ahub_get_value_enum(struct snd_kcontrol *kctl,
0018                      struct snd_ctl_elem_value *uctl)
0019 {
0020     struct snd_soc_component *cmpnt = snd_soc_dapm_kcontrol_component(kctl);
0021     struct tegra_ahub *ahub = snd_soc_component_get_drvdata(cmpnt);
0022     struct soc_enum *e = (struct soc_enum *)kctl->private_value;
0023     unsigned int reg, i, bit_pos = 0;
0024 
0025     /*
0026      * Find the bit position of current MUX input.
0027      * If nothing is set, position would be 0 and it corresponds to 'None'.
0028      */
0029     for (i = 0; i < ahub->soc_data->reg_count; i++) {
0030         unsigned int reg_val;
0031 
0032         reg = e->reg + (TEGRA210_XBAR_PART1_RX * i);
0033         reg_val = snd_soc_component_read(cmpnt, reg);
0034         reg_val &= ahub->soc_data->mask[i];
0035 
0036         if (reg_val) {
0037             bit_pos = ffs(reg_val) +
0038                   (8 * cmpnt->val_bytes * i);
0039             break;
0040         }
0041     }
0042 
0043     /* Find index related to the item in array *_ahub_mux_texts[] */
0044     for (i = 0; i < e->items; i++) {
0045         if (bit_pos == e->values[i]) {
0046             uctl->value.enumerated.item[0] = i;
0047             break;
0048         }
0049     }
0050 
0051     return 0;
0052 }
0053 
0054 static int tegra_ahub_put_value_enum(struct snd_kcontrol *kctl,
0055                      struct snd_ctl_elem_value *uctl)
0056 {
0057     struct snd_soc_component *cmpnt = snd_soc_dapm_kcontrol_component(kctl);
0058     struct tegra_ahub *ahub = snd_soc_component_get_drvdata(cmpnt);
0059     struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kctl);
0060     struct soc_enum *e = (struct soc_enum *)kctl->private_value;
0061     struct snd_soc_dapm_update update[TEGRA_XBAR_UPDATE_MAX_REG] = { };
0062     unsigned int *item = uctl->value.enumerated.item;
0063     unsigned int value = e->values[item[0]];
0064     unsigned int i, bit_pos, reg_idx = 0, reg_val = 0;
0065     int change = 0;
0066 
0067     if (item[0] >= e->items)
0068         return -EINVAL;
0069 
0070     if (value) {
0071         /* Get the register index and value to set */
0072         reg_idx = (value - 1) / (8 * cmpnt->val_bytes);
0073         bit_pos = (value - 1) % (8 * cmpnt->val_bytes);
0074         reg_val = BIT(bit_pos);
0075     }
0076 
0077     /*
0078      * Run through all parts of a MUX register to find the state changes.
0079      * There will be an additional update if new MUX input value is from
0080      * different part of the MUX register.
0081      */
0082     for (i = 0; i < ahub->soc_data->reg_count; i++) {
0083         update[i].reg = e->reg + (TEGRA210_XBAR_PART1_RX * i);
0084         update[i].val = (i == reg_idx) ? reg_val : 0;
0085         update[i].mask = ahub->soc_data->mask[i];
0086         update[i].kcontrol = kctl;
0087 
0088         /* Update widget power if state has changed */
0089         if (snd_soc_component_test_bits(cmpnt, update[i].reg,
0090                         update[i].mask,
0091                         update[i].val))
0092             change |= snd_soc_dapm_mux_update_power(dapm, kctl,
0093                                 item[0], e,
0094                                 &update[i]);
0095     }
0096 
0097     return change;
0098 }
0099 
0100 static struct snd_soc_dai_driver tegra210_ahub_dais[] = {
0101     DAI(ADMAIF1),
0102     DAI(ADMAIF2),
0103     DAI(ADMAIF3),
0104     DAI(ADMAIF4),
0105     DAI(ADMAIF5),
0106     DAI(ADMAIF6),
0107     DAI(ADMAIF7),
0108     DAI(ADMAIF8),
0109     DAI(ADMAIF9),
0110     DAI(ADMAIF10),
0111     /* XBAR <-> I2S <-> Codec */
0112     DAI(I2S1),
0113     DAI(I2S2),
0114     DAI(I2S3),
0115     DAI(I2S4),
0116     DAI(I2S5),
0117     /* XBAR <- DMIC <- Codec */
0118     DAI(DMIC1),
0119     DAI(DMIC2),
0120     DAI(DMIC3),
0121     /* XBAR -> SFC -> XBAR */
0122     DAI(SFC1 RX),
0123     DAI(SFC1 TX),
0124     DAI(SFC2 RX),
0125     DAI(SFC2 TX),
0126     DAI(SFC3 RX),
0127     DAI(SFC3 TX),
0128     DAI(SFC4 RX),
0129     DAI(SFC4 TX),
0130     /* XBAR -> MVC -> XBAR */
0131     DAI(MVC1 RX),
0132     DAI(MVC1 TX),
0133     DAI(MVC2 RX),
0134     DAI(MVC2 TX),
0135     /* XBAR -> AMX(4:1) -> XBAR */
0136     DAI(AMX1 RX1),
0137     DAI(AMX1 RX2),
0138     DAI(AMX1 RX3),
0139     DAI(AMX1 RX4),
0140     DAI(AMX1),
0141     DAI(AMX2 RX1),
0142     DAI(AMX2 RX2),
0143     DAI(AMX2 RX3),
0144     DAI(AMX2 RX4),
0145     DAI(AMX2),
0146     /* XBAR -> ADX(1:4) -> XBAR */
0147     DAI(ADX1),
0148     DAI(ADX1 TX1),
0149     DAI(ADX1 TX2),
0150     DAI(ADX1 TX3),
0151     DAI(ADX1 TX4),
0152     DAI(ADX2),
0153     DAI(ADX2 TX1),
0154     DAI(ADX2 TX2),
0155     DAI(ADX2 TX3),
0156     DAI(ADX2 TX4),
0157     /* XBAR -> MIXER(10:5) -> XBAR */
0158     DAI(MIXER1 RX1),
0159     DAI(MIXER1 RX2),
0160     DAI(MIXER1 RX3),
0161     DAI(MIXER1 RX4),
0162     DAI(MIXER1 RX5),
0163     DAI(MIXER1 RX6),
0164     DAI(MIXER1 RX7),
0165     DAI(MIXER1 RX8),
0166     DAI(MIXER1 RX9),
0167     DAI(MIXER1 RX10),
0168     DAI(MIXER1 TX1),
0169     DAI(MIXER1 TX2),
0170     DAI(MIXER1 TX3),
0171     DAI(MIXER1 TX4),
0172     DAI(MIXER1 TX5),
0173     /* XBAR -> OPE -> XBAR */
0174     DAI(OPE1 RX),
0175     DAI(OPE1 TX),
0176     DAI(OPE2 RX),
0177     DAI(OPE2 TX),
0178 };
0179 
0180 static struct snd_soc_dai_driver tegra186_ahub_dais[] = {
0181     DAI(ADMAIF1),
0182     DAI(ADMAIF2),
0183     DAI(ADMAIF3),
0184     DAI(ADMAIF4),
0185     DAI(ADMAIF5),
0186     DAI(ADMAIF6),
0187     DAI(ADMAIF7),
0188     DAI(ADMAIF8),
0189     DAI(ADMAIF9),
0190     DAI(ADMAIF10),
0191     DAI(ADMAIF11),
0192     DAI(ADMAIF12),
0193     DAI(ADMAIF13),
0194     DAI(ADMAIF14),
0195     DAI(ADMAIF15),
0196     DAI(ADMAIF16),
0197     DAI(ADMAIF17),
0198     DAI(ADMAIF18),
0199     DAI(ADMAIF19),
0200     DAI(ADMAIF20),
0201     /* XBAR <-> I2S <-> Codec */
0202     DAI(I2S1),
0203     DAI(I2S2),
0204     DAI(I2S3),
0205     DAI(I2S4),
0206     DAI(I2S5),
0207     DAI(I2S6),
0208     /* XBAR <- DMIC <- Codec */
0209     DAI(DMIC1),
0210     DAI(DMIC2),
0211     DAI(DMIC3),
0212     DAI(DMIC4),
0213     /* XBAR -> DSPK -> Codec */
0214     DAI(DSPK1),
0215     DAI(DSPK2),
0216     /* XBAR -> SFC -> XBAR */
0217     DAI(SFC1 RX),
0218     DAI(SFC1 TX),
0219     DAI(SFC2 RX),
0220     DAI(SFC2 TX),
0221     DAI(SFC3 RX),
0222     DAI(SFC3 TX),
0223     DAI(SFC4 RX),
0224     DAI(SFC4 TX),
0225     /* XBAR -> MVC -> XBAR */
0226     DAI(MVC1 RX),
0227     DAI(MVC1 TX),
0228     DAI(MVC2 RX),
0229     DAI(MVC2 TX),
0230     /* XBAR -> AMX(4:1) -> XBAR */
0231     DAI(AMX1 RX1),
0232     DAI(AMX1 RX2),
0233     DAI(AMX1 RX3),
0234     DAI(AMX1 RX4),
0235     DAI(AMX1),
0236     DAI(AMX2 RX1),
0237     DAI(AMX2 RX2),
0238     DAI(AMX2 RX3),
0239     DAI(AMX2 RX4),
0240     DAI(AMX2),
0241     DAI(AMX3 RX1),
0242     DAI(AMX3 RX2),
0243     DAI(AMX3 RX3),
0244     DAI(AMX3 RX4),
0245     DAI(AMX3),
0246     DAI(AMX4 RX1),
0247     DAI(AMX4 RX2),
0248     DAI(AMX4 RX3),
0249     DAI(AMX4 RX4),
0250     DAI(AMX4),
0251     /* XBAR -> ADX(1:4) -> XBAR */
0252     DAI(ADX1),
0253     DAI(ADX1 TX1),
0254     DAI(ADX1 TX2),
0255     DAI(ADX1 TX3),
0256     DAI(ADX1 TX4),
0257     DAI(ADX2),
0258     DAI(ADX2 TX1),
0259     DAI(ADX2 TX2),
0260     DAI(ADX2 TX3),
0261     DAI(ADX2 TX4),
0262     DAI(ADX3),
0263     DAI(ADX3 TX1),
0264     DAI(ADX3 TX2),
0265     DAI(ADX3 TX3),
0266     DAI(ADX3 TX4),
0267     DAI(ADX4),
0268     DAI(ADX4 TX1),
0269     DAI(ADX4 TX2),
0270     DAI(ADX4 TX3),
0271     DAI(ADX4 TX4),
0272     /* XBAR -> MIXER1(10:5) -> XBAR */
0273     DAI(MIXER1 RX1),
0274     DAI(MIXER1 RX2),
0275     DAI(MIXER1 RX3),
0276     DAI(MIXER1 RX4),
0277     DAI(MIXER1 RX5),
0278     DAI(MIXER1 RX6),
0279     DAI(MIXER1 RX7),
0280     DAI(MIXER1 RX8),
0281     DAI(MIXER1 RX9),
0282     DAI(MIXER1 RX10),
0283     DAI(MIXER1 TX1),
0284     DAI(MIXER1 TX2),
0285     DAI(MIXER1 TX3),
0286     DAI(MIXER1 TX4),
0287     DAI(MIXER1 TX5),
0288     /* XBAR -> ASRC -> XBAR */
0289     DAI(ASRC1 RX1),
0290     DAI(ASRC1 TX1),
0291     DAI(ASRC1 RX2),
0292     DAI(ASRC1 TX2),
0293     DAI(ASRC1 RX3),
0294     DAI(ASRC1 TX3),
0295     DAI(ASRC1 RX4),
0296     DAI(ASRC1 TX4),
0297     DAI(ASRC1 RX5),
0298     DAI(ASRC1 TX5),
0299     DAI(ASRC1 RX6),
0300     DAI(ASRC1 TX6),
0301     DAI(ASRC1 RX7),
0302     /* XBAR -> OPE -> XBAR */
0303     DAI(OPE1 RX),
0304     DAI(OPE1 TX),
0305 };
0306 
0307 static const char * const tegra210_ahub_mux_texts[] = {
0308     "None",
0309     "ADMAIF1",
0310     "ADMAIF2",
0311     "ADMAIF3",
0312     "ADMAIF4",
0313     "ADMAIF5",
0314     "ADMAIF6",
0315     "ADMAIF7",
0316     "ADMAIF8",
0317     "ADMAIF9",
0318     "ADMAIF10",
0319     "I2S1",
0320     "I2S2",
0321     "I2S3",
0322     "I2S4",
0323     "I2S5",
0324     "DMIC1",
0325     "DMIC2",
0326     "DMIC3",
0327     "SFC1",
0328     "SFC2",
0329     "SFC3",
0330     "SFC4",
0331     "MVC1",
0332     "MVC2",
0333     "AMX1",
0334     "AMX2",
0335     "ADX1 TX1",
0336     "ADX1 TX2",
0337     "ADX1 TX3",
0338     "ADX1 TX4",
0339     "ADX2 TX1",
0340     "ADX2 TX2",
0341     "ADX2 TX3",
0342     "ADX2 TX4",
0343     "MIXER1 TX1",
0344     "MIXER1 TX2",
0345     "MIXER1 TX3",
0346     "MIXER1 TX4",
0347     "MIXER1 TX5",
0348     "OPE1",
0349     "OPE2",
0350 };
0351 
0352 static const char * const tegra186_ahub_mux_texts[] = {
0353     "None",
0354     "ADMAIF1",
0355     "ADMAIF2",
0356     "ADMAIF3",
0357     "ADMAIF4",
0358     "ADMAIF5",
0359     "ADMAIF6",
0360     "ADMAIF7",
0361     "ADMAIF8",
0362     "ADMAIF9",
0363     "ADMAIF10",
0364     "ADMAIF11",
0365     "ADMAIF12",
0366     "ADMAIF13",
0367     "ADMAIF14",
0368     "ADMAIF15",
0369     "ADMAIF16",
0370     "I2S1",
0371     "I2S2",
0372     "I2S3",
0373     "I2S4",
0374     "I2S5",
0375     "I2S6",
0376     "ADMAIF17",
0377     "ADMAIF18",
0378     "ADMAIF19",
0379     "ADMAIF20",
0380     "DMIC1",
0381     "DMIC2",
0382     "DMIC3",
0383     "DMIC4",
0384     "SFC1",
0385     "SFC2",
0386     "SFC3",
0387     "SFC4",
0388     "MVC1",
0389     "MVC2",
0390     "AMX1",
0391     "AMX2",
0392     "AMX3",
0393     "AMX4",
0394     "ADX1 TX1",
0395     "ADX1 TX2",
0396     "ADX1 TX3",
0397     "ADX1 TX4",
0398     "ADX2 TX1",
0399     "ADX2 TX2",
0400     "ADX2 TX3",
0401     "ADX2 TX4",
0402     "ADX3 TX1",
0403     "ADX3 TX2",
0404     "ADX3 TX3",
0405     "ADX3 TX4",
0406     "ADX4 TX1",
0407     "ADX4 TX2",
0408     "ADX4 TX3",
0409     "ADX4 TX4",
0410     "MIXER1 TX1",
0411     "MIXER1 TX2",
0412     "MIXER1 TX3",
0413     "MIXER1 TX4",
0414     "MIXER1 TX5",
0415     "ASRC1 TX1",
0416     "ASRC1 TX2",
0417     "ASRC1 TX3",
0418     "ASRC1 TX4",
0419     "ASRC1 TX5",
0420     "ASRC1 TX6",
0421     "OPE1",
0422 };
0423 
0424 static const unsigned int tegra210_ahub_mux_values[] = {
0425     0,
0426     /* ADMAIF */
0427     MUX_VALUE(0, 0),
0428     MUX_VALUE(0, 1),
0429     MUX_VALUE(0, 2),
0430     MUX_VALUE(0, 3),
0431     MUX_VALUE(0, 4),
0432     MUX_VALUE(0, 5),
0433     MUX_VALUE(0, 6),
0434     MUX_VALUE(0, 7),
0435     MUX_VALUE(0, 8),
0436     MUX_VALUE(0, 9),
0437     /* I2S */
0438     MUX_VALUE(0, 16),
0439     MUX_VALUE(0, 17),
0440     MUX_VALUE(0, 18),
0441     MUX_VALUE(0, 19),
0442     MUX_VALUE(0, 20),
0443     /* DMIC */
0444     MUX_VALUE(2, 18),
0445     MUX_VALUE(2, 19),
0446     MUX_VALUE(2, 20),
0447     /* SFC */
0448     MUX_VALUE(0, 24),
0449     MUX_VALUE(0, 25),
0450     MUX_VALUE(0, 26),
0451     MUX_VALUE(0, 27),
0452     /* MVC */
0453     MUX_VALUE(2, 8),
0454     MUX_VALUE(2, 9),
0455     /* AMX */
0456     MUX_VALUE(1, 8),
0457     MUX_VALUE(1, 9),
0458     /* ADX */
0459     MUX_VALUE(2, 24),
0460     MUX_VALUE(2, 25),
0461     MUX_VALUE(2, 26),
0462     MUX_VALUE(2, 27),
0463     MUX_VALUE(2, 28),
0464     MUX_VALUE(2, 29),
0465     MUX_VALUE(2, 30),
0466     MUX_VALUE(2, 31),
0467     /* MIXER */
0468     MUX_VALUE(1, 0),
0469     MUX_VALUE(1, 1),
0470     MUX_VALUE(1, 2),
0471     MUX_VALUE(1, 3),
0472     MUX_VALUE(1, 4),
0473     /* OPE */
0474     MUX_VALUE(2, 0),
0475     MUX_VALUE(2, 1),
0476 };
0477 
0478 static const unsigned int tegra186_ahub_mux_values[] = {
0479     0,
0480     /* ADMAIF */
0481     MUX_VALUE(0, 0),
0482     MUX_VALUE(0, 1),
0483     MUX_VALUE(0, 2),
0484     MUX_VALUE(0, 3),
0485     MUX_VALUE(0, 4),
0486     MUX_VALUE(0, 5),
0487     MUX_VALUE(0, 6),
0488     MUX_VALUE(0, 7),
0489     MUX_VALUE(0, 8),
0490     MUX_VALUE(0, 9),
0491     MUX_VALUE(0, 10),
0492     MUX_VALUE(0, 11),
0493     MUX_VALUE(0, 12),
0494     MUX_VALUE(0, 13),
0495     MUX_VALUE(0, 14),
0496     MUX_VALUE(0, 15),
0497     /* I2S */
0498     MUX_VALUE(0, 16),
0499     MUX_VALUE(0, 17),
0500     MUX_VALUE(0, 18),
0501     MUX_VALUE(0, 19),
0502     MUX_VALUE(0, 20),
0503     MUX_VALUE(0, 21),
0504     /* ADMAIF */
0505     MUX_VALUE(3, 16),
0506     MUX_VALUE(3, 17),
0507     MUX_VALUE(3, 18),
0508     MUX_VALUE(3, 19),
0509     /* DMIC */
0510     MUX_VALUE(2, 18),
0511     MUX_VALUE(2, 19),
0512     MUX_VALUE(2, 20),
0513     MUX_VALUE(2, 21),
0514     /* SFC */
0515     MUX_VALUE(0, 24),
0516     MUX_VALUE(0, 25),
0517     MUX_VALUE(0, 26),
0518     MUX_VALUE(0, 27),
0519     /* MVC */
0520     MUX_VALUE(2, 8),
0521     MUX_VALUE(2, 9),
0522     /* AMX */
0523     MUX_VALUE(1, 8),
0524     MUX_VALUE(1, 9),
0525     MUX_VALUE(1, 10),
0526     MUX_VALUE(1, 11),
0527     /* ADX */
0528     MUX_VALUE(2, 24),
0529     MUX_VALUE(2, 25),
0530     MUX_VALUE(2, 26),
0531     MUX_VALUE(2, 27),
0532     MUX_VALUE(2, 28),
0533     MUX_VALUE(2, 29),
0534     MUX_VALUE(2, 30),
0535     MUX_VALUE(2, 31),
0536     MUX_VALUE(3, 0),
0537     MUX_VALUE(3, 1),
0538     MUX_VALUE(3, 2),
0539     MUX_VALUE(3, 3),
0540     MUX_VALUE(3, 4),
0541     MUX_VALUE(3, 5),
0542     MUX_VALUE(3, 6),
0543     MUX_VALUE(3, 7),
0544     /* MIXER */
0545     MUX_VALUE(1, 0),
0546     MUX_VALUE(1, 1),
0547     MUX_VALUE(1, 2),
0548     MUX_VALUE(1, 3),
0549     MUX_VALUE(1, 4),
0550     /* ASRC */
0551     MUX_VALUE(3, 24),
0552     MUX_VALUE(3, 25),
0553     MUX_VALUE(3, 26),
0554     MUX_VALUE(3, 27),
0555     MUX_VALUE(3, 28),
0556     MUX_VALUE(3, 29),
0557     /* OPE */
0558     MUX_VALUE(2, 0),
0559 };
0560 
0561 /* Controls for t210 */
0562 MUX_ENUM_CTRL_DECL(t210_admaif1_tx, 0x00);
0563 MUX_ENUM_CTRL_DECL(t210_admaif2_tx, 0x01);
0564 MUX_ENUM_CTRL_DECL(t210_admaif3_tx, 0x02);
0565 MUX_ENUM_CTRL_DECL(t210_admaif4_tx, 0x03);
0566 MUX_ENUM_CTRL_DECL(t210_admaif5_tx, 0x04);
0567 MUX_ENUM_CTRL_DECL(t210_admaif6_tx, 0x05);
0568 MUX_ENUM_CTRL_DECL(t210_admaif7_tx, 0x06);
0569 MUX_ENUM_CTRL_DECL(t210_admaif8_tx, 0x07);
0570 MUX_ENUM_CTRL_DECL(t210_admaif9_tx, 0x08);
0571 MUX_ENUM_CTRL_DECL(t210_admaif10_tx, 0x09);
0572 MUX_ENUM_CTRL_DECL(t210_i2s1_tx, 0x10);
0573 MUX_ENUM_CTRL_DECL(t210_i2s2_tx, 0x11);
0574 MUX_ENUM_CTRL_DECL(t210_i2s3_tx, 0x12);
0575 MUX_ENUM_CTRL_DECL(t210_i2s4_tx, 0x13);
0576 MUX_ENUM_CTRL_DECL(t210_i2s5_tx, 0x14);
0577 MUX_ENUM_CTRL_DECL(t210_sfc1_tx, 0x18);
0578 MUX_ENUM_CTRL_DECL(t210_sfc2_tx, 0x19);
0579 MUX_ENUM_CTRL_DECL(t210_sfc3_tx, 0x1a);
0580 MUX_ENUM_CTRL_DECL(t210_sfc4_tx, 0x1b);
0581 MUX_ENUM_CTRL_DECL(t210_mvc1_tx, 0x48);
0582 MUX_ENUM_CTRL_DECL(t210_mvc2_tx, 0x49);
0583 MUX_ENUM_CTRL_DECL(t210_amx11_tx, 0x50);
0584 MUX_ENUM_CTRL_DECL(t210_amx12_tx, 0x51);
0585 MUX_ENUM_CTRL_DECL(t210_amx13_tx, 0x52);
0586 MUX_ENUM_CTRL_DECL(t210_amx14_tx, 0x53);
0587 MUX_ENUM_CTRL_DECL(t210_amx21_tx, 0x54);
0588 MUX_ENUM_CTRL_DECL(t210_amx22_tx, 0x55);
0589 MUX_ENUM_CTRL_DECL(t210_amx23_tx, 0x56);
0590 MUX_ENUM_CTRL_DECL(t210_amx24_tx, 0x57);
0591 MUX_ENUM_CTRL_DECL(t210_adx1_tx, 0x58);
0592 MUX_ENUM_CTRL_DECL(t210_adx2_tx, 0x59);
0593 MUX_ENUM_CTRL_DECL(t210_mixer11_tx, 0x20);
0594 MUX_ENUM_CTRL_DECL(t210_mixer12_tx, 0x21);
0595 MUX_ENUM_CTRL_DECL(t210_mixer13_tx, 0x22);
0596 MUX_ENUM_CTRL_DECL(t210_mixer14_tx, 0x23);
0597 MUX_ENUM_CTRL_DECL(t210_mixer15_tx, 0x24);
0598 MUX_ENUM_CTRL_DECL(t210_mixer16_tx, 0x25);
0599 MUX_ENUM_CTRL_DECL(t210_mixer17_tx, 0x26);
0600 MUX_ENUM_CTRL_DECL(t210_mixer18_tx, 0x27);
0601 MUX_ENUM_CTRL_DECL(t210_mixer19_tx, 0x28);
0602 MUX_ENUM_CTRL_DECL(t210_mixer110_tx, 0x29);
0603 MUX_ENUM_CTRL_DECL(t210_ope1_tx, 0x40);
0604 MUX_ENUM_CTRL_DECL(t210_ope2_tx, 0x41);
0605 
0606 /* Controls for t186 */
0607 MUX_ENUM_CTRL_DECL_186(t186_admaif1_tx, 0x00);
0608 MUX_ENUM_CTRL_DECL_186(t186_admaif2_tx, 0x01);
0609 MUX_ENUM_CTRL_DECL_186(t186_admaif3_tx, 0x02);
0610 MUX_ENUM_CTRL_DECL_186(t186_admaif4_tx, 0x03);
0611 MUX_ENUM_CTRL_DECL_186(t186_admaif5_tx, 0x04);
0612 MUX_ENUM_CTRL_DECL_186(t186_admaif6_tx, 0x05);
0613 MUX_ENUM_CTRL_DECL_186(t186_admaif7_tx, 0x06);
0614 MUX_ENUM_CTRL_DECL_186(t186_admaif8_tx, 0x07);
0615 MUX_ENUM_CTRL_DECL_186(t186_admaif9_tx, 0x08);
0616 MUX_ENUM_CTRL_DECL_186(t186_admaif10_tx, 0x09);
0617 MUX_ENUM_CTRL_DECL_186(t186_i2s1_tx, 0x10);
0618 MUX_ENUM_CTRL_DECL_186(t186_i2s2_tx, 0x11);
0619 MUX_ENUM_CTRL_DECL_186(t186_i2s3_tx, 0x12);
0620 MUX_ENUM_CTRL_DECL_186(t186_i2s4_tx, 0x13);
0621 MUX_ENUM_CTRL_DECL_186(t186_i2s5_tx, 0x14);
0622 MUX_ENUM_CTRL_DECL_186(t186_admaif11_tx, 0x0a);
0623 MUX_ENUM_CTRL_DECL_186(t186_admaif12_tx, 0x0b);
0624 MUX_ENUM_CTRL_DECL_186(t186_admaif13_tx, 0x0c);
0625 MUX_ENUM_CTRL_DECL_186(t186_admaif14_tx, 0x0d);
0626 MUX_ENUM_CTRL_DECL_186(t186_admaif15_tx, 0x0e);
0627 MUX_ENUM_CTRL_DECL_186(t186_admaif16_tx, 0x0f);
0628 MUX_ENUM_CTRL_DECL_186(t186_i2s6_tx, 0x15);
0629 MUX_ENUM_CTRL_DECL_186(t186_dspk1_tx, 0x30);
0630 MUX_ENUM_CTRL_DECL_186(t186_dspk2_tx, 0x31);
0631 MUX_ENUM_CTRL_DECL_186(t186_admaif17_tx, 0x68);
0632 MUX_ENUM_CTRL_DECL_186(t186_admaif18_tx, 0x69);
0633 MUX_ENUM_CTRL_DECL_186(t186_admaif19_tx, 0x6a);
0634 MUX_ENUM_CTRL_DECL_186(t186_admaif20_tx, 0x6b);
0635 MUX_ENUM_CTRL_DECL_186(t186_sfc1_tx, 0x18);
0636 MUX_ENUM_CTRL_DECL_186(t186_sfc2_tx, 0x19);
0637 MUX_ENUM_CTRL_DECL_186(t186_sfc3_tx, 0x1a);
0638 MUX_ENUM_CTRL_DECL_186(t186_sfc4_tx, 0x1b);
0639 MUX_ENUM_CTRL_DECL_186(t186_mvc1_tx, 0x48);
0640 MUX_ENUM_CTRL_DECL_186(t186_mvc2_tx, 0x49);
0641 MUX_ENUM_CTRL_DECL_186(t186_amx11_tx, 0x50);
0642 MUX_ENUM_CTRL_DECL_186(t186_amx12_tx, 0x51);
0643 MUX_ENUM_CTRL_DECL_186(t186_amx13_tx, 0x52);
0644 MUX_ENUM_CTRL_DECL_186(t186_amx14_tx, 0x53);
0645 MUX_ENUM_CTRL_DECL_186(t186_amx21_tx, 0x54);
0646 MUX_ENUM_CTRL_DECL_186(t186_amx22_tx, 0x55);
0647 MUX_ENUM_CTRL_DECL_186(t186_amx23_tx, 0x56);
0648 MUX_ENUM_CTRL_DECL_186(t186_amx24_tx, 0x57);
0649 MUX_ENUM_CTRL_DECL_186(t186_amx31_tx, 0x58);
0650 MUX_ENUM_CTRL_DECL_186(t186_amx32_tx, 0x59);
0651 MUX_ENUM_CTRL_DECL_186(t186_amx33_tx, 0x5a);
0652 MUX_ENUM_CTRL_DECL_186(t186_amx34_tx, 0x5b);
0653 MUX_ENUM_CTRL_DECL_186(t186_amx41_tx, 0x64);
0654 MUX_ENUM_CTRL_DECL_186(t186_amx42_tx, 0x65);
0655 MUX_ENUM_CTRL_DECL_186(t186_amx43_tx, 0x66);
0656 MUX_ENUM_CTRL_DECL_186(t186_amx44_tx, 0x67);
0657 MUX_ENUM_CTRL_DECL_186(t186_adx1_tx, 0x60);
0658 MUX_ENUM_CTRL_DECL_186(t186_adx2_tx, 0x61);
0659 MUX_ENUM_CTRL_DECL_186(t186_adx3_tx, 0x62);
0660 MUX_ENUM_CTRL_DECL_186(t186_adx4_tx, 0x63);
0661 MUX_ENUM_CTRL_DECL_186(t186_mixer11_tx, 0x20);
0662 MUX_ENUM_CTRL_DECL_186(t186_mixer12_tx, 0x21);
0663 MUX_ENUM_CTRL_DECL_186(t186_mixer13_tx, 0x22);
0664 MUX_ENUM_CTRL_DECL_186(t186_mixer14_tx, 0x23);
0665 MUX_ENUM_CTRL_DECL_186(t186_mixer15_tx, 0x24);
0666 MUX_ENUM_CTRL_DECL_186(t186_mixer16_tx, 0x25);
0667 MUX_ENUM_CTRL_DECL_186(t186_mixer17_tx, 0x26);
0668 MUX_ENUM_CTRL_DECL_186(t186_mixer18_tx, 0x27);
0669 MUX_ENUM_CTRL_DECL_186(t186_mixer19_tx, 0x28);
0670 MUX_ENUM_CTRL_DECL_186(t186_mixer110_tx, 0x29);
0671 MUX_ENUM_CTRL_DECL_186(t186_asrc11_tx, 0x6c);
0672 MUX_ENUM_CTRL_DECL_186(t186_asrc12_tx, 0x6d);
0673 MUX_ENUM_CTRL_DECL_186(t186_asrc13_tx, 0x6e);
0674 MUX_ENUM_CTRL_DECL_186(t186_asrc14_tx, 0x6f);
0675 MUX_ENUM_CTRL_DECL_186(t186_asrc15_tx, 0x70);
0676 MUX_ENUM_CTRL_DECL_186(t186_asrc16_tx, 0x71);
0677 MUX_ENUM_CTRL_DECL_186(t186_asrc17_tx, 0x72);
0678 MUX_ENUM_CTRL_DECL_186(t186_ope1_tx, 0x40);
0679 
0680 /* Controls for t234 */
0681 MUX_ENUM_CTRL_DECL_234(t234_mvc1_tx, 0x44);
0682 MUX_ENUM_CTRL_DECL_234(t234_mvc2_tx, 0x45);
0683 MUX_ENUM_CTRL_DECL_234(t234_amx11_tx, 0x48);
0684 MUX_ENUM_CTRL_DECL_234(t234_amx12_tx, 0x49);
0685 MUX_ENUM_CTRL_DECL_234(t234_amx13_tx, 0x4a);
0686 MUX_ENUM_CTRL_DECL_234(t234_amx14_tx, 0x4b);
0687 MUX_ENUM_CTRL_DECL_234(t234_amx21_tx, 0x4c);
0688 MUX_ENUM_CTRL_DECL_234(t234_amx22_tx, 0x4d);
0689 MUX_ENUM_CTRL_DECL_234(t234_amx23_tx, 0x4e);
0690 MUX_ENUM_CTRL_DECL_234(t234_amx24_tx, 0x4f);
0691 MUX_ENUM_CTRL_DECL_234(t234_amx31_tx, 0x50);
0692 MUX_ENUM_CTRL_DECL_234(t234_amx32_tx, 0x51);
0693 MUX_ENUM_CTRL_DECL_234(t234_amx33_tx, 0x52);
0694 MUX_ENUM_CTRL_DECL_234(t234_amx34_tx, 0x53);
0695 MUX_ENUM_CTRL_DECL_234(t234_adx1_tx, 0x58);
0696 MUX_ENUM_CTRL_DECL_234(t234_adx2_tx, 0x59);
0697 MUX_ENUM_CTRL_DECL_234(t234_adx3_tx, 0x5a);
0698 MUX_ENUM_CTRL_DECL_234(t234_adx4_tx, 0x5b);
0699 MUX_ENUM_CTRL_DECL_234(t234_amx41_tx, 0x5c);
0700 MUX_ENUM_CTRL_DECL_234(t234_amx42_tx, 0x5d);
0701 MUX_ENUM_CTRL_DECL_234(t234_amx43_tx, 0x5e);
0702 MUX_ENUM_CTRL_DECL_234(t234_amx44_tx, 0x5f);
0703 MUX_ENUM_CTRL_DECL_234(t234_admaif17_tx, 0x60);
0704 MUX_ENUM_CTRL_DECL_234(t234_admaif18_tx, 0x61);
0705 MUX_ENUM_CTRL_DECL_234(t234_admaif19_tx, 0x62);
0706 MUX_ENUM_CTRL_DECL_234(t234_admaif20_tx, 0x63);
0707 MUX_ENUM_CTRL_DECL_234(t234_asrc11_tx, 0x64);
0708 MUX_ENUM_CTRL_DECL_234(t234_asrc12_tx, 0x65);
0709 MUX_ENUM_CTRL_DECL_234(t234_asrc13_tx, 0x66);
0710 MUX_ENUM_CTRL_DECL_234(t234_asrc14_tx, 0x67);
0711 MUX_ENUM_CTRL_DECL_234(t234_asrc15_tx, 0x68);
0712 MUX_ENUM_CTRL_DECL_234(t234_asrc16_tx, 0x69);
0713 MUX_ENUM_CTRL_DECL_234(t234_asrc17_tx, 0x6a);
0714 
0715 /*
0716  * The number of entries in, and order of, this array is closely tied to the
0717  * calculation of tegra210_ahub_codec.num_dapm_widgets near the end of
0718  * tegra210_ahub_probe()
0719  */
0720 static const struct snd_soc_dapm_widget tegra210_ahub_widgets[] = {
0721     WIDGETS("ADMAIF1", t210_admaif1_tx),
0722     WIDGETS("ADMAIF2", t210_admaif2_tx),
0723     WIDGETS("ADMAIF3", t210_admaif3_tx),
0724     WIDGETS("ADMAIF4", t210_admaif4_tx),
0725     WIDGETS("ADMAIF5", t210_admaif5_tx),
0726     WIDGETS("ADMAIF6", t210_admaif6_tx),
0727     WIDGETS("ADMAIF7", t210_admaif7_tx),
0728     WIDGETS("ADMAIF8", t210_admaif8_tx),
0729     WIDGETS("ADMAIF9", t210_admaif9_tx),
0730     WIDGETS("ADMAIF10", t210_admaif10_tx),
0731     WIDGETS("I2S1", t210_i2s1_tx),
0732     WIDGETS("I2S2", t210_i2s2_tx),
0733     WIDGETS("I2S3", t210_i2s3_tx),
0734     WIDGETS("I2S4", t210_i2s4_tx),
0735     WIDGETS("I2S5", t210_i2s5_tx),
0736     TX_WIDGETS("DMIC1"),
0737     TX_WIDGETS("DMIC2"),
0738     TX_WIDGETS("DMIC3"),
0739     WIDGETS("SFC1", t210_sfc1_tx),
0740     WIDGETS("SFC2", t210_sfc2_tx),
0741     WIDGETS("SFC3", t210_sfc3_tx),
0742     WIDGETS("SFC4", t210_sfc4_tx),
0743     WIDGETS("MVC1", t210_mvc1_tx),
0744     WIDGETS("MVC2", t210_mvc2_tx),
0745     WIDGETS("AMX1 RX1", t210_amx11_tx),
0746     WIDGETS("AMX1 RX2", t210_amx12_tx),
0747     WIDGETS("AMX1 RX3", t210_amx13_tx),
0748     WIDGETS("AMX1 RX4", t210_amx14_tx),
0749     WIDGETS("AMX2 RX1", t210_amx21_tx),
0750     WIDGETS("AMX2 RX2", t210_amx22_tx),
0751     WIDGETS("AMX2 RX3", t210_amx23_tx),
0752     WIDGETS("AMX2 RX4", t210_amx24_tx),
0753     TX_WIDGETS("AMX1"),
0754     TX_WIDGETS("AMX2"),
0755     WIDGETS("ADX1", t210_adx1_tx),
0756     WIDGETS("ADX2", t210_adx2_tx),
0757     TX_WIDGETS("ADX1 TX1"),
0758     TX_WIDGETS("ADX1 TX2"),
0759     TX_WIDGETS("ADX1 TX3"),
0760     TX_WIDGETS("ADX1 TX4"),
0761     TX_WIDGETS("ADX2 TX1"),
0762     TX_WIDGETS("ADX2 TX2"),
0763     TX_WIDGETS("ADX2 TX3"),
0764     TX_WIDGETS("ADX2 TX4"),
0765     WIDGETS("MIXER1 RX1", t210_mixer11_tx),
0766     WIDGETS("MIXER1 RX2", t210_mixer12_tx),
0767     WIDGETS("MIXER1 RX3", t210_mixer13_tx),
0768     WIDGETS("MIXER1 RX4", t210_mixer14_tx),
0769     WIDGETS("MIXER1 RX5", t210_mixer15_tx),
0770     WIDGETS("MIXER1 RX6", t210_mixer16_tx),
0771     WIDGETS("MIXER1 RX7", t210_mixer17_tx),
0772     WIDGETS("MIXER1 RX8", t210_mixer18_tx),
0773     WIDGETS("MIXER1 RX9", t210_mixer19_tx),
0774     WIDGETS("MIXER1 RX10", t210_mixer110_tx),
0775     TX_WIDGETS("MIXER1 TX1"),
0776     TX_WIDGETS("MIXER1 TX2"),
0777     TX_WIDGETS("MIXER1 TX3"),
0778     TX_WIDGETS("MIXER1 TX4"),
0779     TX_WIDGETS("MIXER1 TX5"),
0780     WIDGETS("OPE1", t210_ope1_tx),
0781     WIDGETS("OPE2", t210_ope2_tx),
0782 };
0783 
0784 static const struct snd_soc_dapm_widget tegra186_ahub_widgets[] = {
0785     WIDGETS("ADMAIF1", t186_admaif1_tx),
0786     WIDGETS("ADMAIF2", t186_admaif2_tx),
0787     WIDGETS("ADMAIF3", t186_admaif3_tx),
0788     WIDGETS("ADMAIF4", t186_admaif4_tx),
0789     WIDGETS("ADMAIF5", t186_admaif5_tx),
0790     WIDGETS("ADMAIF6", t186_admaif6_tx),
0791     WIDGETS("ADMAIF7", t186_admaif7_tx),
0792     WIDGETS("ADMAIF8", t186_admaif8_tx),
0793     WIDGETS("ADMAIF9", t186_admaif9_tx),
0794     WIDGETS("ADMAIF10", t186_admaif10_tx),
0795     WIDGETS("ADMAIF11", t186_admaif11_tx),
0796     WIDGETS("ADMAIF12", t186_admaif12_tx),
0797     WIDGETS("ADMAIF13", t186_admaif13_tx),
0798     WIDGETS("ADMAIF14", t186_admaif14_tx),
0799     WIDGETS("ADMAIF15", t186_admaif15_tx),
0800     WIDGETS("ADMAIF16", t186_admaif16_tx),
0801     WIDGETS("ADMAIF17", t186_admaif17_tx),
0802     WIDGETS("ADMAIF18", t186_admaif18_tx),
0803     WIDGETS("ADMAIF19", t186_admaif19_tx),
0804     WIDGETS("ADMAIF20", t186_admaif20_tx),
0805     WIDGETS("I2S1", t186_i2s1_tx),
0806     WIDGETS("I2S2", t186_i2s2_tx),
0807     WIDGETS("I2S3", t186_i2s3_tx),
0808     WIDGETS("I2S4", t186_i2s4_tx),
0809     WIDGETS("I2S5", t186_i2s5_tx),
0810     WIDGETS("I2S6", t186_i2s6_tx),
0811     TX_WIDGETS("DMIC1"),
0812     TX_WIDGETS("DMIC2"),
0813     TX_WIDGETS("DMIC3"),
0814     TX_WIDGETS("DMIC4"),
0815     WIDGETS("DSPK1", t186_dspk1_tx),
0816     WIDGETS("DSPK2", t186_dspk2_tx),
0817     WIDGETS("SFC1", t186_sfc1_tx),
0818     WIDGETS("SFC2", t186_sfc2_tx),
0819     WIDGETS("SFC3", t186_sfc3_tx),
0820     WIDGETS("SFC4", t186_sfc4_tx),
0821     WIDGETS("MVC1", t186_mvc1_tx),
0822     WIDGETS("MVC2", t186_mvc2_tx),
0823     WIDGETS("AMX1 RX1", t186_amx11_tx),
0824     WIDGETS("AMX1 RX2", t186_amx12_tx),
0825     WIDGETS("AMX1 RX3", t186_amx13_tx),
0826     WIDGETS("AMX1 RX4", t186_amx14_tx),
0827     WIDGETS("AMX2 RX1", t186_amx21_tx),
0828     WIDGETS("AMX2 RX2", t186_amx22_tx),
0829     WIDGETS("AMX2 RX3", t186_amx23_tx),
0830     WIDGETS("AMX2 RX4", t186_amx24_tx),
0831     WIDGETS("AMX3 RX1", t186_amx31_tx),
0832     WIDGETS("AMX3 RX2", t186_amx32_tx),
0833     WIDGETS("AMX3 RX3", t186_amx33_tx),
0834     WIDGETS("AMX3 RX4", t186_amx34_tx),
0835     WIDGETS("AMX4 RX1", t186_amx41_tx),
0836     WIDGETS("AMX4 RX2", t186_amx42_tx),
0837     WIDGETS("AMX4 RX3", t186_amx43_tx),
0838     WIDGETS("AMX4 RX4", t186_amx44_tx),
0839     TX_WIDGETS("AMX1"),
0840     TX_WIDGETS("AMX2"),
0841     TX_WIDGETS("AMX3"),
0842     TX_WIDGETS("AMX4"),
0843     WIDGETS("ADX1", t186_adx1_tx),
0844     WIDGETS("ADX2", t186_adx2_tx),
0845     WIDGETS("ADX3", t186_adx3_tx),
0846     WIDGETS("ADX4", t186_adx4_tx),
0847     TX_WIDGETS("ADX1 TX1"),
0848     TX_WIDGETS("ADX1 TX2"),
0849     TX_WIDGETS("ADX1 TX3"),
0850     TX_WIDGETS("ADX1 TX4"),
0851     TX_WIDGETS("ADX2 TX1"),
0852     TX_WIDGETS("ADX2 TX2"),
0853     TX_WIDGETS("ADX2 TX3"),
0854     TX_WIDGETS("ADX2 TX4"),
0855     TX_WIDGETS("ADX3 TX1"),
0856     TX_WIDGETS("ADX3 TX2"),
0857     TX_WIDGETS("ADX3 TX3"),
0858     TX_WIDGETS("ADX3 TX4"),
0859     TX_WIDGETS("ADX4 TX1"),
0860     TX_WIDGETS("ADX4 TX2"),
0861     TX_WIDGETS("ADX4 TX3"),
0862     TX_WIDGETS("ADX4 TX4"),
0863     WIDGETS("MIXER1 RX1", t186_mixer11_tx),
0864     WIDGETS("MIXER1 RX2", t186_mixer12_tx),
0865     WIDGETS("MIXER1 RX3", t186_mixer13_tx),
0866     WIDGETS("MIXER1 RX4", t186_mixer14_tx),
0867     WIDGETS("MIXER1 RX5", t186_mixer15_tx),
0868     WIDGETS("MIXER1 RX6", t186_mixer16_tx),
0869     WIDGETS("MIXER1 RX7", t186_mixer17_tx),
0870     WIDGETS("MIXER1 RX8", t186_mixer18_tx),
0871     WIDGETS("MIXER1 RX9", t186_mixer19_tx),
0872     WIDGETS("MIXER1 RX10", t186_mixer110_tx),
0873     TX_WIDGETS("MIXER1 TX1"),
0874     TX_WIDGETS("MIXER1 TX2"),
0875     TX_WIDGETS("MIXER1 TX3"),
0876     TX_WIDGETS("MIXER1 TX4"),
0877     TX_WIDGETS("MIXER1 TX5"),
0878     WIDGETS("ASRC1 RX1", t186_asrc11_tx),
0879     WIDGETS("ASRC1 RX2", t186_asrc12_tx),
0880     WIDGETS("ASRC1 RX3", t186_asrc13_tx),
0881     WIDGETS("ASRC1 RX4", t186_asrc14_tx),
0882     WIDGETS("ASRC1 RX5", t186_asrc15_tx),
0883     WIDGETS("ASRC1 RX6", t186_asrc16_tx),
0884     WIDGETS("ASRC1 RX7", t186_asrc17_tx),
0885     TX_WIDGETS("ASRC1 TX1"),
0886     TX_WIDGETS("ASRC1 TX2"),
0887     TX_WIDGETS("ASRC1 TX3"),
0888     TX_WIDGETS("ASRC1 TX4"),
0889     TX_WIDGETS("ASRC1 TX5"),
0890     TX_WIDGETS("ASRC1 TX6"),
0891     WIDGETS("OPE1", t186_ope1_tx),
0892 };
0893 
0894 static const struct snd_soc_dapm_widget tegra234_ahub_widgets[] = {
0895     WIDGETS("ADMAIF1", t186_admaif1_tx),
0896     WIDGETS("ADMAIF2", t186_admaif2_tx),
0897     WIDGETS("ADMAIF3", t186_admaif3_tx),
0898     WIDGETS("ADMAIF4", t186_admaif4_tx),
0899     WIDGETS("ADMAIF5", t186_admaif5_tx),
0900     WIDGETS("ADMAIF6", t186_admaif6_tx),
0901     WIDGETS("ADMAIF7", t186_admaif7_tx),
0902     WIDGETS("ADMAIF8", t186_admaif8_tx),
0903     WIDGETS("ADMAIF9", t186_admaif9_tx),
0904     WIDGETS("ADMAIF10", t186_admaif10_tx),
0905     WIDGETS("ADMAIF11", t186_admaif11_tx),
0906     WIDGETS("ADMAIF12", t186_admaif12_tx),
0907     WIDGETS("ADMAIF13", t186_admaif13_tx),
0908     WIDGETS("ADMAIF14", t186_admaif14_tx),
0909     WIDGETS("ADMAIF15", t186_admaif15_tx),
0910     WIDGETS("ADMAIF16", t186_admaif16_tx),
0911     WIDGETS("ADMAIF17", t234_admaif17_tx),
0912     WIDGETS("ADMAIF18", t234_admaif18_tx),
0913     WIDGETS("ADMAIF19", t234_admaif19_tx),
0914     WIDGETS("ADMAIF20", t234_admaif20_tx),
0915     WIDGETS("I2S1", t186_i2s1_tx),
0916     WIDGETS("I2S2", t186_i2s2_tx),
0917     WIDGETS("I2S3", t186_i2s3_tx),
0918     WIDGETS("I2S4", t186_i2s4_tx),
0919     WIDGETS("I2S5", t186_i2s5_tx),
0920     WIDGETS("I2S6", t186_i2s6_tx),
0921     TX_WIDGETS("DMIC1"),
0922     TX_WIDGETS("DMIC2"),
0923     TX_WIDGETS("DMIC3"),
0924     TX_WIDGETS("DMIC4"),
0925     WIDGETS("DSPK1", t186_dspk1_tx),
0926     WIDGETS("DSPK2", t186_dspk2_tx),
0927     WIDGETS("SFC1", t186_sfc1_tx),
0928     WIDGETS("SFC2", t186_sfc2_tx),
0929     WIDGETS("SFC3", t186_sfc3_tx),
0930     WIDGETS("SFC4", t186_sfc4_tx),
0931     WIDGETS("MVC1", t234_mvc1_tx),
0932     WIDGETS("MVC2", t234_mvc2_tx),
0933     WIDGETS("AMX1 RX1", t234_amx11_tx),
0934     WIDGETS("AMX1 RX2", t234_amx12_tx),
0935     WIDGETS("AMX1 RX3", t234_amx13_tx),
0936     WIDGETS("AMX1 RX4", t234_amx14_tx),
0937     WIDGETS("AMX2 RX1", t234_amx21_tx),
0938     WIDGETS("AMX2 RX2", t234_amx22_tx),
0939     WIDGETS("AMX2 RX3", t234_amx23_tx),
0940     WIDGETS("AMX2 RX4", t234_amx24_tx),
0941     WIDGETS("AMX3 RX1", t234_amx31_tx),
0942     WIDGETS("AMX3 RX2", t234_amx32_tx),
0943     WIDGETS("AMX3 RX3", t234_amx33_tx),
0944     WIDGETS("AMX3 RX4", t234_amx34_tx),
0945     WIDGETS("AMX4 RX1", t234_amx41_tx),
0946     WIDGETS("AMX4 RX2", t234_amx42_tx),
0947     WIDGETS("AMX4 RX3", t234_amx43_tx),
0948     WIDGETS("AMX4 RX4", t234_amx44_tx),
0949     TX_WIDGETS("AMX1"),
0950     TX_WIDGETS("AMX2"),
0951     TX_WIDGETS("AMX3"),
0952     TX_WIDGETS("AMX4"),
0953     WIDGETS("ADX1", t234_adx1_tx),
0954     WIDGETS("ADX2", t234_adx2_tx),
0955     WIDGETS("ADX3", t234_adx3_tx),
0956     WIDGETS("ADX4", t234_adx4_tx),
0957     TX_WIDGETS("ADX1 TX1"),
0958     TX_WIDGETS("ADX1 TX2"),
0959     TX_WIDGETS("ADX1 TX3"),
0960     TX_WIDGETS("ADX1 TX4"),
0961     TX_WIDGETS("ADX2 TX1"),
0962     TX_WIDGETS("ADX2 TX2"),
0963     TX_WIDGETS("ADX2 TX3"),
0964     TX_WIDGETS("ADX2 TX4"),
0965     TX_WIDGETS("ADX3 TX1"),
0966     TX_WIDGETS("ADX3 TX2"),
0967     TX_WIDGETS("ADX3 TX3"),
0968     TX_WIDGETS("ADX3 TX4"),
0969     TX_WIDGETS("ADX4 TX1"),
0970     TX_WIDGETS("ADX4 TX2"),
0971     TX_WIDGETS("ADX4 TX3"),
0972     TX_WIDGETS("ADX4 TX4"),
0973     WIDGETS("MIXER1 RX1", t186_mixer11_tx),
0974     WIDGETS("MIXER1 RX2", t186_mixer12_tx),
0975     WIDGETS("MIXER1 RX3", t186_mixer13_tx),
0976     WIDGETS("MIXER1 RX4", t186_mixer14_tx),
0977     WIDGETS("MIXER1 RX5", t186_mixer15_tx),
0978     WIDGETS("MIXER1 RX6", t186_mixer16_tx),
0979     WIDGETS("MIXER1 RX7", t186_mixer17_tx),
0980     WIDGETS("MIXER1 RX8", t186_mixer18_tx),
0981     WIDGETS("MIXER1 RX9", t186_mixer19_tx),
0982     WIDGETS("MIXER1 RX10", t186_mixer110_tx),
0983     TX_WIDGETS("MIXER1 TX1"),
0984     TX_WIDGETS("MIXER1 TX2"),
0985     TX_WIDGETS("MIXER1 TX3"),
0986     TX_WIDGETS("MIXER1 TX4"),
0987     TX_WIDGETS("MIXER1 TX5"),
0988     WIDGETS("ASRC1 RX1", t234_asrc11_tx),
0989     WIDGETS("ASRC1 RX2", t234_asrc12_tx),
0990     WIDGETS("ASRC1 RX3", t234_asrc13_tx),
0991     WIDGETS("ASRC1 RX4", t234_asrc14_tx),
0992     WIDGETS("ASRC1 RX5", t234_asrc15_tx),
0993     WIDGETS("ASRC1 RX6", t234_asrc16_tx),
0994     WIDGETS("ASRC1 RX7", t234_asrc17_tx),
0995     TX_WIDGETS("ASRC1 TX1"),
0996     TX_WIDGETS("ASRC1 TX2"),
0997     TX_WIDGETS("ASRC1 TX3"),
0998     TX_WIDGETS("ASRC1 TX4"),
0999     TX_WIDGETS("ASRC1 TX5"),
1000     TX_WIDGETS("ASRC1 TX6"),
1001     WIDGETS("OPE1", t186_ope1_tx),
1002 };
1003 
1004 #define TEGRA_COMMON_MUX_ROUTES(name)                   \
1005     { name " XBAR-TX",   NULL,      name " Mux" },      \
1006     { name " Mux",      "ADMAIF1",  "ADMAIF1 XBAR-RX" },    \
1007     { name " Mux",      "ADMAIF2",  "ADMAIF2 XBAR-RX" },    \
1008     { name " Mux",      "ADMAIF3",  "ADMAIF3 XBAR-RX" },    \
1009     { name " Mux",      "ADMAIF4",  "ADMAIF4 XBAR-RX" },    \
1010     { name " Mux",      "ADMAIF5",  "ADMAIF5 XBAR-RX" },    \
1011     { name " Mux",      "ADMAIF6",  "ADMAIF6 XBAR-RX" },    \
1012     { name " Mux",      "ADMAIF7",  "ADMAIF7 XBAR-RX" },    \
1013     { name " Mux",      "ADMAIF8",  "ADMAIF8 XBAR-RX" },    \
1014     { name " Mux",      "ADMAIF9",  "ADMAIF9 XBAR-RX" },    \
1015     { name " Mux",      "ADMAIF10", "ADMAIF10 XBAR-RX" },   \
1016     { name " Mux",      "I2S1",     "I2S1 XBAR-RX" },   \
1017     { name " Mux",      "I2S2",     "I2S2 XBAR-RX" },   \
1018     { name " Mux",      "I2S3",     "I2S3 XBAR-RX" },   \
1019     { name " Mux",      "I2S4",     "I2S4 XBAR-RX" },   \
1020     { name " Mux",      "I2S5",     "I2S5 XBAR-RX" },   \
1021     { name " Mux",      "DMIC1",    "DMIC1 XBAR-RX" },  \
1022     { name " Mux",      "DMIC2",    "DMIC2 XBAR-RX" },  \
1023     { name " Mux",      "DMIC3",    "DMIC3 XBAR-RX" },  \
1024     { name " Mux",      "SFC1",     "SFC1 XBAR-RX" },   \
1025     { name " Mux",      "SFC2",     "SFC2 XBAR-RX" },   \
1026     { name " Mux",      "SFC3",     "SFC3 XBAR-RX" },   \
1027     { name " Mux",      "SFC4",     "SFC4 XBAR-RX" },   \
1028     { name " Mux",      "MVC1",     "MVC1 XBAR-RX" },   \
1029     { name " Mux",      "MVC2",     "MVC2 XBAR-RX" },   \
1030     { name " Mux",      "AMX1",     "AMX1 XBAR-RX" },   \
1031     { name " Mux",      "AMX2",     "AMX2 XBAR-RX" },   \
1032     { name " Mux",      "ADX1 TX1", "ADX1 TX1 XBAR-RX" },   \
1033     { name " Mux",      "ADX1 TX2", "ADX1 TX2 XBAR-RX" },   \
1034     { name " Mux",      "ADX1 TX3", "ADX1 TX3 XBAR-RX" },   \
1035     { name " Mux",      "ADX1 TX4", "ADX1 TX4 XBAR-RX" },   \
1036     { name " Mux",      "ADX2 TX1", "ADX2 TX1 XBAR-RX" },   \
1037     { name " Mux",      "ADX2 TX2", "ADX2 TX2 XBAR-RX" },   \
1038     { name " Mux",      "ADX2 TX3", "ADX2 TX3 XBAR-RX" },   \
1039     { name " Mux",      "ADX2 TX4", "ADX2 TX4 XBAR-RX" },   \
1040     { name " Mux",      "MIXER1 TX1",   "MIXER1 TX1 XBAR-RX" }, \
1041     { name " Mux",      "MIXER1 TX2",   "MIXER1 TX2 XBAR-RX" }, \
1042     { name " Mux",      "MIXER1 TX3",   "MIXER1 TX3 XBAR-RX" }, \
1043     { name " Mux",      "MIXER1 TX4",   "MIXER1 TX4 XBAR-RX" }, \
1044     { name " Mux",      "MIXER1 TX5",   "MIXER1 TX5 XBAR-RX" }, \
1045     { name " Mux",      "OPE1",     "OPE1 XBAR-RX" },
1046 
1047 #define TEGRA210_ONLY_MUX_ROUTES(name)                  \
1048     { name " Mux",          "OPE2",         "OPE2 XBAR-RX" },
1049 
1050 #define TEGRA186_ONLY_MUX_ROUTES(name)                  \
1051     { name " Mux",      "ADMAIF11", "ADMAIF11 XBAR-RX" },   \
1052     { name " Mux",      "ADMAIF12", "ADMAIF12 XBAR-RX" },   \
1053     { name " Mux",      "ADMAIF13", "ADMAIF13 XBAR-RX" },   \
1054     { name " Mux",      "ADMAIF14", "ADMAIF14 XBAR-RX" },   \
1055     { name " Mux",      "ADMAIF15", "ADMAIF15 XBAR-RX" },   \
1056     { name " Mux",      "ADMAIF16", "ADMAIF16 XBAR-RX" },   \
1057     { name " Mux",      "ADMAIF17", "ADMAIF17 XBAR-RX" },   \
1058     { name " Mux",      "ADMAIF18", "ADMAIF18 XBAR-RX" },   \
1059     { name " Mux",      "ADMAIF19", "ADMAIF19 XBAR-RX" },   \
1060     { name " Mux",      "ADMAIF20", "ADMAIF20 XBAR-RX" },   \
1061     { name " Mux",      "I2S6",     "I2S6 XBAR-RX" },   \
1062     { name " Mux",      "DMIC4",    "DMIC4 XBAR-RX" },  \
1063     { name " Mux",      "AMX3",     "AMX3 XBAR-RX" },   \
1064     { name " Mux",      "AMX4",     "AMX4 XBAR-RX" },   \
1065     { name " Mux",      "ADX3 TX1", "ADX3 TX1 XBAR-RX" },   \
1066     { name " Mux",      "ADX3 TX2", "ADX3 TX2 XBAR-RX" },   \
1067     { name " Mux",      "ADX3 TX3", "ADX3 TX3 XBAR-RX" },   \
1068     { name " Mux",      "ADX3 TX4", "ADX3 TX4 XBAR-RX" },   \
1069     { name " Mux",      "ADX4 TX1", "ADX4 TX1 XBAR-RX" },   \
1070     { name " Mux",      "ADX4 TX2", "ADX4 TX2 XBAR-RX" },   \
1071     { name " Mux",      "ADX4 TX3", "ADX4 TX3 XBAR-RX" },   \
1072     { name " Mux",      "ADX4 TX4", "ADX4 TX4 XBAR-RX" },   \
1073     { name " Mux",      "ASRC1 TX1",    "ASRC1 TX1 XBAR-RX" },  \
1074     { name " Mux",      "ASRC1 TX2",    "ASRC1 TX2 XBAR-RX" },  \
1075     { name " Mux",      "ASRC1 TX3",    "ASRC1 TX3 XBAR-RX" },  \
1076     { name " Mux",      "ASRC1 TX4",    "ASRC1 TX4 XBAR-RX" },  \
1077     { name " Mux",      "ASRC1 TX5",    "ASRC1 TX5 XBAR-RX" },  \
1078     { name " Mux",      "ASRC1 TX6",    "ASRC1 TX6 XBAR-RX" },
1079 
1080 #define TEGRA210_MUX_ROUTES(name)                   \
1081     TEGRA_COMMON_MUX_ROUTES(name)                   \
1082     TEGRA210_ONLY_MUX_ROUTES(name)
1083 
1084 #define TEGRA186_MUX_ROUTES(name)                   \
1085     TEGRA_COMMON_MUX_ROUTES(name)                   \
1086     TEGRA186_ONLY_MUX_ROUTES(name)
1087 
1088 /* Connect FEs with XBAR */
1089 #define TEGRA_FE_ROUTES(name) \
1090     { name " XBAR-Playback",    NULL,   name " Playback" }, \
1091     { name " XBAR-RX",      NULL,   name " XBAR-Playback"}, \
1092     { name " XBAR-Capture",     NULL,   name " XBAR-TX" },      \
1093     { name " Capture",      NULL,   name " XBAR-Capture" },
1094 
1095 /*
1096  * The number of entries in, and order of, this array is closely tied to the
1097  * calculation of tegra210_ahub_codec.num_dapm_routes near the end of
1098  * tegra210_ahub_probe()
1099  */
1100 static const struct snd_soc_dapm_route tegra210_ahub_routes[] = {
1101     TEGRA_FE_ROUTES("ADMAIF1")
1102     TEGRA_FE_ROUTES("ADMAIF2")
1103     TEGRA_FE_ROUTES("ADMAIF3")
1104     TEGRA_FE_ROUTES("ADMAIF4")
1105     TEGRA_FE_ROUTES("ADMAIF5")
1106     TEGRA_FE_ROUTES("ADMAIF6")
1107     TEGRA_FE_ROUTES("ADMAIF7")
1108     TEGRA_FE_ROUTES("ADMAIF8")
1109     TEGRA_FE_ROUTES("ADMAIF9")
1110     TEGRA_FE_ROUTES("ADMAIF10")
1111     TEGRA210_MUX_ROUTES("ADMAIF1")
1112     TEGRA210_MUX_ROUTES("ADMAIF2")
1113     TEGRA210_MUX_ROUTES("ADMAIF3")
1114     TEGRA210_MUX_ROUTES("ADMAIF4")
1115     TEGRA210_MUX_ROUTES("ADMAIF5")
1116     TEGRA210_MUX_ROUTES("ADMAIF6")
1117     TEGRA210_MUX_ROUTES("ADMAIF7")
1118     TEGRA210_MUX_ROUTES("ADMAIF8")
1119     TEGRA210_MUX_ROUTES("ADMAIF9")
1120     TEGRA210_MUX_ROUTES("ADMAIF10")
1121     TEGRA210_MUX_ROUTES("I2S1")
1122     TEGRA210_MUX_ROUTES("I2S2")
1123     TEGRA210_MUX_ROUTES("I2S3")
1124     TEGRA210_MUX_ROUTES("I2S4")
1125     TEGRA210_MUX_ROUTES("I2S5")
1126     TEGRA210_MUX_ROUTES("SFC1")
1127     TEGRA210_MUX_ROUTES("SFC2")
1128     TEGRA210_MUX_ROUTES("SFC3")
1129     TEGRA210_MUX_ROUTES("SFC4")
1130     TEGRA210_MUX_ROUTES("MVC1")
1131     TEGRA210_MUX_ROUTES("MVC2")
1132     TEGRA210_MUX_ROUTES("AMX1 RX1")
1133     TEGRA210_MUX_ROUTES("AMX1 RX2")
1134     TEGRA210_MUX_ROUTES("AMX1 RX3")
1135     TEGRA210_MUX_ROUTES("AMX1 RX4")
1136     TEGRA210_MUX_ROUTES("AMX2 RX1")
1137     TEGRA210_MUX_ROUTES("AMX2 RX2")
1138     TEGRA210_MUX_ROUTES("AMX2 RX3")
1139     TEGRA210_MUX_ROUTES("AMX2 RX4")
1140     TEGRA210_MUX_ROUTES("ADX1")
1141     TEGRA210_MUX_ROUTES("ADX2")
1142     TEGRA210_MUX_ROUTES("MIXER1 RX1")
1143     TEGRA210_MUX_ROUTES("MIXER1 RX2")
1144     TEGRA210_MUX_ROUTES("MIXER1 RX3")
1145     TEGRA210_MUX_ROUTES("MIXER1 RX4")
1146     TEGRA210_MUX_ROUTES("MIXER1 RX5")
1147     TEGRA210_MUX_ROUTES("MIXER1 RX6")
1148     TEGRA210_MUX_ROUTES("MIXER1 RX7")
1149     TEGRA210_MUX_ROUTES("MIXER1 RX8")
1150     TEGRA210_MUX_ROUTES("MIXER1 RX9")
1151     TEGRA210_MUX_ROUTES("MIXER1 RX10")
1152     TEGRA210_MUX_ROUTES("OPE1")
1153     TEGRA210_MUX_ROUTES("OPE2")
1154 };
1155 
1156 static const struct snd_soc_dapm_route tegra186_ahub_routes[] = {
1157     TEGRA_FE_ROUTES("ADMAIF1")
1158     TEGRA_FE_ROUTES("ADMAIF2")
1159     TEGRA_FE_ROUTES("ADMAIF3")
1160     TEGRA_FE_ROUTES("ADMAIF4")
1161     TEGRA_FE_ROUTES("ADMAIF5")
1162     TEGRA_FE_ROUTES("ADMAIF6")
1163     TEGRA_FE_ROUTES("ADMAIF7")
1164     TEGRA_FE_ROUTES("ADMAIF8")
1165     TEGRA_FE_ROUTES("ADMAIF9")
1166     TEGRA_FE_ROUTES("ADMAIF10")
1167     TEGRA_FE_ROUTES("ADMAIF11")
1168     TEGRA_FE_ROUTES("ADMAIF12")
1169     TEGRA_FE_ROUTES("ADMAIF13")
1170     TEGRA_FE_ROUTES("ADMAIF14")
1171     TEGRA_FE_ROUTES("ADMAIF15")
1172     TEGRA_FE_ROUTES("ADMAIF16")
1173     TEGRA_FE_ROUTES("ADMAIF17")
1174     TEGRA_FE_ROUTES("ADMAIF18")
1175     TEGRA_FE_ROUTES("ADMAIF19")
1176     TEGRA_FE_ROUTES("ADMAIF20")
1177     TEGRA186_MUX_ROUTES("ADMAIF1")
1178     TEGRA186_MUX_ROUTES("ADMAIF2")
1179     TEGRA186_MUX_ROUTES("ADMAIF3")
1180     TEGRA186_MUX_ROUTES("ADMAIF4")
1181     TEGRA186_MUX_ROUTES("ADMAIF5")
1182     TEGRA186_MUX_ROUTES("ADMAIF6")
1183     TEGRA186_MUX_ROUTES("ADMAIF7")
1184     TEGRA186_MUX_ROUTES("ADMAIF8")
1185     TEGRA186_MUX_ROUTES("ADMAIF9")
1186     TEGRA186_MUX_ROUTES("ADMAIF10")
1187     TEGRA186_MUX_ROUTES("ADMAIF11")
1188     TEGRA186_MUX_ROUTES("ADMAIF12")
1189     TEGRA186_MUX_ROUTES("ADMAIF13")
1190     TEGRA186_MUX_ROUTES("ADMAIF14")
1191     TEGRA186_MUX_ROUTES("ADMAIF15")
1192     TEGRA186_MUX_ROUTES("ADMAIF16")
1193     TEGRA186_MUX_ROUTES("ADMAIF17")
1194     TEGRA186_MUX_ROUTES("ADMAIF18")
1195     TEGRA186_MUX_ROUTES("ADMAIF19")
1196     TEGRA186_MUX_ROUTES("ADMAIF20")
1197     TEGRA186_MUX_ROUTES("I2S1")
1198     TEGRA186_MUX_ROUTES("I2S2")
1199     TEGRA186_MUX_ROUTES("I2S3")
1200     TEGRA186_MUX_ROUTES("I2S4")
1201     TEGRA186_MUX_ROUTES("I2S5")
1202     TEGRA186_MUX_ROUTES("I2S6")
1203     TEGRA186_MUX_ROUTES("DSPK1")
1204     TEGRA186_MUX_ROUTES("DSPK2")
1205     TEGRA186_MUX_ROUTES("SFC1")
1206     TEGRA186_MUX_ROUTES("SFC2")
1207     TEGRA186_MUX_ROUTES("SFC3")
1208     TEGRA186_MUX_ROUTES("SFC4")
1209     TEGRA186_MUX_ROUTES("MVC1")
1210     TEGRA186_MUX_ROUTES("MVC2")
1211     TEGRA186_MUX_ROUTES("AMX1 RX1")
1212     TEGRA186_MUX_ROUTES("AMX1 RX2")
1213     TEGRA186_MUX_ROUTES("AMX1 RX3")
1214     TEGRA186_MUX_ROUTES("AMX1 RX4")
1215     TEGRA186_MUX_ROUTES("AMX2 RX1")
1216     TEGRA186_MUX_ROUTES("AMX2 RX2")
1217     TEGRA186_MUX_ROUTES("AMX2 RX3")
1218     TEGRA186_MUX_ROUTES("AMX2 RX4")
1219     TEGRA186_MUX_ROUTES("AMX3 RX1")
1220     TEGRA186_MUX_ROUTES("AMX3 RX2")
1221     TEGRA186_MUX_ROUTES("AMX3 RX3")
1222     TEGRA186_MUX_ROUTES("AMX3 RX4")
1223     TEGRA186_MUX_ROUTES("AMX4 RX1")
1224     TEGRA186_MUX_ROUTES("AMX4 RX2")
1225     TEGRA186_MUX_ROUTES("AMX4 RX3")
1226     TEGRA186_MUX_ROUTES("AMX4 RX4")
1227     TEGRA186_MUX_ROUTES("ADX1")
1228     TEGRA186_MUX_ROUTES("ADX2")
1229     TEGRA186_MUX_ROUTES("ADX3")
1230     TEGRA186_MUX_ROUTES("ADX4")
1231     TEGRA186_MUX_ROUTES("MIXER1 RX1")
1232     TEGRA186_MUX_ROUTES("MIXER1 RX2")
1233     TEGRA186_MUX_ROUTES("MIXER1 RX3")
1234     TEGRA186_MUX_ROUTES("MIXER1 RX4")
1235     TEGRA186_MUX_ROUTES("MIXER1 RX5")
1236     TEGRA186_MUX_ROUTES("MIXER1 RX6")
1237     TEGRA186_MUX_ROUTES("MIXER1 RX7")
1238     TEGRA186_MUX_ROUTES("MIXER1 RX8")
1239     TEGRA186_MUX_ROUTES("MIXER1 RX9")
1240     TEGRA186_MUX_ROUTES("MIXER1 RX10")
1241     TEGRA186_MUX_ROUTES("ASRC1 RX1")
1242     TEGRA186_MUX_ROUTES("ASRC1 RX2")
1243     TEGRA186_MUX_ROUTES("ASRC1 RX3")
1244     TEGRA186_MUX_ROUTES("ASRC1 RX4")
1245     TEGRA186_MUX_ROUTES("ASRC1 RX5")
1246     TEGRA186_MUX_ROUTES("ASRC1 RX6")
1247     TEGRA186_MUX_ROUTES("ASRC1 RX7")
1248     TEGRA186_MUX_ROUTES("OPE1")
1249 };
1250 
1251 static const struct snd_soc_component_driver tegra210_ahub_component = {
1252     .dapm_widgets       = tegra210_ahub_widgets,
1253     .num_dapm_widgets   = ARRAY_SIZE(tegra210_ahub_widgets),
1254     .dapm_routes        = tegra210_ahub_routes,
1255     .num_dapm_routes    = ARRAY_SIZE(tegra210_ahub_routes),
1256 };
1257 
1258 static const struct snd_soc_component_driver tegra186_ahub_component = {
1259     .dapm_widgets = tegra186_ahub_widgets,
1260     .num_dapm_widgets = ARRAY_SIZE(tegra186_ahub_widgets),
1261     .dapm_routes = tegra186_ahub_routes,
1262     .num_dapm_routes = ARRAY_SIZE(tegra186_ahub_routes),
1263 };
1264 
1265 static const struct snd_soc_component_driver tegra234_ahub_component = {
1266     .dapm_widgets       = tegra234_ahub_widgets,
1267     .num_dapm_widgets   = ARRAY_SIZE(tegra234_ahub_widgets),
1268     .dapm_routes        = tegra186_ahub_routes,
1269     .num_dapm_routes    = ARRAY_SIZE(tegra186_ahub_routes),
1270 };
1271 
1272 static const struct regmap_config tegra210_ahub_regmap_config = {
1273     .reg_bits       = 32,
1274     .val_bits       = 32,
1275     .reg_stride     = 4,
1276     .max_register       = TEGRA210_MAX_REGISTER_ADDR,
1277     .cache_type     = REGCACHE_FLAT,
1278 };
1279 
1280 static const struct regmap_config tegra186_ahub_regmap_config = {
1281     .reg_bits       = 32,
1282     .val_bits       = 32,
1283     .reg_stride     = 4,
1284     .max_register       = TEGRA186_MAX_REGISTER_ADDR,
1285     .cache_type     = REGCACHE_FLAT,
1286 };
1287 
1288 static const struct tegra_ahub_soc_data soc_data_tegra210 = {
1289     .cmpnt_drv  = &tegra210_ahub_component,
1290     .dai_drv    = tegra210_ahub_dais,
1291     .num_dais   = ARRAY_SIZE(tegra210_ahub_dais),
1292     .regmap_config  = &tegra210_ahub_regmap_config,
1293     .mask[0]    = TEGRA210_XBAR_REG_MASK_0,
1294     .mask[1]    = TEGRA210_XBAR_REG_MASK_1,
1295     .mask[2]    = TEGRA210_XBAR_REG_MASK_2,
1296     .mask[3]    = TEGRA210_XBAR_REG_MASK_3,
1297     .reg_count  = TEGRA210_XBAR_UPDATE_MAX_REG,
1298 };
1299 
1300 static const struct tegra_ahub_soc_data soc_data_tegra186 = {
1301     .cmpnt_drv  = &tegra186_ahub_component,
1302     .dai_drv    = tegra186_ahub_dais,
1303     .num_dais   = ARRAY_SIZE(tegra186_ahub_dais),
1304     .regmap_config  = &tegra186_ahub_regmap_config,
1305     .mask[0]    = TEGRA186_XBAR_REG_MASK_0,
1306     .mask[1]    = TEGRA186_XBAR_REG_MASK_1,
1307     .mask[2]    = TEGRA186_XBAR_REG_MASK_2,
1308     .mask[3]    = TEGRA186_XBAR_REG_MASK_3,
1309     .reg_count  = TEGRA186_XBAR_UPDATE_MAX_REG,
1310 };
1311 
1312 static const struct tegra_ahub_soc_data soc_data_tegra234 = {
1313     .cmpnt_drv  = &tegra234_ahub_component,
1314     .dai_drv    = tegra186_ahub_dais,
1315     .num_dais   = ARRAY_SIZE(tegra186_ahub_dais),
1316     .regmap_config  = &tegra186_ahub_regmap_config,
1317     .mask[0]    = TEGRA186_XBAR_REG_MASK_0,
1318     .mask[1]    = TEGRA186_XBAR_REG_MASK_1,
1319     .mask[2]    = TEGRA186_XBAR_REG_MASK_2,
1320     .mask[3]    = TEGRA186_XBAR_REG_MASK_3,
1321     .reg_count  = TEGRA186_XBAR_UPDATE_MAX_REG,
1322 };
1323 
1324 static const struct of_device_id tegra_ahub_of_match[] = {
1325     { .compatible = "nvidia,tegra210-ahub", .data = &soc_data_tegra210 },
1326     { .compatible = "nvidia,tegra186-ahub", .data = &soc_data_tegra186 },
1327     { .compatible = "nvidia,tegra234-ahub", .data = &soc_data_tegra234 },
1328     {},
1329 };
1330 MODULE_DEVICE_TABLE(of, tegra_ahub_of_match);
1331 
1332 static int __maybe_unused tegra_ahub_runtime_suspend(struct device *dev)
1333 {
1334     struct tegra_ahub *ahub = dev_get_drvdata(dev);
1335 
1336     regcache_cache_only(ahub->regmap, true);
1337     regcache_mark_dirty(ahub->regmap);
1338 
1339     clk_disable_unprepare(ahub->clk);
1340 
1341     return 0;
1342 }
1343 
1344 static int __maybe_unused tegra_ahub_runtime_resume(struct device *dev)
1345 {
1346     struct tegra_ahub *ahub = dev_get_drvdata(dev);
1347     int err;
1348 
1349     err = clk_prepare_enable(ahub->clk);
1350     if (err) {
1351         dev_err(dev, "failed to enable AHUB clock, err: %d\n", err);
1352         return err;
1353     }
1354 
1355     regcache_cache_only(ahub->regmap, false);
1356     regcache_sync(ahub->regmap);
1357 
1358     return 0;
1359 }
1360 
1361 static int tegra_ahub_probe(struct platform_device *pdev)
1362 {
1363     struct tegra_ahub *ahub;
1364     void __iomem *regs;
1365     int err;
1366 
1367     ahub = devm_kzalloc(&pdev->dev, sizeof(*ahub), GFP_KERNEL);
1368     if (!ahub)
1369         return -ENOMEM;
1370 
1371     ahub->soc_data = of_device_get_match_data(&pdev->dev);
1372 
1373     platform_set_drvdata(pdev, ahub);
1374 
1375     ahub->clk = devm_clk_get(&pdev->dev, "ahub");
1376     if (IS_ERR(ahub->clk)) {
1377         dev_err(&pdev->dev, "can't retrieve AHUB clock\n");
1378         return PTR_ERR(ahub->clk);
1379     }
1380 
1381     regs = devm_platform_ioremap_resource(pdev, 0);
1382     if (IS_ERR(regs))
1383         return PTR_ERR(regs);
1384 
1385     ahub->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
1386                          ahub->soc_data->regmap_config);
1387     if (IS_ERR(ahub->regmap)) {
1388         dev_err(&pdev->dev, "regmap init failed\n");
1389         return PTR_ERR(ahub->regmap);
1390     }
1391 
1392     regcache_cache_only(ahub->regmap, true);
1393 
1394     err = devm_snd_soc_register_component(&pdev->dev,
1395                           ahub->soc_data->cmpnt_drv,
1396                           ahub->soc_data->dai_drv,
1397                           ahub->soc_data->num_dais);
1398     if (err) {
1399         dev_err(&pdev->dev, "can't register AHUB component, err: %d\n",
1400             err);
1401         return err;
1402     }
1403 
1404     err = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
1405     if (err)
1406         return err;
1407 
1408     pm_runtime_enable(&pdev->dev);
1409 
1410     return 0;
1411 }
1412 
1413 static int tegra_ahub_remove(struct platform_device *pdev)
1414 {
1415     pm_runtime_disable(&pdev->dev);
1416 
1417     return 0;
1418 }
1419 
1420 static const struct dev_pm_ops tegra_ahub_pm_ops = {
1421     SET_RUNTIME_PM_OPS(tegra_ahub_runtime_suspend,
1422                tegra_ahub_runtime_resume, NULL)
1423     SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1424                 pm_runtime_force_resume)
1425 };
1426 
1427 static struct platform_driver tegra_ahub_driver = {
1428     .probe = tegra_ahub_probe,
1429     .remove = tegra_ahub_remove,
1430     .driver = {
1431         .name = "tegra210-ahub",
1432         .of_match_table = tegra_ahub_of_match,
1433         .pm = &tegra_ahub_pm_ops,
1434     },
1435 };
1436 module_platform_driver(tegra_ahub_driver);
1437 
1438 MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
1439 MODULE_AUTHOR("Mohan Kumar <mkumard@nvidia.com>");
1440 MODULE_DESCRIPTION("Tegra210 ASoC AHUB driver");
1441 MODULE_LICENSE("GPL v2");
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