soc/tegra/tegra20_spdif.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * tegra20_spdif.c - Tegra20 SPDIF driver
0004  *
0005  * Author: Stephen Warren <swarren@nvidia.com>
0006  * Copyright (C) 2011-2012 - NVIDIA, Inc.
0007  */
0008
0009 #include <linux/clk.h>
0010 #include <linux/delay.h>
0011 #include <linux/device.h>
0012 #include <linux/io.h>
0013 #include <linux/module.h>
0014 #include <linux/of_device.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/pm_runtime.h>
0017 #include <linux/regmap.h>
0018 #include <linux/reset.h>
0019 #include <linux/slab.h>
0020 #include <sound/core.h>
0021 #include <sound/pcm.h>
0022 #include <sound/pcm_params.h>
0023 #include <sound/soc.h>
0024 #include <sound/dmaengine_pcm.h>
0025
0026 #include "tegra20_spdif.h"
0027
0028 static __maybe_unused int tegra20_spdif_runtime_suspend(struct device *dev)
0029 {
0030     struct tegra20_spdif *spdif = dev_get_drvdata(dev);
0031
0032     regcache_cache_only(spdif->regmap, true);
0033
0034     clk_disable_unprepare(spdif->clk_spdif_out);
0035
0036     return 0;
0037 }
0038
0039 static __maybe_unused int tegra20_spdif_runtime_resume(struct device *dev)
0040 {
0041     struct tegra20_spdif *spdif = dev_get_drvdata(dev);
0042     int ret;
0043
0044     ret = reset_control_assert(spdif->reset);
0045     if (ret)
0046         return ret;
0047
0048     ret = clk_prepare_enable(spdif->clk_spdif_out);
0049     if (ret) {
0050         dev_err(dev, "clk_enable failed: %d\n", ret);
0051         return ret;
0052     }
0053
0054     usleep_range(10, 100);
0055
0056     ret = reset_control_deassert(spdif->reset);
0057     if (ret)
0058         goto disable_clocks;
0059
0060     regcache_cache_only(spdif->regmap, false);
0061     regcache_mark_dirty(spdif->regmap);
0062
0063     ret = regcache_sync(spdif->regmap);
0064     if (ret)
0065         goto disable_clocks;
0066
0067     return 0;
0068
0069 disable_clocks:
0070     clk_disable_unprepare(spdif->clk_spdif_out);
0071
0072     return ret;
0073 }
0074
0075 static int tegra20_spdif_hw_params(struct snd_pcm_substream *substream,
0076                    struct snd_pcm_hw_params *params,
0077                    struct snd_soc_dai *dai)
0078 {
0079     struct tegra20_spdif *spdif = dev_get_drvdata(dai->dev);
0080     unsigned int mask = 0, val = 0;
0081     int ret, spdifclock;
0082     long rate;
0083
0084     mask |= TEGRA20_SPDIF_CTRL_PACK |
0085         TEGRA20_SPDIF_CTRL_BIT_MODE_MASK;
0086     switch (params_format(params)) {
0087     case SNDRV_PCM_FORMAT_S16_LE:
0088         val |= TEGRA20_SPDIF_CTRL_PACK |
0089                TEGRA20_SPDIF_CTRL_BIT_MODE_16BIT;
0090         break;
0091     default:
0092         return -EINVAL;
0093     }
0094
0095     regmap_update_bits(spdif->regmap, TEGRA20_SPDIF_CTRL, mask, val);
0096
0097     /*
0098      * FIFO trigger level must be bigger than DMA burst or equal to it,
0099      * otherwise data is discarded on overflow.
0100      */
0101     regmap_update_bits(spdif->regmap, TEGRA20_SPDIF_DATA_FIFO_CSR,
0102                TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_MASK,
0103                TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_TU4_WORD_FULL);
0104
0105     switch (params_rate(params)) {
0106     case 32000:
0107         spdifclock = 4096000;
0108         break;
0109     case 44100:
0110         spdifclock = 5644800;
0111         break;
0112     case 48000:
0113         spdifclock = 6144000;
0114         break;
0115     case 88200:
0116         spdifclock = 11289600;
0117         break;
0118     case 96000:
0119         spdifclock = 12288000;
0120         break;
0121     case 176400:
0122         spdifclock = 22579200;
0123         break;
0124     case 192000:
0125         spdifclock = 24576000;
0126         break;
0127     default:
0128         return -EINVAL;
0129     }
0130
0131     ret = clk_set_rate(spdif->clk_spdif_out, spdifclock);
0132     if (ret) {
0133         dev_err(dai->dev, "Can't set SPDIF clock rate: %d\n", ret);
0134         return ret;
0135     }
0136
0137     rate = clk_get_rate(spdif->clk_spdif_out);
0138     if (rate != spdifclock)
0139         dev_warn_once(dai->dev,
0140                   "SPDIF clock rate %d doesn't match requested rate %lu\n",
0141                   spdifclock, rate);
0142
0143     return 0;
0144 }
0145
0146 static void tegra20_spdif_start_playback(struct tegra20_spdif *spdif)
0147 {
0148     regmap_update_bits(spdif->regmap, TEGRA20_SPDIF_CTRL,
0149                TEGRA20_SPDIF_CTRL_TX_EN,
0150                TEGRA20_SPDIF_CTRL_TX_EN);
0151 }
0152
0153 static void tegra20_spdif_stop_playback(struct tegra20_spdif *spdif)
0154 {
0155     regmap_update_bits(spdif->regmap, TEGRA20_SPDIF_CTRL,
0156                TEGRA20_SPDIF_CTRL_TX_EN, 0);
0157 }
0158
0159 static int tegra20_spdif_trigger(struct snd_pcm_substream *substream, int cmd,
0160                  struct snd_soc_dai *dai)
0161 {
0162     struct tegra20_spdif *spdif = dev_get_drvdata(dai->dev);
0163
0164     switch (cmd) {
0165     case SNDRV_PCM_TRIGGER_START:
0166     case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
0167     case SNDRV_PCM_TRIGGER_RESUME:
0168         tegra20_spdif_start_playback(spdif);
0169         break;
0170     case SNDRV_PCM_TRIGGER_STOP:
0171     case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
0172     case SNDRV_PCM_TRIGGER_SUSPEND:
0173         tegra20_spdif_stop_playback(spdif);
0174         break;
0175     default:
0176         return -EINVAL;
0177     }
0178
0179     return 0;
0180 }
0181
0182 static int tegra20_spdif_filter_rates(struct snd_pcm_hw_params *params,
0183                       struct snd_pcm_hw_rule *rule)
0184 {
0185     struct snd_interval *r = hw_param_interval(params, rule->var);
0186     struct snd_soc_dai *dai = rule->private;
0187     struct tegra20_spdif *spdif = dev_get_drvdata(dai->dev);
0188     struct clk *parent = clk_get_parent(spdif->clk_spdif_out);
0189     static const unsigned int rates[] = { 32000, 44100, 48000 };
0190     long i, parent_rate, valid_rates = 0;
0191
0192     parent_rate = clk_get_rate(parent);
0193     if (parent_rate <= 0) {
0194         dev_err(dai->dev, "Can't get parent clock rate: %ld\n",
0195             parent_rate);
0196         return parent_rate ?: -EINVAL;
0197     }
0198
0199     for (i = 0; i < ARRAY_SIZE(rates); i++) {
0200         if (parent_rate % (rates[i] * 128) == 0)
0201             valid_rates |= BIT(i);
0202     }
0203
0204     /*
0205      * At least one rate must be valid, otherwise the parent clock isn't
0206      * audio PLL. Nothing should be filtered in this case.
0207      */
0208     if (!valid_rates)
0209         valid_rates = BIT(ARRAY_SIZE(rates)) - 1;
0210
0211     return snd_interval_list(r, ARRAY_SIZE(rates), rates, valid_rates);
0212 }
0213
0214 static int tegra20_spdif_startup(struct snd_pcm_substream *substream,
0215                  struct snd_soc_dai *dai)
0216 {
0217     if (!device_property_read_bool(dai->dev, "nvidia,fixed-parent-rate"))
0218         return 0;
0219
0220     /*
0221      * SPDIF and I2S share audio PLL. HDMI takes audio packets from SPDIF
0222      * and audio may not work on some TVs if clock rate isn't precise.
0223      *
0224      * PLL rate is controlled by I2S side. Filter out audio rates that
0225      * don't match PLL rate at the start of stream to allow both SPDIF
0226      * and I2S work simultaneously, assuming that PLL rate won't be
0227      * changed later on.
0228      */
0229     return snd_pcm_hw_rule_add(substream->runtime, 0,
0230                    SNDRV_PCM_HW_PARAM_RATE,
0231                    tegra20_spdif_filter_rates, dai,
0232                    SNDRV_PCM_HW_PARAM_RATE, -1);
0233 }
0234
0235 static int tegra20_spdif_probe(struct snd_soc_dai *dai)
0236 {
0237     struct tegra20_spdif *spdif = dev_get_drvdata(dai->dev);
0238
0239     dai->capture_dma_data = NULL;
0240     dai->playback_dma_data = &spdif->playback_dma_data;
0241
0242     return 0;
0243 }
0244
0245 static const struct snd_soc_dai_ops tegra20_spdif_dai_ops = {
0246     .hw_params = tegra20_spdif_hw_params,
0247     .trigger = tegra20_spdif_trigger,
0248     .startup = tegra20_spdif_startup,
0249 };
0250
0251 static struct snd_soc_dai_driver tegra20_spdif_dai = {
0252     .name = "tegra20-spdif",
0253     .probe = tegra20_spdif_probe,
0254     .playback = {
0255         .stream_name = "Playback",
0256         .channels_min = 2,
0257         .channels_max = 2,
0258         .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
0259              SNDRV_PCM_RATE_48000,
0260         .formats = SNDRV_PCM_FMTBIT_S16_LE,
0261     },
0262     .ops = &tegra20_spdif_dai_ops,
0263 };
0264
0265 static const struct snd_soc_component_driver tegra20_spdif_component = {
0266     .name = "tegra20-spdif",
0267     .legacy_dai_naming = 1,
0268 };
0269
0270 static bool tegra20_spdif_wr_rd_reg(struct device *dev, unsigned int reg)
0271 {
0272     switch (reg) {
0273     case TEGRA20_SPDIF_CTRL:
0274     case TEGRA20_SPDIF_STATUS:
0275     case TEGRA20_SPDIF_STROBE_CTRL:
0276     case TEGRA20_SPDIF_DATA_FIFO_CSR:
0277     case TEGRA20_SPDIF_DATA_OUT:
0278     case TEGRA20_SPDIF_DATA_IN:
0279     case TEGRA20_SPDIF_CH_STA_RX_A:
0280     case TEGRA20_SPDIF_CH_STA_RX_B:
0281     case TEGRA20_SPDIF_CH_STA_RX_C:
0282     case TEGRA20_SPDIF_CH_STA_RX_D:
0283     case TEGRA20_SPDIF_CH_STA_RX_E:
0284     case TEGRA20_SPDIF_CH_STA_RX_F:
0285     case TEGRA20_SPDIF_CH_STA_TX_A:
0286     case TEGRA20_SPDIF_CH_STA_TX_B:
0287     case TEGRA20_SPDIF_CH_STA_TX_C:
0288     case TEGRA20_SPDIF_CH_STA_TX_D:
0289     case TEGRA20_SPDIF_CH_STA_TX_E:
0290     case TEGRA20_SPDIF_CH_STA_TX_F:
0291     case TEGRA20_SPDIF_USR_STA_RX_A:
0292     case TEGRA20_SPDIF_USR_DAT_TX_A:
0293         return true;
0294     default:
0295         return false;
0296     }
0297 }
0298
0299 static bool tegra20_spdif_volatile_reg(struct device *dev, unsigned int reg)
0300 {
0301     switch (reg) {
0302     case TEGRA20_SPDIF_STATUS:
0303     case TEGRA20_SPDIF_DATA_FIFO_CSR:
0304     case TEGRA20_SPDIF_DATA_OUT:
0305     case TEGRA20_SPDIF_DATA_IN:
0306     case TEGRA20_SPDIF_CH_STA_RX_A:
0307     case TEGRA20_SPDIF_CH_STA_RX_B:
0308     case TEGRA20_SPDIF_CH_STA_RX_C:
0309     case TEGRA20_SPDIF_CH_STA_RX_D:
0310     case TEGRA20_SPDIF_CH_STA_RX_E:
0311     case TEGRA20_SPDIF_CH_STA_RX_F:
0312     case TEGRA20_SPDIF_USR_STA_RX_A:
0313     case TEGRA20_SPDIF_USR_DAT_TX_A:
0314         return true;
0315     default:
0316         return false;
0317     }
0318 }
0319
0320 static bool tegra20_spdif_precious_reg(struct device *dev, unsigned int reg)
0321 {
0322     switch (reg) {
0323     case TEGRA20_SPDIF_DATA_OUT:
0324     case TEGRA20_SPDIF_DATA_IN:
0325     case TEGRA20_SPDIF_USR_STA_RX_A:
0326     case TEGRA20_SPDIF_USR_DAT_TX_A:
0327         return true;
0328     default:
0329         return false;
0330     }
0331 }
0332
0333 static const struct regmap_config tegra20_spdif_regmap_config = {
0334     .reg_bits = 32,
0335     .reg_stride = 4,
0336     .val_bits = 32,
0337     .max_register = TEGRA20_SPDIF_USR_DAT_TX_A,
0338     .writeable_reg = tegra20_spdif_wr_rd_reg,
0339     .readable_reg = tegra20_spdif_wr_rd_reg,
0340     .volatile_reg = tegra20_spdif_volatile_reg,
0341     .precious_reg = tegra20_spdif_precious_reg,
0342     .cache_type = REGCACHE_FLAT,
0343 };
0344
0345 static int tegra20_spdif_platform_probe(struct platform_device *pdev)
0346 {
0347     struct tegra20_spdif *spdif;
0348     struct resource *mem;
0349     void __iomem *regs;
0350     int ret;
0351
0352     spdif = devm_kzalloc(&pdev->dev, sizeof(struct tegra20_spdif),
0353                  GFP_KERNEL);
0354     if (!spdif)
0355         return -ENOMEM;
0356
0357     dev_set_drvdata(&pdev->dev, spdif);
0358
0359     spdif->reset = devm_reset_control_get_exclusive(&pdev->dev, NULL);
0360     if (IS_ERR(spdif->reset)) {
0361         dev_err(&pdev->dev, "Can't retrieve spdif reset\n");
0362         return PTR_ERR(spdif->reset);
0363     }
0364
0365     spdif->clk_spdif_out = devm_clk_get(&pdev->dev, "out");
0366     if (IS_ERR(spdif->clk_spdif_out)) {
0367         dev_err(&pdev->dev, "Could not retrieve spdif clock\n");
0368         return PTR_ERR(spdif->clk_spdif_out);
0369     }
0370
0371     regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
0372     if (IS_ERR(regs))
0373         return PTR_ERR(regs);
0374
0375     spdif->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
0376                           &tegra20_spdif_regmap_config);
0377     if (IS_ERR(spdif->regmap)) {
0378         dev_err(&pdev->dev, "regmap init failed\n");
0379         return PTR_ERR(spdif->regmap);
0380     }
0381
0382     spdif->playback_dma_data.addr = mem->start + TEGRA20_SPDIF_DATA_OUT;
0383     spdif->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
0384     spdif->playback_dma_data.maxburst = 4;
0385
0386     ret = devm_pm_runtime_enable(&pdev->dev);
0387     if (ret)
0388         return ret;
0389
0390     ret = devm_snd_soc_register_component(&pdev->dev,
0391                           &tegra20_spdif_component,
0392                           &tegra20_spdif_dai, 1);
0393     if (ret) {
0394         dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
0395         return ret;
0396     }
0397
0398     ret = devm_tegra_pcm_platform_register(&pdev->dev);
0399     if (ret) {
0400         dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
0401         return ret;
0402     }
0403
0404     return 0;
0405 }
0406
0407 static const struct dev_pm_ops tegra20_spdif_pm_ops = {
0408     SET_RUNTIME_PM_OPS(tegra20_spdif_runtime_suspend,
0409                tegra20_spdif_runtime_resume, NULL)
0410     SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
0411                 pm_runtime_force_resume)
0412 };
0413
0414 static const struct of_device_id tegra20_spdif_of_match[] = {
0415     { .compatible = "nvidia,tegra20-spdif", },
0416     {},
0417 };
0418 MODULE_DEVICE_TABLE(of, tegra20_spdif_of_match);
0419
0420 static struct platform_driver tegra20_spdif_driver = {
0421     .driver = {
0422         .name = "tegra20-spdif",
0423         .pm = &tegra20_spdif_pm_ops,
0424         .of_match_table = tegra20_spdif_of_match,
0425     },
0426     .probe = tegra20_spdif_platform_probe,
0427 };
0428 module_platform_driver(tegra20_spdif_driver);
0429
0430 MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
0431 MODULE_DESCRIPTION("Tegra20 SPDIF ASoC driver");
0432 MODULE_LICENSE("GPL");