soc/tegra/tegra20_ac97.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * tegra20_ac97.h - Definitions for the Tegra20 AC97 controller driver
0004  *
0005  * Copyright (c) 2012 Lucas Stach <dev@lynxeye.de>
0006  *
0007  * Partly based on code copyright/by:
0008  *
0009  * Copyright (c) 2011,2012 Toradex Inc.
0010  */
0011
0012 #ifndef __TEGRA20_AC97_H__
0013 #define __TEGRA20_AC97_H__
0014
0015 #include "tegra_pcm.h"
0016
0017 #define TEGRA20_AC97_CTRL               0x00
0018 #define TEGRA20_AC97_CMD                0x04
0019 #define TEGRA20_AC97_STATUS1                0x08
0020 /* ... */
0021 #define TEGRA20_AC97_FIFO1_SCR              0x1c
0022 /* ... */
0023 #define TEGRA20_AC97_FIFO_TX1               0x40
0024 #define TEGRA20_AC97_FIFO_RX1               0x80
0025
0026 /* TEGRA20_AC97_CTRL */
0027 #define TEGRA20_AC97_CTRL_STM2_EN           (1 << 16)
0028 #define TEGRA20_AC97_CTRL_DOUBLE_SAMPLING_EN        (1 << 11)
0029 #define TEGRA20_AC97_CTRL_IO_CNTRL_EN           (1 << 10)
0030 #define TEGRA20_AC97_CTRL_HSET_DAC_EN           (1 << 9)
0031 #define TEGRA20_AC97_CTRL_LINE2_DAC_EN          (1 << 8)
0032 #define TEGRA20_AC97_CTRL_PCM_LFE_EN            (1 << 7)
0033 #define TEGRA20_AC97_CTRL_PCM_SUR_EN            (1 << 6)
0034 #define TEGRA20_AC97_CTRL_PCM_CEN_DAC_EN        (1 << 5)
0035 #define TEGRA20_AC97_CTRL_LINE1_DAC_EN          (1 << 4)
0036 #define TEGRA20_AC97_CTRL_PCM_DAC_EN            (1 << 3)
0037 #define TEGRA20_AC97_CTRL_COLD_RESET            (1 << 2)
0038 #define TEGRA20_AC97_CTRL_WARM_RESET            (1 << 1)
0039 #define TEGRA20_AC97_CTRL_STM_EN            (1 << 0)
0040
0041 /* TEGRA20_AC97_CMD */
0042 #define TEGRA20_AC97_CMD_CMD_ADDR_SHIFT         24
0043 #define TEGRA20_AC97_CMD_CMD_ADDR_MASK          (0xff << TEGRA20_AC97_CMD_CMD_ADDR_SHIFT)
0044 #define TEGRA20_AC97_CMD_CMD_DATA_SHIFT         8
0045 #define TEGRA20_AC97_CMD_CMD_DATA_MASK          (0xffff << TEGRA20_AC97_CMD_CMD_DATA_SHIFT)
0046 #define TEGRA20_AC97_CMD_CMD_ID_SHIFT           2
0047 #define TEGRA20_AC97_CMD_CMD_ID_MASK            (0x3 << TEGRA20_AC97_CMD_CMD_ID_SHIFT)
0048 #define TEGRA20_AC97_CMD_BUSY               (1 << 0)
0049
0050 /* TEGRA20_AC97_STATUS1 */
0051 #define TEGRA20_AC97_STATUS1_STA_ADDR1_SHIFT        24
0052 #define TEGRA20_AC97_STATUS1_STA_ADDR1_MASK     (0xff << TEGRA20_AC97_STATUS1_STA_ADDR1_SHIFT)
0053 #define TEGRA20_AC97_STATUS1_STA_DATA1_SHIFT        8
0054 #define TEGRA20_AC97_STATUS1_STA_DATA1_MASK     (0xffff << TEGRA20_AC97_STATUS1_STA_DATA1_SHIFT)
0055 #define TEGRA20_AC97_STATUS1_STA_VALID1         (1 << 2)
0056 #define TEGRA20_AC97_STATUS1_STANDBY1           (1 << 1)
0057 #define TEGRA20_AC97_STATUS1_CODEC1_RDY         (1 << 0)
0058
0059 /* TEGRA20_AC97_FIFO1_SCR */
0060 #define TEGRA20_AC97_FIFO_SCR_REC_MT_CNT_SHIFT      27
0061 #define TEGRA20_AC97_FIFO_SCR_REC_MT_CNT_MASK       (0x1f << TEGRA20_AC97_FIFO_SCR_REC_MT_CNT_SHIFT)
0062 #define TEGRA20_AC97_FIFO_SCR_PB_MT_CNT_SHIFT       22
0063 #define TEGRA20_AC97_FIFO_SCR_PB_MT_CNT_MASK        (0x1f << TEGRA20_AC97_FIFO_SCR_PB_MT_CNT_SHIFT)
0064 #define TEGRA20_AC97_FIFO_SCR_REC_OVERRUN_INT_STA   (1 << 19)
0065 #define TEGRA20_AC97_FIFO_SCR_PB_UNDERRUN_INT_STA   (1 << 18)
0066 #define TEGRA20_AC97_FIFO_SCR_REC_FORCE_MT      (1 << 17)
0067 #define TEGRA20_AC97_FIFO_SCR_PB_FORCE_MT       (1 << 16)
0068 #define TEGRA20_AC97_FIFO_SCR_REC_FULL_EN       (1 << 15)
0069 #define TEGRA20_AC97_FIFO_SCR_REC_3QRT_FULL_EN      (1 << 14)
0070 #define TEGRA20_AC97_FIFO_SCR_REC_QRT_FULL_EN       (1 << 13)
0071 #define TEGRA20_AC97_FIFO_SCR_REC_EMPTY_EN      (1 << 12)
0072 #define TEGRA20_AC97_FIFO_SCR_PB_NOT_FULL_EN        (1 << 11)
0073 #define TEGRA20_AC97_FIFO_SCR_PB_QRT_MT_EN      (1 << 10)
0074 #define TEGRA20_AC97_FIFO_SCR_PB_3QRT_MT_EN     (1 << 9)
0075 #define TEGRA20_AC97_FIFO_SCR_PB_EMPTY_MT_EN        (1 << 8)
0076
0077 struct tegra20_ac97 {
0078     struct clk *clk_ac97;
0079     struct snd_dmaengine_dai_dma_data capture_dma_data;
0080     struct snd_dmaengine_dai_dma_data playback_dma_data;
0081     struct reset_control *reset;
0082     struct regmap *regmap;
0083     int reset_gpio;
0084     int sync_gpio;
0085 };
0086 #endif /* __TEGRA20_AC97_H__ */