soc/tegra/tegra20_ac97.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * tegra20_ac97.c - Tegra20 AC97 platform driver
0004  *
0005  * Copyright (c) 2012 Lucas Stach <dev@lynxeye.de>
0006  *
0007  * Partly based on code copyright/by:
0008  *
0009  * Copyright (c) 2011,2012 Toradex Inc.
0010  */
0011
0012 #include <linux/clk.h>
0013 #include <linux/delay.h>
0014 #include <linux/device.h>
0015 #include <linux/gpio.h>
0016 #include <linux/io.h>
0017 #include <linux/jiffies.h>
0018 #include <linux/module.h>
0019 #include <linux/of.h>
0020 #include <linux/of_gpio.h>
0021 #include <linux/platform_device.h>
0022 #include <linux/pm_runtime.h>
0023 #include <linux/regmap.h>
0024 #include <linux/reset.h>
0025 #include <linux/slab.h>
0026 #include <sound/core.h>
0027 #include <sound/pcm.h>
0028 #include <sound/pcm_params.h>
0029 #include <sound/soc.h>
0030 #include <sound/dmaengine_pcm.h>
0031
0032 #include "tegra20_ac97.h"
0033
0034 #define DRV_NAME "tegra20-ac97"
0035
0036 static struct tegra20_ac97 *workdata;
0037
0038 static void tegra20_ac97_codec_reset(struct snd_ac97 *ac97)
0039 {
0040     u32 readback;
0041     unsigned long timeout;
0042
0043     /* reset line is not driven by DAC pad group, have to toggle GPIO */
0044     gpio_set_value(workdata->reset_gpio, 0);
0045     udelay(2);
0046
0047     gpio_set_value(workdata->reset_gpio, 1);
0048     udelay(2);
0049
0050     timeout = jiffies + msecs_to_jiffies(100);
0051
0052     do {
0053         regmap_read(workdata->regmap, TEGRA20_AC97_STATUS1, &readback);
0054         if (readback & TEGRA20_AC97_STATUS1_CODEC1_RDY)
0055             break;
0056         usleep_range(1000, 2000);
0057     } while (!time_after(jiffies, timeout));
0058 }
0059
0060 static void tegra20_ac97_codec_warm_reset(struct snd_ac97 *ac97)
0061 {
0062     u32 readback;
0063     unsigned long timeout;
0064
0065     /*
0066      * although sync line is driven by the DAC pad group warm reset using
0067      * the controller cmd is not working, have to toggle sync line
0068      * manually.
0069      */
0070     gpio_request(workdata->sync_gpio, "codec-sync");
0071
0072     gpio_direction_output(workdata->sync_gpio, 1);
0073
0074     udelay(2);
0075     gpio_set_value(workdata->sync_gpio, 0);
0076     udelay(2);
0077     gpio_free(workdata->sync_gpio);
0078
0079     timeout = jiffies + msecs_to_jiffies(100);
0080
0081     do {
0082         regmap_read(workdata->regmap, TEGRA20_AC97_STATUS1, &readback);
0083         if (readback & TEGRA20_AC97_STATUS1_CODEC1_RDY)
0084             break;
0085         usleep_range(1000, 2000);
0086     } while (!time_after(jiffies, timeout));
0087 }
0088
0089 static unsigned short tegra20_ac97_codec_read(struct snd_ac97 *ac97_snd,
0090                           unsigned short reg)
0091 {
0092     u32 readback;
0093     unsigned long timeout;
0094
0095     regmap_write(workdata->regmap, TEGRA20_AC97_CMD,
0096              (((reg | 0x80) << TEGRA20_AC97_CMD_CMD_ADDR_SHIFT) &
0097               TEGRA20_AC97_CMD_CMD_ADDR_MASK) |
0098              TEGRA20_AC97_CMD_BUSY);
0099
0100     timeout = jiffies + msecs_to_jiffies(100);
0101
0102     do {
0103         regmap_read(workdata->regmap, TEGRA20_AC97_STATUS1, &readback);
0104         if (readback & TEGRA20_AC97_STATUS1_STA_VALID1)
0105             break;
0106         usleep_range(1000, 2000);
0107     } while (!time_after(jiffies, timeout));
0108
0109     return ((readback & TEGRA20_AC97_STATUS1_STA_DATA1_MASK) >>
0110         TEGRA20_AC97_STATUS1_STA_DATA1_SHIFT);
0111 }
0112
0113 static void tegra20_ac97_codec_write(struct snd_ac97 *ac97_snd,
0114                      unsigned short reg, unsigned short val)
0115 {
0116     u32 readback;
0117     unsigned long timeout;
0118
0119     regmap_write(workdata->regmap, TEGRA20_AC97_CMD,
0120              ((reg << TEGRA20_AC97_CMD_CMD_ADDR_SHIFT) &
0121               TEGRA20_AC97_CMD_CMD_ADDR_MASK) |
0122              ((val << TEGRA20_AC97_CMD_CMD_DATA_SHIFT) &
0123               TEGRA20_AC97_CMD_CMD_DATA_MASK) |
0124              TEGRA20_AC97_CMD_BUSY);
0125
0126     timeout = jiffies + msecs_to_jiffies(100);
0127
0128     do {
0129         regmap_read(workdata->regmap, TEGRA20_AC97_CMD, &readback);
0130         if (!(readback & TEGRA20_AC97_CMD_BUSY))
0131             break;
0132         usleep_range(1000, 2000);
0133     } while (!time_after(jiffies, timeout));
0134 }
0135
0136 static struct snd_ac97_bus_ops tegra20_ac97_ops = {
0137     .read       = tegra20_ac97_codec_read,
0138     .write      = tegra20_ac97_codec_write,
0139     .reset      = tegra20_ac97_codec_reset,
0140     .warm_reset = tegra20_ac97_codec_warm_reset,
0141 };
0142
0143 static inline void tegra20_ac97_start_playback(struct tegra20_ac97 *ac97)
0144 {
0145     regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR,
0146                TEGRA20_AC97_FIFO_SCR_PB_QRT_MT_EN,
0147                TEGRA20_AC97_FIFO_SCR_PB_QRT_MT_EN);
0148
0149     regmap_update_bits(ac97->regmap, TEGRA20_AC97_CTRL,
0150                TEGRA20_AC97_CTRL_PCM_DAC_EN |
0151                TEGRA20_AC97_CTRL_STM_EN,
0152                TEGRA20_AC97_CTRL_PCM_DAC_EN |
0153                TEGRA20_AC97_CTRL_STM_EN);
0154 }
0155
0156 static inline void tegra20_ac97_stop_playback(struct tegra20_ac97 *ac97)
0157 {
0158     regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR,
0159                TEGRA20_AC97_FIFO_SCR_PB_QRT_MT_EN, 0);
0160
0161     regmap_update_bits(ac97->regmap, TEGRA20_AC97_CTRL,
0162                TEGRA20_AC97_CTRL_PCM_DAC_EN, 0);
0163 }
0164
0165 static inline void tegra20_ac97_start_capture(struct tegra20_ac97 *ac97)
0166 {
0167     regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR,
0168                TEGRA20_AC97_FIFO_SCR_REC_FULL_EN,
0169                TEGRA20_AC97_FIFO_SCR_REC_FULL_EN);
0170 }
0171
0172 static inline void tegra20_ac97_stop_capture(struct tegra20_ac97 *ac97)
0173 {
0174     regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR,
0175                TEGRA20_AC97_FIFO_SCR_REC_FULL_EN, 0);
0176 }
0177
0178 static int tegra20_ac97_trigger(struct snd_pcm_substream *substream, int cmd,
0179                 struct snd_soc_dai *dai)
0180 {
0181     struct tegra20_ac97 *ac97 = snd_soc_dai_get_drvdata(dai);
0182
0183     switch (cmd) {
0184     case SNDRV_PCM_TRIGGER_START:
0185     case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
0186     case SNDRV_PCM_TRIGGER_RESUME:
0187         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
0188             tegra20_ac97_start_playback(ac97);
0189         else
0190             tegra20_ac97_start_capture(ac97);
0191         break;
0192     case SNDRV_PCM_TRIGGER_STOP:
0193     case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
0194     case SNDRV_PCM_TRIGGER_SUSPEND:
0195         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
0196             tegra20_ac97_stop_playback(ac97);
0197         else
0198             tegra20_ac97_stop_capture(ac97);
0199         break;
0200     default:
0201         return -EINVAL;
0202     }
0203
0204     return 0;
0205 }
0206
0207 static const struct snd_soc_dai_ops tegra20_ac97_dai_ops = {
0208     .trigger    = tegra20_ac97_trigger,
0209 };
0210
0211 static int tegra20_ac97_probe(struct snd_soc_dai *dai)
0212 {
0213     struct tegra20_ac97 *ac97 = snd_soc_dai_get_drvdata(dai);
0214
0215     dai->capture_dma_data = &ac97->capture_dma_data;
0216     dai->playback_dma_data = &ac97->playback_dma_data;
0217
0218     return 0;
0219 }
0220
0221 static struct snd_soc_dai_driver tegra20_ac97_dai = {
0222     .name = "tegra-ac97-pcm",
0223     .probe = tegra20_ac97_probe,
0224     .playback = {
0225         .stream_name = "PCM Playback",
0226         .channels_min = 2,
0227         .channels_max = 2,
0228         .rates = SNDRV_PCM_RATE_8000_48000,
0229         .formats = SNDRV_PCM_FMTBIT_S16_LE,
0230     },
0231     .capture = {
0232         .stream_name = "PCM Capture",
0233         .channels_min = 2,
0234         .channels_max = 2,
0235         .rates = SNDRV_PCM_RATE_8000_48000,
0236         .formats = SNDRV_PCM_FMTBIT_S16_LE,
0237     },
0238     .ops = &tegra20_ac97_dai_ops,
0239 };
0240
0241 static const struct snd_soc_component_driver tegra20_ac97_component = {
0242     .name           = DRV_NAME,
0243     .legacy_dai_naming  = 1,
0244 };
0245
0246 static bool tegra20_ac97_wr_rd_reg(struct device *dev, unsigned int reg)
0247 {
0248     switch (reg) {
0249     case TEGRA20_AC97_CTRL:
0250     case TEGRA20_AC97_CMD:
0251     case TEGRA20_AC97_STATUS1:
0252     case TEGRA20_AC97_FIFO1_SCR:
0253     case TEGRA20_AC97_FIFO_TX1:
0254     case TEGRA20_AC97_FIFO_RX1:
0255         return true;
0256     default:
0257         break;
0258     }
0259
0260     return false;
0261 }
0262
0263 static bool tegra20_ac97_volatile_reg(struct device *dev, unsigned int reg)
0264 {
0265     switch (reg) {
0266     case TEGRA20_AC97_STATUS1:
0267     case TEGRA20_AC97_FIFO1_SCR:
0268     case TEGRA20_AC97_FIFO_TX1:
0269     case TEGRA20_AC97_FIFO_RX1:
0270         return true;
0271     default:
0272         break;
0273     }
0274
0275     return false;
0276 }
0277
0278 static bool tegra20_ac97_precious_reg(struct device *dev, unsigned int reg)
0279 {
0280     switch (reg) {
0281     case TEGRA20_AC97_FIFO_TX1:
0282     case TEGRA20_AC97_FIFO_RX1:
0283         return true;
0284     default:
0285         break;
0286     }
0287
0288     return false;
0289 }
0290
0291 static const struct regmap_config tegra20_ac97_regmap_config = {
0292     .reg_bits = 32,
0293     .reg_stride = 4,
0294     .val_bits = 32,
0295     .max_register = TEGRA20_AC97_FIFO_RX1,
0296     .writeable_reg = tegra20_ac97_wr_rd_reg,
0297     .readable_reg = tegra20_ac97_wr_rd_reg,
0298     .volatile_reg = tegra20_ac97_volatile_reg,
0299     .precious_reg = tegra20_ac97_precious_reg,
0300     .cache_type = REGCACHE_FLAT,
0301 };
0302
0303 static int tegra20_ac97_platform_probe(struct platform_device *pdev)
0304 {
0305     struct tegra20_ac97 *ac97;
0306     struct resource *mem;
0307     void __iomem *regs;
0308     int ret = 0;
0309
0310     ac97 = devm_kzalloc(&pdev->dev, sizeof(struct tegra20_ac97),
0311                 GFP_KERNEL);
0312     if (!ac97) {
0313         ret = -ENOMEM;
0314         goto err;
0315     }
0316     dev_set_drvdata(&pdev->dev, ac97);
0317
0318     ac97->reset = devm_reset_control_get_exclusive(&pdev->dev, "ac97");
0319     if (IS_ERR(ac97->reset)) {
0320         dev_err(&pdev->dev, "Can't retrieve ac97 reset\n");
0321         return PTR_ERR(ac97->reset);
0322     }
0323
0324     ac97->clk_ac97 = devm_clk_get(&pdev->dev, NULL);
0325     if (IS_ERR(ac97->clk_ac97)) {
0326         dev_err(&pdev->dev, "Can't retrieve ac97 clock\n");
0327         ret = PTR_ERR(ac97->clk_ac97);
0328         goto err;
0329     }
0330
0331     mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0332     regs = devm_ioremap_resource(&pdev->dev, mem);
0333     if (IS_ERR(regs)) {
0334         ret = PTR_ERR(regs);
0335         goto err_clk_put;
0336     }
0337
0338     ac97->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
0339                         &tegra20_ac97_regmap_config);
0340     if (IS_ERR(ac97->regmap)) {
0341         dev_err(&pdev->dev, "regmap init failed\n");
0342         ret = PTR_ERR(ac97->regmap);
0343         goto err_clk_put;
0344     }
0345
0346     ac97->reset_gpio = of_get_named_gpio(pdev->dev.of_node,
0347                          "nvidia,codec-reset-gpio", 0);
0348     if (gpio_is_valid(ac97->reset_gpio)) {
0349         ret = devm_gpio_request_one(&pdev->dev, ac97->reset_gpio,
0350                         GPIOF_OUT_INIT_HIGH, "codec-reset");
0351         if (ret) {
0352             dev_err(&pdev->dev, "could not get codec-reset GPIO\n");
0353             goto err_clk_put;
0354         }
0355     } else {
0356         dev_err(&pdev->dev, "no codec-reset GPIO supplied\n");
0357         ret = -EINVAL;
0358         goto err_clk_put;
0359     }
0360
0361     ac97->sync_gpio = of_get_named_gpio(pdev->dev.of_node,
0362                         "nvidia,codec-sync-gpio", 0);
0363     if (!gpio_is_valid(ac97->sync_gpio)) {
0364         dev_err(&pdev->dev, "no codec-sync GPIO supplied\n");
0365         ret = -EINVAL;
0366         goto err_clk_put;
0367     }
0368
0369     ac97->capture_dma_data.addr = mem->start + TEGRA20_AC97_FIFO_RX1;
0370     ac97->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
0371     ac97->capture_dma_data.maxburst = 4;
0372
0373     ac97->playback_dma_data.addr = mem->start + TEGRA20_AC97_FIFO_TX1;
0374     ac97->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
0375     ac97->playback_dma_data.maxburst = 4;
0376
0377     ret = reset_control_assert(ac97->reset);
0378     if (ret) {
0379         dev_err(&pdev->dev, "Failed to assert AC'97 reset: %d\n", ret);
0380         goto err_clk_put;
0381     }
0382
0383     ret = clk_prepare_enable(ac97->clk_ac97);
0384     if (ret) {
0385         dev_err(&pdev->dev, "clk_enable failed: %d\n", ret);
0386         goto err_clk_put;
0387     }
0388
0389     usleep_range(10, 100);
0390
0391     ret = reset_control_deassert(ac97->reset);
0392     if (ret) {
0393         dev_err(&pdev->dev, "Failed to deassert AC'97 reset: %d\n", ret);
0394         goto err_clk_disable_unprepare;
0395     }
0396
0397     ret = snd_soc_set_ac97_ops(&tegra20_ac97_ops);
0398     if (ret) {
0399         dev_err(&pdev->dev, "Failed to set AC'97 ops: %d\n", ret);
0400         goto err_clk_disable_unprepare;
0401     }
0402
0403     ret = snd_soc_register_component(&pdev->dev, &tegra20_ac97_component,
0404                      &tegra20_ac97_dai, 1);
0405     if (ret) {
0406         dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
0407         ret = -ENOMEM;
0408         goto err_clk_disable_unprepare;
0409     }
0410
0411     ret = tegra_pcm_platform_register(&pdev->dev);
0412     if (ret) {
0413         dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
0414         goto err_unregister_component;
0415     }
0416
0417     /* XXX: crufty ASoC AC97 API - only one AC97 codec allowed */
0418     workdata = ac97;
0419
0420     return 0;
0421
0422 err_unregister_component:
0423     snd_soc_unregister_component(&pdev->dev);
0424 err_clk_disable_unprepare:
0425     clk_disable_unprepare(ac97->clk_ac97);
0426 err_clk_put:
0427 err:
0428     snd_soc_set_ac97_ops(NULL);
0429     return ret;
0430 }
0431
0432 static int tegra20_ac97_platform_remove(struct platform_device *pdev)
0433 {
0434     struct tegra20_ac97 *ac97 = dev_get_drvdata(&pdev->dev);
0435
0436     tegra_pcm_platform_unregister(&pdev->dev);
0437     snd_soc_unregister_component(&pdev->dev);
0438
0439     clk_disable_unprepare(ac97->clk_ac97);
0440
0441     snd_soc_set_ac97_ops(NULL);
0442
0443     return 0;
0444 }
0445
0446 static const struct of_device_id tegra20_ac97_of_match[] = {
0447     { .compatible = "nvidia,tegra20-ac97", },
0448     {},
0449 };
0450
0451 static struct platform_driver tegra20_ac97_driver = {
0452     .driver = {
0453         .name = DRV_NAME,
0454         .of_match_table = tegra20_ac97_of_match,
0455     },
0456     .probe = tegra20_ac97_platform_probe,
0457     .remove = tegra20_ac97_platform_remove,
0458 };
0459 module_platform_driver(tegra20_ac97_driver);
0460
0461 MODULE_AUTHOR("Lucas Stach");
0462 MODULE_DESCRIPTION("Tegra20 AC97 ASoC driver");
0463 MODULE_LICENSE("GPL v2");
0464 MODULE_ALIAS("platform:" DRV_NAME);
0465 MODULE_DEVICE_TABLE(of, tegra20_ac97_of_match);