soc/tegra/tegra186_dspk.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * tegra186_dspk.h - Definitions for Tegra186 DSPK driver
0004  *
0005  * Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved.
0006  *
0007  */
0008
0009 #ifndef __TEGRA186_DSPK_H__
0010 #define __TEGRA186_DSPK_H__
0011
0012 /* Register offsets from DSPK BASE */
0013 #define TEGRA186_DSPK_RX_STATUS         0x0c
0014 #define TEGRA186_DSPK_RX_INT_STATUS     0x10
0015 #define TEGRA186_DSPK_RX_INT_MASK       0x14
0016 #define TEGRA186_DSPK_RX_INT_SET        0x18
0017 #define TEGRA186_DSPK_RX_INT_CLEAR      0x1c
0018 #define TEGRA186_DSPK_RX_CIF_CTRL       0x20
0019 #define TEGRA186_DSPK_ENABLE            0x40
0020 #define TEGRA186_DSPK_SOFT_RESET        0x44
0021 #define TEGRA186_DSPK_CG            0x48
0022 #define TEGRA186_DSPK_STATUS            0x4c
0023 #define TEGRA186_DSPK_INT_STATUS        0x50
0024 #define TEGRA186_DSPK_CORE_CTRL         0x60
0025 #define TEGRA186_DSPK_CODEC_CTRL        0x64
0026
0027 /* DSPK CORE CONTROL fields */
0028 #define CH_SEL_SHIFT                8
0029 #define TEGRA186_DSPK_CHANNEL_SELECT_MASK   (0x3 << CH_SEL_SHIFT)
0030 #define DSPK_OSR_SHIFT              4
0031 #define TEGRA186_DSPK_OSR_MASK          (0x3 << DSPK_OSR_SHIFT)
0032 #define LRSEL_POL_SHIFT             0
0033 #define TEGRA186_DSPK_CTRL_LRSEL_POLARITY_MASK  (0x1 << LRSEL_POL_SHIFT)
0034 #define TEGRA186_DSPK_RX_FIFO_DEPTH     64
0035
0036 #define DSPK_OSR_FACTOR             32
0037
0038 /* DSPK interface clock ratio */
0039 #define DSPK_CLK_RATIO              4
0040
0041 enum tegra_dspk_osr {
0042     DSPK_OSR_32,
0043     DSPK_OSR_64,
0044     DSPK_OSR_128,
0045     DSPK_OSR_256,
0046 };
0047
0048 enum tegra_dspk_ch_sel {
0049     DSPK_CH_SELECT_LEFT,
0050     DSPK_CH_SELECT_RIGHT,
0051     DSPK_CH_SELECT_STEREO,
0052 };
0053
0054 enum tegra_dspk_lrsel {
0055     DSPK_LRSEL_LEFT,
0056     DSPK_LRSEL_RIGHT,
0057 };
0058
0059 struct tegra186_dspk {
0060     unsigned int rx_fifo_th;
0061     unsigned int osr_val;
0062     unsigned int lrsel;
0063     unsigned int ch_sel;
0064     unsigned int mono_to_stereo;
0065     unsigned int stereo_to_mono;
0066     struct clk *clk_dspk;
0067     struct regmap *regmap;
0068 };
0069
0070 #endif