soc/tegra/tegra186_asrc.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * tegra186_asrc.h - Definitions for Tegra186 ASRC driver
0004  *
0005  * Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
0006  *
0007  */
0008
0009 #ifndef __TEGRA186_ASRC_H__
0010 #define __TEGRA186_ASRC_H__
0011
0012 /* ASRC stream related offset */
0013 #define TEGRA186_ASRC_CFG               0x0
0014 #define TEGRA186_ASRC_RATIO_INT_PART            0x4
0015 #define TEGRA186_ASRC_RATIO_FRAC_PART           0x8
0016 #define TEGRA186_ASRC_RATIO_LOCK_STATUS         0xc
0017 #define TEGRA186_ASRC_MUTE_UNMUTE_DURATION      0x10
0018 #define TEGRA186_ASRC_TX_THRESHOLD          0x14
0019 #define TEGRA186_ASRC_RX_THRESHOLD          0x18
0020 #define TEGRA186_ASRC_RATIO_COMP            0x1c
0021 #define TEGRA186_ASRC_RX_STATUS             0x20
0022 #define TEGRA186_ASRC_RX_CIF_CTRL           0x24
0023 #define TEGRA186_ASRC_TX_STATUS             0x2c
0024 #define TEGRA186_ASRC_TX_CIF_CTRL           0x30
0025 #define TEGRA186_ASRC_ENABLE                0x38
0026 #define TEGRA186_ASRC_SOFT_RESET            0x3c
0027 #define TEGRA186_ASRC_STATUS                0x4c
0028 #define TEGRA186_ASRC_STATEBUF_ADDR         0x5c
0029 #define TEGRA186_ASRC_STATEBUF_CFG          0x60
0030 #define TEGRA186_ASRC_INSAMPLEBUF_ADDR          0x64
0031 #define TEGRA186_ASRC_INSAMPLEBUF_CFG           0x68
0032 #define TEGRA186_ASRC_OUTSAMPLEBUF_ADDR         0x6c
0033 #define TEGRA186_ASRC_OUTSAMPLEBUF_CFG          0x70
0034
0035 /* ASRC Global registers offset */
0036 #define TEGRA186_ASRC_GLOBAL_ENB            0x2f4
0037 #define TEGRA186_ASRC_GLOBAL_SOFT_RESET         0x2f8
0038 #define TEGRA186_ASRC_GLOBAL_CG             0x2fc
0039 #define TEGRA186_ASRC_GLOBAL_CFG            0x300
0040 #define TEGRA186_ASRC_GLOBAL_SCRATCH_ADDR       0x304
0041 #define TEGRA186_ASRC_GLOBAL_SCRATCH_CFG        0x308
0042 #define TEGRA186_ASRC_RATIO_UPD_RX_CIF_CTRL     0x30c
0043 #define TEGRA186_ASRC_RATIO_UPD_RX_STATUS       0x310
0044 #define TEGRA186_ASRC_GLOBAL_STATUS         0x314
0045 #define TEGRA186_ASRC_GLOBAL_STREAM_ENABLE_STATUS   0x318
0046 #define TEGRA186_ASRC_GLOBAL_INT_STATUS         0x324
0047 #define TEGRA186_ASRC_GLOBAL_INT_MASK           0x328
0048 #define TEGRA186_ASRC_GLOBAL_INT_SET            0x32c
0049 #define TEGRA186_ASRC_GLOBAL_INT_CLEAR          0x330
0050 #define TEGRA186_ASRC_GLOBAL_TRANSFER_ERROR_LOG     0x334
0051 #define TEGRA186_ASRC_GLOBAL_APR_CTRL           0x1000
0052 #define TEGRA186_ASRC_GLOBAL_APR_CTRL_ACCESS_CTRL   0x1004
0053 #define TEGRA186_ASRC_GLOBAL_DISARM_APR         0x1008
0054 #define TEGRA186_ASRC_GLOBAL_DISARM_APR_ACCESS_CTRL 0x100c
0055 #define TEGRA186_ASRC_GLOBAL_RATIO_WR_ACCESS        0x1010
0056 #define TEGRA186_ASRC_GLOBAL_RATIO_WR_ACCESS_CTRL   0x1014
0057 #define TEGRA186_ASRC_CYA               0x1018
0058
0059 #define TEGRA186_ASRC_STREAM_DEFAULT_HW_COMP_BIAS_VALUE     0xaaaa
0060 #define TEGRA186_ASRC_STREAM_DEFAULT_INPUT_HW_COMP_THRESH_CFG   0x00201002
0061 #define TEGRA186_ASRC_STREAM_DEFAULT_OUTPUT_HW_COMP_THRESH_CFG  0x00201002
0062
0063 #define TEGRA186_ASRC_GLOBAL_CFG_FRAC_28BIT_PRECISION       0
0064 #define TEGRA186_ASRC_GLOBAL_CFG_FRAC_32BIT_PRECISION       1
0065
0066 #define TEGRA186_ASRC_STREAM_ENABLE_HW_RATIO_COMP_SHIFT     31
0067 #define TEGRA186_ASRC_STREAM_ENABLE_HW_RATIO_COMP_MASK      (1 << TEGRA186_ASRC_STREAM_ENABLE_HW_RATIO_COMP_SHIFT)
0068 #define TEGRA186_ASRC_STREAM_ENABLE_HW_RATIO_COMP_ENABLE    (1 << TEGRA186_ASRC_STREAM_ENABLE_HW_RATIO_COMP_SHIFT)
0069 #define TEGRA186_ASRC_STREAM_ENABLE_HW_RATIO_COMP_DISABLE   (0 << TEGRA186_ASRC_STREAM_ENABLE_HW_RATIO_COMP_SHIFT)
0070
0071 #define TEGRA186_ASRC_STREAM_RATIO_TYPE_SHIFT           0
0072 #define TEGRA186_ASRC_STREAM_RATIO_TYPE_MASK            (1 << TEGRA186_ASRC_STREAM_RATIO_TYPE_SHIFT)
0073
0074 #define TEGRA186_ASRC_STREAM_EN_SHIFT               0
0075 #define TEGRA186_ASRC_STREAM_EN                 (1 << TEGRA186_ASRC_STREAM_EN_SHIFT)
0076 #define TEGRA186_ASRC_GLOBAL_EN_SHIFT               0
0077 #define TEGRA186_ASRC_GLOBAL_EN                 (1 << TEGRA186_ASRC_GLOBAL_EN_SHIFT)
0078
0079 #define TEGRA186_ASRC_STREAM_STATEBUF_CFG_SIZE_SHIFT        0
0080 #define TEGRA186_ASRC_STREAM_STATEBUF_CFG_SIZE_MASK     (0xffff << TEGRA186_ASRC_STREAM_STATEBUF_CFG_SIZE_SHIFT)
0081 #define TEGRA186_ASRC_STREAM_INSAMPLEBUF_CFG_SIZE_SHIFT     0
0082 #define TEGRA186_ASRC_STREAM_INSAMPLEBUF_CFG_SIZE_MASK      (0xffff << TEGRA186_ASRC_STREAM_INSAMPLEBUF_CFG_SIZE_SHIFT)
0083 #define TEGRA186_ASRC_STREAM_OUTSAMPLEBUF_CFG_SIZE_SHIFT    0
0084 #define TEGRA186_ASRC_STREAM_OUTSAMPLEBUF_CFG_SIZE_MASK     (0xffff << TEGRA186_ASRC_STREAM_OUTSAMPLEBUF_CFG_SIZE_SHIFT)
0085
0086 #define TEGRA186_ASRC_STREAM_RATIO_INT_PART_MASK        0x1f
0087 #define TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MASK       0xffffffff
0088
0089 #define TEGRA186_ASRC_STREAM_STRIDE             0x80
0090 #define TEGRA186_ASRC_STREAM_MAX                0x6
0091 #define TEGRA186_ASRC_STREAM_LIMIT              0x2f0
0092
0093 #define TEGRA186_ASRC_RATIO_SOURCE_ARAD             0x0
0094 #define TEGRA186_ASRC_RATIO_SOURCE_SW               0x1
0095
0096 #define TEGRA186_ASRC_ARAM_START_ADDR               0x3f800000
0097
0098 struct tegra186_asrc_lane {
0099     unsigned int int_part;
0100     unsigned int frac_part;
0101     unsigned int ratio_source;
0102     unsigned int hwcomp_disable;
0103     unsigned int input_thresh;
0104     unsigned int output_thresh;
0105 };
0106
0107 struct tegra186_asrc {
0108     struct tegra186_asrc_lane lane[TEGRA186_ASRC_STREAM_MAX];
0109     struct regmap *regmap;
0110 };
0111
0112 #endif