Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * STM32 ALSA SoC Digital Audio Interface (SPDIF-rx) driver.
0004  *
0005  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
0006  * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics.
0007  */
0008 
0009 #include <linux/bitfield.h>
0010 #include <linux/clk.h>
0011 #include <linux/completion.h>
0012 #include <linux/delay.h>
0013 #include <linux/module.h>
0014 #include <linux/of_platform.h>
0015 #include <linux/pm_runtime.h>
0016 #include <linux/regmap.h>
0017 #include <linux/reset.h>
0018 
0019 #include <sound/dmaengine_pcm.h>
0020 #include <sound/pcm_params.h>
0021 
0022 /* SPDIF-rx Register Map */
0023 #define STM32_SPDIFRX_CR    0x00
0024 #define STM32_SPDIFRX_IMR   0x04
0025 #define STM32_SPDIFRX_SR    0x08
0026 #define STM32_SPDIFRX_IFCR  0x0C
0027 #define STM32_SPDIFRX_DR    0x10
0028 #define STM32_SPDIFRX_CSR   0x14
0029 #define STM32_SPDIFRX_DIR   0x18
0030 #define STM32_SPDIFRX_VERR  0x3F4
0031 #define STM32_SPDIFRX_IDR   0x3F8
0032 #define STM32_SPDIFRX_SIDR  0x3FC
0033 
0034 /* Bit definition for SPDIF_CR register */
0035 #define SPDIFRX_CR_SPDIFEN_SHIFT    0
0036 #define SPDIFRX_CR_SPDIFEN_MASK GENMASK(1, SPDIFRX_CR_SPDIFEN_SHIFT)
0037 #define SPDIFRX_CR_SPDIFENSET(x)    ((x) << SPDIFRX_CR_SPDIFEN_SHIFT)
0038 
0039 #define SPDIFRX_CR_RXDMAEN  BIT(2)
0040 #define SPDIFRX_CR_RXSTEO   BIT(3)
0041 
0042 #define SPDIFRX_CR_DRFMT_SHIFT  4
0043 #define SPDIFRX_CR_DRFMT_MASK   GENMASK(5, SPDIFRX_CR_DRFMT_SHIFT)
0044 #define SPDIFRX_CR_DRFMTSET(x)  ((x) << SPDIFRX_CR_DRFMT_SHIFT)
0045 
0046 #define SPDIFRX_CR_PMSK     BIT(6)
0047 #define SPDIFRX_CR_VMSK     BIT(7)
0048 #define SPDIFRX_CR_CUMSK    BIT(8)
0049 #define SPDIFRX_CR_PTMSK    BIT(9)
0050 #define SPDIFRX_CR_CBDMAEN  BIT(10)
0051 #define SPDIFRX_CR_CHSEL_SHIFT  11
0052 #define SPDIFRX_CR_CHSEL    BIT(SPDIFRX_CR_CHSEL_SHIFT)
0053 
0054 #define SPDIFRX_CR_NBTR_SHIFT   12
0055 #define SPDIFRX_CR_NBTR_MASK    GENMASK(13, SPDIFRX_CR_NBTR_SHIFT)
0056 #define SPDIFRX_CR_NBTRSET(x)   ((x) << SPDIFRX_CR_NBTR_SHIFT)
0057 
0058 #define SPDIFRX_CR_WFA      BIT(14)
0059 
0060 #define SPDIFRX_CR_INSEL_SHIFT  16
0061 #define SPDIFRX_CR_INSEL_MASK   GENMASK(18, PDIFRX_CR_INSEL_SHIFT)
0062 #define SPDIFRX_CR_INSELSET(x)  ((x) << SPDIFRX_CR_INSEL_SHIFT)
0063 
0064 #define SPDIFRX_CR_CKSEN_SHIFT  20
0065 #define SPDIFRX_CR_CKSEN    BIT(20)
0066 #define SPDIFRX_CR_CKSBKPEN BIT(21)
0067 
0068 /* Bit definition for SPDIFRX_IMR register */
0069 #define SPDIFRX_IMR_RXNEI   BIT(0)
0070 #define SPDIFRX_IMR_CSRNEIE BIT(1)
0071 #define SPDIFRX_IMR_PERRIE  BIT(2)
0072 #define SPDIFRX_IMR_OVRIE   BIT(3)
0073 #define SPDIFRX_IMR_SBLKIE  BIT(4)
0074 #define SPDIFRX_IMR_SYNCDIE BIT(5)
0075 #define SPDIFRX_IMR_IFEIE   BIT(6)
0076 
0077 #define SPDIFRX_XIMR_MASK   GENMASK(6, 0)
0078 
0079 /* Bit definition for SPDIFRX_SR register */
0080 #define SPDIFRX_SR_RXNE     BIT(0)
0081 #define SPDIFRX_SR_CSRNE    BIT(1)
0082 #define SPDIFRX_SR_PERR     BIT(2)
0083 #define SPDIFRX_SR_OVR      BIT(3)
0084 #define SPDIFRX_SR_SBD      BIT(4)
0085 #define SPDIFRX_SR_SYNCD    BIT(5)
0086 #define SPDIFRX_SR_FERR     BIT(6)
0087 #define SPDIFRX_SR_SERR     BIT(7)
0088 #define SPDIFRX_SR_TERR     BIT(8)
0089 
0090 #define SPDIFRX_SR_WIDTH5_SHIFT 16
0091 #define SPDIFRX_SR_WIDTH5_MASK  GENMASK(30, PDIFRX_SR_WIDTH5_SHIFT)
0092 #define SPDIFRX_SR_WIDTH5SET(x) ((x) << SPDIFRX_SR_WIDTH5_SHIFT)
0093 
0094 /* Bit definition for SPDIFRX_IFCR register */
0095 #define SPDIFRX_IFCR_PERRCF BIT(2)
0096 #define SPDIFRX_IFCR_OVRCF  BIT(3)
0097 #define SPDIFRX_IFCR_SBDCF  BIT(4)
0098 #define SPDIFRX_IFCR_SYNCDCF    BIT(5)
0099 
0100 #define SPDIFRX_XIFCR_MASK  GENMASK(5, 2)
0101 
0102 /* Bit definition for SPDIFRX_DR register (DRFMT = 0b00) */
0103 #define SPDIFRX_DR0_DR_SHIFT    0
0104 #define SPDIFRX_DR0_DR_MASK GENMASK(23, SPDIFRX_DR0_DR_SHIFT)
0105 #define SPDIFRX_DR0_DRSET(x)    ((x) << SPDIFRX_DR0_DR_SHIFT)
0106 
0107 #define SPDIFRX_DR0_PE      BIT(24)
0108 
0109 #define SPDIFRX_DR0_V       BIT(25)
0110 #define SPDIFRX_DR0_U       BIT(26)
0111 #define SPDIFRX_DR0_C       BIT(27)
0112 
0113 #define SPDIFRX_DR0_PT_SHIFT    28
0114 #define SPDIFRX_DR0_PT_MASK GENMASK(29, SPDIFRX_DR0_PT_SHIFT)
0115 #define SPDIFRX_DR0_PTSET(x)    ((x) << SPDIFRX_DR0_PT_SHIFT)
0116 
0117 /* Bit definition for SPDIFRX_DR register (DRFMT = 0b01) */
0118 #define  SPDIFRX_DR1_PE     BIT(0)
0119 #define  SPDIFRX_DR1_V      BIT(1)
0120 #define  SPDIFRX_DR1_U      BIT(2)
0121 #define  SPDIFRX_DR1_C      BIT(3)
0122 
0123 #define  SPDIFRX_DR1_PT_SHIFT   4
0124 #define  SPDIFRX_DR1_PT_MASK    GENMASK(5, SPDIFRX_DR1_PT_SHIFT)
0125 #define  SPDIFRX_DR1_PTSET(x)   ((x) << SPDIFRX_DR1_PT_SHIFT)
0126 
0127 #define SPDIFRX_DR1_DR_SHIFT    8
0128 #define SPDIFRX_DR1_DR_MASK GENMASK(31, SPDIFRX_DR1_DR_SHIFT)
0129 #define SPDIFRX_DR1_DRSET(x)    ((x) << SPDIFRX_DR1_DR_SHIFT)
0130 
0131 /* Bit definition for SPDIFRX_DR register (DRFMT = 0b10) */
0132 #define SPDIFRX_DR1_DRNL1_SHIFT 0
0133 #define SPDIFRX_DR1_DRNL1_MASK  GENMASK(15, SPDIFRX_DR1_DRNL1_SHIFT)
0134 #define SPDIFRX_DR1_DRNL1SET(x) ((x) << SPDIFRX_DR1_DRNL1_SHIFT)
0135 
0136 #define SPDIFRX_DR1_DRNL2_SHIFT 16
0137 #define SPDIFRX_DR1_DRNL2_MASK  GENMASK(31, SPDIFRX_DR1_DRNL2_SHIFT)
0138 #define SPDIFRX_DR1_DRNL2SET(x) ((x) << SPDIFRX_DR1_DRNL2_SHIFT)
0139 
0140 /* Bit definition for SPDIFRX_CSR register */
0141 #define SPDIFRX_CSR_USR_SHIFT   0
0142 #define SPDIFRX_CSR_USR_MASK    GENMASK(15, SPDIFRX_CSR_USR_SHIFT)
0143 #define SPDIFRX_CSR_USRGET(x)   (((x) & SPDIFRX_CSR_USR_MASK)\
0144                 >> SPDIFRX_CSR_USR_SHIFT)
0145 
0146 #define SPDIFRX_CSR_CS_SHIFT    16
0147 #define SPDIFRX_CSR_CS_MASK GENMASK(23, SPDIFRX_CSR_CS_SHIFT)
0148 #define SPDIFRX_CSR_CSGET(x)    (((x) & SPDIFRX_CSR_CS_MASK)\
0149                 >> SPDIFRX_CSR_CS_SHIFT)
0150 
0151 #define SPDIFRX_CSR_SOB     BIT(24)
0152 
0153 /* Bit definition for SPDIFRX_DIR register */
0154 #define SPDIFRX_DIR_THI_SHIFT   0
0155 #define SPDIFRX_DIR_THI_MASK    GENMASK(12, SPDIFRX_DIR_THI_SHIFT)
0156 #define SPDIFRX_DIR_THI_SET(x)  ((x) << SPDIFRX_DIR_THI_SHIFT)
0157 
0158 #define SPDIFRX_DIR_TLO_SHIFT   16
0159 #define SPDIFRX_DIR_TLO_MASK    GENMASK(28, SPDIFRX_DIR_TLO_SHIFT)
0160 #define SPDIFRX_DIR_TLO_SET(x)  ((x) << SPDIFRX_DIR_TLO_SHIFT)
0161 
0162 #define SPDIFRX_SPDIFEN_DISABLE 0x0
0163 #define SPDIFRX_SPDIFEN_SYNC    0x1
0164 #define SPDIFRX_SPDIFEN_ENABLE  0x3
0165 
0166 /* Bit definition for SPDIFRX_VERR register */
0167 #define SPDIFRX_VERR_MIN_MASK   GENMASK(3, 0)
0168 #define SPDIFRX_VERR_MAJ_MASK   GENMASK(7, 4)
0169 
0170 /* Bit definition for SPDIFRX_IDR register */
0171 #define SPDIFRX_IDR_ID_MASK GENMASK(31, 0)
0172 
0173 /* Bit definition for SPDIFRX_SIDR register */
0174 #define SPDIFRX_SIDR_SID_MASK   GENMASK(31, 0)
0175 
0176 #define SPDIFRX_IPIDR_NUMBER    0x00130041
0177 
0178 #define SPDIFRX_IN1     0x1
0179 #define SPDIFRX_IN2     0x2
0180 #define SPDIFRX_IN3     0x3
0181 #define SPDIFRX_IN4     0x4
0182 #define SPDIFRX_IN5     0x5
0183 #define SPDIFRX_IN6     0x6
0184 #define SPDIFRX_IN7     0x7
0185 #define SPDIFRX_IN8     0x8
0186 
0187 #define SPDIFRX_NBTR_NONE   0x0
0188 #define SPDIFRX_NBTR_3      0x1
0189 #define SPDIFRX_NBTR_15     0x2
0190 #define SPDIFRX_NBTR_63     0x3
0191 
0192 #define SPDIFRX_DRFMT_RIGHT 0x0
0193 #define SPDIFRX_DRFMT_LEFT  0x1
0194 #define SPDIFRX_DRFMT_PACKED    0x2
0195 
0196 /* 192 CS bits in S/PDIF frame. i.e 24 CS bytes */
0197 #define SPDIFRX_CS_BYTES_NB 24
0198 #define SPDIFRX_UB_BYTES_NB 48
0199 
0200 /*
0201  * CSR register is retrieved as a 32 bits word
0202  * It contains 1 channel status byte and 2 user data bytes
0203  * 2 S/PDIF frames are acquired to get all CS/UB bits
0204  */
0205 #define SPDIFRX_CSR_BUF_LENGTH  (SPDIFRX_CS_BYTES_NB * 4 * 2)
0206 
0207 /**
0208  * struct stm32_spdifrx_data - private data of SPDIFRX
0209  * @pdev: device data pointer
0210  * @base: mmio register base virtual address
0211  * @regmap: SPDIFRX register map pointer
0212  * @regmap_conf: SPDIFRX register map configuration pointer
0213  * @cs_completion: channel status retrieving completion
0214  * @kclk: kernel clock feeding the SPDIFRX clock generator
0215  * @dma_params: dma configuration data for rx channel
0216  * @substream: PCM substream data pointer
0217  * @dmab: dma buffer info pointer
0218  * @ctrl_chan: dma channel for S/PDIF control bits
0219  * @desc:dma async transaction descriptor
0220  * @slave_config: dma slave channel runtime config pointer
0221  * @phys_addr: SPDIFRX registers physical base address
0222  * @lock: synchronization enabling lock
0223  * @irq_lock: prevent race condition with IRQ on stream state
0224  * @cs: channel status buffer
0225  * @ub: user data buffer
0226  * @irq: SPDIFRX interrupt line
0227  * @refcount: keep count of opened DMA channels
0228  */
0229 struct stm32_spdifrx_data {
0230     struct platform_device *pdev;
0231     void __iomem *base;
0232     struct regmap *regmap;
0233     const struct regmap_config *regmap_conf;
0234     struct completion cs_completion;
0235     struct clk *kclk;
0236     struct snd_dmaengine_dai_dma_data dma_params;
0237     struct snd_pcm_substream *substream;
0238     struct snd_dma_buffer *dmab;
0239     struct dma_chan *ctrl_chan;
0240     struct dma_async_tx_descriptor *desc;
0241     struct dma_slave_config slave_config;
0242     dma_addr_t phys_addr;
0243     spinlock_t lock;  /* Sync enabling lock */
0244     spinlock_t irq_lock; /* Prevent race condition on stream state */
0245     unsigned char cs[SPDIFRX_CS_BYTES_NB];
0246     unsigned char ub[SPDIFRX_UB_BYTES_NB];
0247     int irq;
0248     int refcount;
0249 };
0250 
0251 static void stm32_spdifrx_dma_complete(void *data)
0252 {
0253     struct stm32_spdifrx_data *spdifrx = (struct stm32_spdifrx_data *)data;
0254     struct platform_device *pdev = spdifrx->pdev;
0255     u32 *p_start = (u32 *)spdifrx->dmab->area;
0256     u32 *p_end = p_start + (2 * SPDIFRX_CS_BYTES_NB) - 1;
0257     u32 *ptr = p_start;
0258     u16 *ub_ptr = (short *)spdifrx->ub;
0259     int i = 0;
0260 
0261     regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
0262                SPDIFRX_CR_CBDMAEN,
0263                (unsigned int)~SPDIFRX_CR_CBDMAEN);
0264 
0265     if (!spdifrx->dmab->area)
0266         return;
0267 
0268     while (ptr <= p_end) {
0269         if (*ptr & SPDIFRX_CSR_SOB)
0270             break;
0271         ptr++;
0272     }
0273 
0274     if (ptr > p_end) {
0275         dev_err(&pdev->dev, "Start of S/PDIF block not found\n");
0276         return;
0277     }
0278 
0279     while (i < SPDIFRX_CS_BYTES_NB) {
0280         spdifrx->cs[i] = (unsigned char)SPDIFRX_CSR_CSGET(*ptr);
0281         *ub_ptr++ = SPDIFRX_CSR_USRGET(*ptr++);
0282         if (ptr > p_end) {
0283             dev_err(&pdev->dev, "Failed to get channel status\n");
0284             return;
0285         }
0286         i++;
0287     }
0288 
0289     complete(&spdifrx->cs_completion);
0290 }
0291 
0292 static int stm32_spdifrx_dma_ctrl_start(struct stm32_spdifrx_data *spdifrx)
0293 {
0294     dma_cookie_t cookie;
0295     int err;
0296 
0297     spdifrx->desc = dmaengine_prep_slave_single(spdifrx->ctrl_chan,
0298                             spdifrx->dmab->addr,
0299                             SPDIFRX_CSR_BUF_LENGTH,
0300                             DMA_DEV_TO_MEM,
0301                             DMA_CTRL_ACK);
0302     if (!spdifrx->desc)
0303         return -EINVAL;
0304 
0305     spdifrx->desc->callback = stm32_spdifrx_dma_complete;
0306     spdifrx->desc->callback_param = spdifrx;
0307     cookie = dmaengine_submit(spdifrx->desc);
0308     err = dma_submit_error(cookie);
0309     if (err)
0310         return -EINVAL;
0311 
0312     dma_async_issue_pending(spdifrx->ctrl_chan);
0313 
0314     return 0;
0315 }
0316 
0317 static void stm32_spdifrx_dma_ctrl_stop(struct stm32_spdifrx_data *spdifrx)
0318 {
0319     dmaengine_terminate_async(spdifrx->ctrl_chan);
0320 }
0321 
0322 static int stm32_spdifrx_start_sync(struct stm32_spdifrx_data *spdifrx)
0323 {
0324     int cr, cr_mask, imr, ret;
0325     unsigned long flags;
0326 
0327     /* Enable IRQs */
0328     imr = SPDIFRX_IMR_IFEIE | SPDIFRX_IMR_SYNCDIE | SPDIFRX_IMR_PERRIE;
0329     ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR, imr, imr);
0330     if (ret)
0331         return ret;
0332 
0333     spin_lock_irqsave(&spdifrx->lock, flags);
0334 
0335     spdifrx->refcount++;
0336 
0337     regmap_read(spdifrx->regmap, STM32_SPDIFRX_CR, &cr);
0338 
0339     if (!(cr & SPDIFRX_CR_SPDIFEN_MASK)) {
0340         /*
0341          * Start sync if SPDIFRX is still in idle state.
0342          * SPDIFRX reception enabled when sync done
0343          */
0344         dev_dbg(&spdifrx->pdev->dev, "start synchronization\n");
0345 
0346         /*
0347          * SPDIFRX configuration:
0348          * Wait for activity before starting sync process. This avoid
0349          * to issue sync errors when spdif signal is missing on input.
0350          * Preamble, CS, user, validity and parity error bits not copied
0351          * to DR register.
0352          */
0353         cr = SPDIFRX_CR_WFA | SPDIFRX_CR_PMSK | SPDIFRX_CR_VMSK |
0354              SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK | SPDIFRX_CR_RXSTEO;
0355         cr_mask = cr;
0356 
0357         cr |= SPDIFRX_CR_NBTRSET(SPDIFRX_NBTR_63);
0358         cr_mask |= SPDIFRX_CR_NBTR_MASK;
0359         cr |= SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_SYNC);
0360         cr_mask |= SPDIFRX_CR_SPDIFEN_MASK;
0361         ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
0362                      cr_mask, cr);
0363         if (ret < 0)
0364             dev_err(&spdifrx->pdev->dev,
0365                 "Failed to start synchronization\n");
0366     }
0367 
0368     spin_unlock_irqrestore(&spdifrx->lock, flags);
0369 
0370     return ret;
0371 }
0372 
0373 static void stm32_spdifrx_stop(struct stm32_spdifrx_data *spdifrx)
0374 {
0375     int cr, cr_mask, reg;
0376     unsigned long flags;
0377 
0378     spin_lock_irqsave(&spdifrx->lock, flags);
0379 
0380     if (--spdifrx->refcount) {
0381         spin_unlock_irqrestore(&spdifrx->lock, flags);
0382         return;
0383     }
0384 
0385     cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_DISABLE);
0386     cr_mask = SPDIFRX_CR_SPDIFEN_MASK | SPDIFRX_CR_RXDMAEN;
0387 
0388     regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, cr_mask, cr);
0389 
0390     regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR,
0391                SPDIFRX_XIMR_MASK, 0);
0392 
0393     regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IFCR,
0394                SPDIFRX_XIFCR_MASK, SPDIFRX_XIFCR_MASK);
0395 
0396     /* dummy read to clear CSRNE and RXNE in status register */
0397     regmap_read(spdifrx->regmap, STM32_SPDIFRX_DR, &reg);
0398     regmap_read(spdifrx->regmap, STM32_SPDIFRX_CSR, &reg);
0399 
0400     spin_unlock_irqrestore(&spdifrx->lock, flags);
0401 }
0402 
0403 static int stm32_spdifrx_dma_ctrl_register(struct device *dev,
0404                        struct stm32_spdifrx_data *spdifrx)
0405 {
0406     int ret;
0407 
0408     spdifrx->ctrl_chan = dma_request_chan(dev, "rx-ctrl");
0409     if (IS_ERR(spdifrx->ctrl_chan))
0410         return dev_err_probe(dev, PTR_ERR(spdifrx->ctrl_chan),
0411                      "dma_request_slave_channel error\n");
0412 
0413     spdifrx->dmab = devm_kzalloc(dev, sizeof(struct snd_dma_buffer),
0414                      GFP_KERNEL);
0415     if (!spdifrx->dmab)
0416         return -ENOMEM;
0417 
0418     spdifrx->dmab->dev.type = SNDRV_DMA_TYPE_DEV_IRAM;
0419     spdifrx->dmab->dev.dev = dev;
0420     ret = snd_dma_alloc_pages(spdifrx->dmab->dev.type, dev,
0421                   SPDIFRX_CSR_BUF_LENGTH, spdifrx->dmab);
0422     if (ret < 0) {
0423         dev_err(dev, "snd_dma_alloc_pages returned error %d\n", ret);
0424         return ret;
0425     }
0426 
0427     spdifrx->slave_config.direction = DMA_DEV_TO_MEM;
0428     spdifrx->slave_config.src_addr = (dma_addr_t)(spdifrx->phys_addr +
0429                      STM32_SPDIFRX_CSR);
0430     spdifrx->slave_config.dst_addr = spdifrx->dmab->addr;
0431     spdifrx->slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
0432     spdifrx->slave_config.src_maxburst = 1;
0433 
0434     ret = dmaengine_slave_config(spdifrx->ctrl_chan,
0435                      &spdifrx->slave_config);
0436     if (ret < 0) {
0437         dev_err(dev, "dmaengine_slave_config returned error %d\n", ret);
0438         spdifrx->ctrl_chan = NULL;
0439     }
0440 
0441     return ret;
0442 };
0443 
0444 static const char * const spdifrx_enum_input[] = {
0445     "in0", "in1", "in2", "in3"
0446 };
0447 
0448 /*  By default CS bits are retrieved from channel A */
0449 static const char * const spdifrx_enum_cs_channel[] = {
0450     "A", "B"
0451 };
0452 
0453 static SOC_ENUM_SINGLE_DECL(ctrl_enum_input,
0454                 STM32_SPDIFRX_CR, SPDIFRX_CR_INSEL_SHIFT,
0455                 spdifrx_enum_input);
0456 
0457 static SOC_ENUM_SINGLE_DECL(ctrl_enum_cs_channel,
0458                 STM32_SPDIFRX_CR, SPDIFRX_CR_CHSEL_SHIFT,
0459                 spdifrx_enum_cs_channel);
0460 
0461 static int stm32_spdifrx_info(struct snd_kcontrol *kcontrol,
0462                   struct snd_ctl_elem_info *uinfo)
0463 {
0464     uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
0465     uinfo->count = 1;
0466 
0467     return 0;
0468 }
0469 
0470 static int stm32_spdifrx_ub_info(struct snd_kcontrol *kcontrol,
0471                  struct snd_ctl_elem_info *uinfo)
0472 {
0473     uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
0474     uinfo->count = 1;
0475 
0476     return 0;
0477 }
0478 
0479 static int stm32_spdifrx_get_ctrl_data(struct stm32_spdifrx_data *spdifrx)
0480 {
0481     int ret = 0;
0482 
0483     memset(spdifrx->cs, 0, SPDIFRX_CS_BYTES_NB);
0484     memset(spdifrx->ub, 0, SPDIFRX_UB_BYTES_NB);
0485 
0486     ret = stm32_spdifrx_dma_ctrl_start(spdifrx);
0487     if (ret < 0)
0488         return ret;
0489 
0490     ret = clk_prepare_enable(spdifrx->kclk);
0491     if (ret) {
0492         dev_err(&spdifrx->pdev->dev, "Enable kclk failed: %d\n", ret);
0493         return ret;
0494     }
0495 
0496     ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
0497                  SPDIFRX_CR_CBDMAEN, SPDIFRX_CR_CBDMAEN);
0498     if (ret < 0)
0499         goto end;
0500 
0501     ret = stm32_spdifrx_start_sync(spdifrx);
0502     if (ret < 0)
0503         goto end;
0504 
0505     if (wait_for_completion_interruptible_timeout(&spdifrx->cs_completion,
0506                               msecs_to_jiffies(100))
0507                               <= 0) {
0508         dev_dbg(&spdifrx->pdev->dev, "Failed to get control data\n");
0509         ret = -EAGAIN;
0510     }
0511 
0512     stm32_spdifrx_stop(spdifrx);
0513     stm32_spdifrx_dma_ctrl_stop(spdifrx);
0514 
0515 end:
0516     clk_disable_unprepare(spdifrx->kclk);
0517 
0518     return ret;
0519 }
0520 
0521 static int stm32_spdifrx_capture_get(struct snd_kcontrol *kcontrol,
0522                      struct snd_ctl_elem_value *ucontrol)
0523 {
0524     struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
0525     struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
0526 
0527     stm32_spdifrx_get_ctrl_data(spdifrx);
0528 
0529     ucontrol->value.iec958.status[0] = spdifrx->cs[0];
0530     ucontrol->value.iec958.status[1] = spdifrx->cs[1];
0531     ucontrol->value.iec958.status[2] = spdifrx->cs[2];
0532     ucontrol->value.iec958.status[3] = spdifrx->cs[3];
0533     ucontrol->value.iec958.status[4] = spdifrx->cs[4];
0534 
0535     return 0;
0536 }
0537 
0538 static int stm32_spdif_user_bits_get(struct snd_kcontrol *kcontrol,
0539                      struct snd_ctl_elem_value *ucontrol)
0540 {
0541     struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
0542     struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
0543 
0544     stm32_spdifrx_get_ctrl_data(spdifrx);
0545 
0546     ucontrol->value.iec958.status[0] = spdifrx->ub[0];
0547     ucontrol->value.iec958.status[1] = spdifrx->ub[1];
0548     ucontrol->value.iec958.status[2] = spdifrx->ub[2];
0549     ucontrol->value.iec958.status[3] = spdifrx->ub[3];
0550     ucontrol->value.iec958.status[4] = spdifrx->ub[4];
0551 
0552     return 0;
0553 }
0554 
0555 static struct snd_kcontrol_new stm32_spdifrx_iec_ctrls[] = {
0556     /* Channel status control */
0557     {
0558         .iface = SNDRV_CTL_ELEM_IFACE_PCM,
0559         .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT),
0560         .access = SNDRV_CTL_ELEM_ACCESS_READ |
0561               SNDRV_CTL_ELEM_ACCESS_VOLATILE,
0562         .info = stm32_spdifrx_info,
0563         .get = stm32_spdifrx_capture_get,
0564     },
0565     /* User bits control */
0566     {
0567         .iface = SNDRV_CTL_ELEM_IFACE_PCM,
0568         .name = "IEC958 User Bit Capture Default",
0569         .access = SNDRV_CTL_ELEM_ACCESS_READ |
0570               SNDRV_CTL_ELEM_ACCESS_VOLATILE,
0571         .info = stm32_spdifrx_ub_info,
0572         .get = stm32_spdif_user_bits_get,
0573     },
0574 };
0575 
0576 static struct snd_kcontrol_new stm32_spdifrx_ctrls[] = {
0577     SOC_ENUM("SPDIFRX input", ctrl_enum_input),
0578     SOC_ENUM("SPDIFRX CS channel", ctrl_enum_cs_channel),
0579 };
0580 
0581 static int stm32_spdifrx_dai_register_ctrls(struct snd_soc_dai *cpu_dai)
0582 {
0583     int ret;
0584 
0585     ret = snd_soc_add_dai_controls(cpu_dai, stm32_spdifrx_iec_ctrls,
0586                        ARRAY_SIZE(stm32_spdifrx_iec_ctrls));
0587     if (ret < 0)
0588         return ret;
0589 
0590     return snd_soc_add_component_controls(cpu_dai->component,
0591                           stm32_spdifrx_ctrls,
0592                           ARRAY_SIZE(stm32_spdifrx_ctrls));
0593 }
0594 
0595 static int stm32_spdifrx_dai_probe(struct snd_soc_dai *cpu_dai)
0596 {
0597     struct stm32_spdifrx_data *spdifrx = dev_get_drvdata(cpu_dai->dev);
0598 
0599     spdifrx->dma_params.addr = (dma_addr_t)(spdifrx->phys_addr +
0600                    STM32_SPDIFRX_DR);
0601     spdifrx->dma_params.maxburst = 1;
0602 
0603     snd_soc_dai_init_dma_data(cpu_dai, NULL, &spdifrx->dma_params);
0604 
0605     return stm32_spdifrx_dai_register_ctrls(cpu_dai);
0606 }
0607 
0608 static bool stm32_spdifrx_readable_reg(struct device *dev, unsigned int reg)
0609 {
0610     switch (reg) {
0611     case STM32_SPDIFRX_CR:
0612     case STM32_SPDIFRX_IMR:
0613     case STM32_SPDIFRX_SR:
0614     case STM32_SPDIFRX_IFCR:
0615     case STM32_SPDIFRX_DR:
0616     case STM32_SPDIFRX_CSR:
0617     case STM32_SPDIFRX_DIR:
0618     case STM32_SPDIFRX_VERR:
0619     case STM32_SPDIFRX_IDR:
0620     case STM32_SPDIFRX_SIDR:
0621         return true;
0622     default:
0623         return false;
0624     }
0625 }
0626 
0627 static bool stm32_spdifrx_volatile_reg(struct device *dev, unsigned int reg)
0628 {
0629     switch (reg) {
0630     case STM32_SPDIFRX_DR:
0631     case STM32_SPDIFRX_CSR:
0632     case STM32_SPDIFRX_SR:
0633     case STM32_SPDIFRX_DIR:
0634         return true;
0635     default:
0636         return false;
0637     }
0638 }
0639 
0640 static bool stm32_spdifrx_writeable_reg(struct device *dev, unsigned int reg)
0641 {
0642     switch (reg) {
0643     case STM32_SPDIFRX_CR:
0644     case STM32_SPDIFRX_IMR:
0645     case STM32_SPDIFRX_IFCR:
0646         return true;
0647     default:
0648         return false;
0649     }
0650 }
0651 
0652 static const struct regmap_config stm32_h7_spdifrx_regmap_conf = {
0653     .reg_bits = 32,
0654     .reg_stride = 4,
0655     .val_bits = 32,
0656     .max_register = STM32_SPDIFRX_SIDR,
0657     .readable_reg = stm32_spdifrx_readable_reg,
0658     .volatile_reg = stm32_spdifrx_volatile_reg,
0659     .writeable_reg = stm32_spdifrx_writeable_reg,
0660     .num_reg_defaults_raw = STM32_SPDIFRX_SIDR / sizeof(u32) + 1,
0661     .fast_io = true,
0662     .cache_type = REGCACHE_FLAT,
0663 };
0664 
0665 static irqreturn_t stm32_spdifrx_isr(int irq, void *devid)
0666 {
0667     struct stm32_spdifrx_data *spdifrx = (struct stm32_spdifrx_data *)devid;
0668     struct platform_device *pdev = spdifrx->pdev;
0669     unsigned int cr, mask, sr, imr;
0670     unsigned int flags, sync_state;
0671     int err = 0, err_xrun = 0;
0672 
0673     regmap_read(spdifrx->regmap, STM32_SPDIFRX_SR, &sr);
0674     regmap_read(spdifrx->regmap, STM32_SPDIFRX_IMR, &imr);
0675 
0676     mask = imr & SPDIFRX_XIMR_MASK;
0677     /* SERR, TERR, FERR IRQs are generated if IFEIE is set */
0678     if (mask & SPDIFRX_IMR_IFEIE)
0679         mask |= (SPDIFRX_IMR_IFEIE << 1) | (SPDIFRX_IMR_IFEIE << 2);
0680 
0681     flags = sr & mask;
0682     if (!flags) {
0683         dev_err(&pdev->dev, "Unexpected IRQ. rflags=%#x, imr=%#x\n",
0684             sr, imr);
0685         return IRQ_NONE;
0686     }
0687 
0688     /* Clear IRQs */
0689     regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IFCR,
0690                SPDIFRX_XIFCR_MASK, flags);
0691 
0692     if (flags & SPDIFRX_SR_PERR) {
0693         dev_dbg(&pdev->dev, "Parity error\n");
0694         err_xrun = 1;
0695     }
0696 
0697     if (flags & SPDIFRX_SR_OVR) {
0698         dev_dbg(&pdev->dev, "Overrun error\n");
0699         err_xrun = 1;
0700     }
0701 
0702     if (flags & SPDIFRX_SR_SBD)
0703         dev_dbg(&pdev->dev, "Synchronization block detected\n");
0704 
0705     if (flags & SPDIFRX_SR_SYNCD) {
0706         dev_dbg(&pdev->dev, "Synchronization done\n");
0707 
0708         /* Enable spdifrx */
0709         cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_ENABLE);
0710         regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
0711                    SPDIFRX_CR_SPDIFEN_MASK, cr);
0712     }
0713 
0714     if (flags & SPDIFRX_SR_FERR) {
0715         dev_dbg(&pdev->dev, "Frame error\n");
0716         err = 1;
0717     }
0718 
0719     if (flags & SPDIFRX_SR_SERR) {
0720         dev_dbg(&pdev->dev, "Synchronization error\n");
0721         err = 1;
0722     }
0723 
0724     if (flags & SPDIFRX_SR_TERR) {
0725         dev_dbg(&pdev->dev, "Timeout error\n");
0726         err = 1;
0727     }
0728 
0729     if (err) {
0730         regmap_read(spdifrx->regmap, STM32_SPDIFRX_CR, &cr);
0731         sync_state = FIELD_GET(SPDIFRX_CR_SPDIFEN_MASK, cr) &&
0732                  SPDIFRX_SPDIFEN_SYNC;
0733 
0734         /* SPDIFRX is in STATE_STOP. Disable SPDIFRX to clear errors */
0735         cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_DISABLE);
0736         regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
0737                    SPDIFRX_CR_SPDIFEN_MASK, cr);
0738 
0739         /* If SPDIFRX was in STATE_SYNC, retry synchro */
0740         if (sync_state) {
0741             cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_SYNC);
0742             regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
0743                        SPDIFRX_CR_SPDIFEN_MASK, cr);
0744             return IRQ_HANDLED;
0745         }
0746 
0747         spin_lock(&spdifrx->irq_lock);
0748         if (spdifrx->substream)
0749             snd_pcm_stop(spdifrx->substream,
0750                      SNDRV_PCM_STATE_DISCONNECTED);
0751         spin_unlock(&spdifrx->irq_lock);
0752 
0753         return IRQ_HANDLED;
0754     }
0755 
0756     spin_lock(&spdifrx->irq_lock);
0757     if (err_xrun && spdifrx->substream)
0758         snd_pcm_stop_xrun(spdifrx->substream);
0759     spin_unlock(&spdifrx->irq_lock);
0760 
0761     return IRQ_HANDLED;
0762 }
0763 
0764 static int stm32_spdifrx_startup(struct snd_pcm_substream *substream,
0765                  struct snd_soc_dai *cpu_dai)
0766 {
0767     struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
0768     unsigned long flags;
0769     int ret;
0770 
0771     spin_lock_irqsave(&spdifrx->irq_lock, flags);
0772     spdifrx->substream = substream;
0773     spin_unlock_irqrestore(&spdifrx->irq_lock, flags);
0774 
0775     ret = clk_prepare_enable(spdifrx->kclk);
0776     if (ret)
0777         dev_err(&spdifrx->pdev->dev, "Enable kclk failed: %d\n", ret);
0778 
0779     return ret;
0780 }
0781 
0782 static int stm32_spdifrx_hw_params(struct snd_pcm_substream *substream,
0783                    struct snd_pcm_hw_params *params,
0784                    struct snd_soc_dai *cpu_dai)
0785 {
0786     struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
0787     int data_size = params_width(params);
0788     int fmt;
0789 
0790     switch (data_size) {
0791     case 16:
0792         fmt = SPDIFRX_DRFMT_PACKED;
0793         break;
0794     case 32:
0795         fmt = SPDIFRX_DRFMT_LEFT;
0796         break;
0797     default:
0798         dev_err(&spdifrx->pdev->dev, "Unexpected data format\n");
0799         return -EINVAL;
0800     }
0801 
0802     /*
0803      * Set buswidth to 4 bytes for all data formats.
0804      * Packed format: transfer 2 x 2 bytes samples
0805      * Left format: transfer 1 x 3 bytes samples + 1 dummy byte
0806      */
0807     spdifrx->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
0808     snd_soc_dai_init_dma_data(cpu_dai, NULL, &spdifrx->dma_params);
0809 
0810     return regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
0811                   SPDIFRX_CR_DRFMT_MASK,
0812                   SPDIFRX_CR_DRFMTSET(fmt));
0813 }
0814 
0815 static int stm32_spdifrx_trigger(struct snd_pcm_substream *substream, int cmd,
0816                  struct snd_soc_dai *cpu_dai)
0817 {
0818     struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
0819     int ret = 0;
0820 
0821     switch (cmd) {
0822     case SNDRV_PCM_TRIGGER_START:
0823     case SNDRV_PCM_TRIGGER_RESUME:
0824     case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
0825         regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR,
0826                    SPDIFRX_IMR_OVRIE, SPDIFRX_IMR_OVRIE);
0827 
0828         regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
0829                    SPDIFRX_CR_RXDMAEN, SPDIFRX_CR_RXDMAEN);
0830 
0831         ret = stm32_spdifrx_start_sync(spdifrx);
0832         break;
0833     case SNDRV_PCM_TRIGGER_SUSPEND:
0834     case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
0835     case SNDRV_PCM_TRIGGER_STOP:
0836         stm32_spdifrx_stop(spdifrx);
0837         break;
0838     default:
0839         return -EINVAL;
0840     }
0841 
0842     return ret;
0843 }
0844 
0845 static void stm32_spdifrx_shutdown(struct snd_pcm_substream *substream,
0846                    struct snd_soc_dai *cpu_dai)
0847 {
0848     struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
0849     unsigned long flags;
0850 
0851     spin_lock_irqsave(&spdifrx->irq_lock, flags);
0852     spdifrx->substream = NULL;
0853     spin_unlock_irqrestore(&spdifrx->irq_lock, flags);
0854 
0855     clk_disable_unprepare(spdifrx->kclk);
0856 }
0857 
0858 static const struct snd_soc_dai_ops stm32_spdifrx_pcm_dai_ops = {
0859     .startup    = stm32_spdifrx_startup,
0860     .hw_params  = stm32_spdifrx_hw_params,
0861     .trigger    = stm32_spdifrx_trigger,
0862     .shutdown   = stm32_spdifrx_shutdown,
0863 };
0864 
0865 static struct snd_soc_dai_driver stm32_spdifrx_dai[] = {
0866     {
0867         .probe = stm32_spdifrx_dai_probe,
0868         .capture = {
0869             .stream_name = "CPU-Capture",
0870             .channels_min = 1,
0871             .channels_max = 2,
0872             .rates = SNDRV_PCM_RATE_8000_192000,
0873             .formats = SNDRV_PCM_FMTBIT_S32_LE |
0874                    SNDRV_PCM_FMTBIT_S16_LE,
0875         },
0876         .ops = &stm32_spdifrx_pcm_dai_ops,
0877     }
0878 };
0879 
0880 static const struct snd_pcm_hardware stm32_spdifrx_pcm_hw = {
0881     .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP,
0882     .buffer_bytes_max = 8 * PAGE_SIZE,
0883     .period_bytes_min = 1024,
0884     .period_bytes_max = 4 * PAGE_SIZE,
0885     .periods_min = 2,
0886     .periods_max = 8,
0887 };
0888 
0889 static const struct snd_soc_component_driver stm32_spdifrx_component = {
0890     .name = "stm32-spdifrx",
0891     .legacy_dai_naming = 1,
0892 };
0893 
0894 static const struct snd_dmaengine_pcm_config stm32_spdifrx_pcm_config = {
0895     .pcm_hardware = &stm32_spdifrx_pcm_hw,
0896     .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
0897 };
0898 
0899 static const struct of_device_id stm32_spdifrx_ids[] = {
0900     {
0901         .compatible = "st,stm32h7-spdifrx",
0902         .data = &stm32_h7_spdifrx_regmap_conf
0903     },
0904     {}
0905 };
0906 
0907 static int stm32_spdifrx_parse_of(struct platform_device *pdev,
0908                   struct stm32_spdifrx_data *spdifrx)
0909 {
0910     struct device_node *np = pdev->dev.of_node;
0911     const struct of_device_id *of_id;
0912     struct resource *res;
0913 
0914     if (!np)
0915         return -ENODEV;
0916 
0917     of_id = of_match_device(stm32_spdifrx_ids, &pdev->dev);
0918     if (of_id)
0919         spdifrx->regmap_conf =
0920             (const struct regmap_config *)of_id->data;
0921     else
0922         return -EINVAL;
0923 
0924     spdifrx->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
0925     if (IS_ERR(spdifrx->base))
0926         return PTR_ERR(spdifrx->base);
0927 
0928     spdifrx->phys_addr = res->start;
0929 
0930     spdifrx->kclk = devm_clk_get(&pdev->dev, "kclk");
0931     if (IS_ERR(spdifrx->kclk))
0932         return dev_err_probe(&pdev->dev, PTR_ERR(spdifrx->kclk),
0933                      "Could not get kclk\n");
0934 
0935     spdifrx->irq = platform_get_irq(pdev, 0);
0936     if (spdifrx->irq < 0)
0937         return spdifrx->irq;
0938 
0939     return 0;
0940 }
0941 
0942 static int stm32_spdifrx_remove(struct platform_device *pdev)
0943 {
0944     struct stm32_spdifrx_data *spdifrx = platform_get_drvdata(pdev);
0945 
0946     if (spdifrx->ctrl_chan)
0947         dma_release_channel(spdifrx->ctrl_chan);
0948 
0949     if (spdifrx->dmab)
0950         snd_dma_free_pages(spdifrx->dmab);
0951 
0952     snd_dmaengine_pcm_unregister(&pdev->dev);
0953     snd_soc_unregister_component(&pdev->dev);
0954     pm_runtime_disable(&pdev->dev);
0955 
0956     return 0;
0957 }
0958 
0959 static int stm32_spdifrx_probe(struct platform_device *pdev)
0960 {
0961     struct stm32_spdifrx_data *spdifrx;
0962     struct reset_control *rst;
0963     const struct snd_dmaengine_pcm_config *pcm_config = NULL;
0964     u32 ver, idr;
0965     int ret;
0966 
0967     spdifrx = devm_kzalloc(&pdev->dev, sizeof(*spdifrx), GFP_KERNEL);
0968     if (!spdifrx)
0969         return -ENOMEM;
0970 
0971     spdifrx->pdev = pdev;
0972     init_completion(&spdifrx->cs_completion);
0973     spin_lock_init(&spdifrx->lock);
0974     spin_lock_init(&spdifrx->irq_lock);
0975 
0976     platform_set_drvdata(pdev, spdifrx);
0977 
0978     ret = stm32_spdifrx_parse_of(pdev, spdifrx);
0979     if (ret)
0980         return ret;
0981 
0982     spdifrx->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "kclk",
0983                             spdifrx->base,
0984                             spdifrx->regmap_conf);
0985     if (IS_ERR(spdifrx->regmap))
0986         return dev_err_probe(&pdev->dev, PTR_ERR(spdifrx->regmap),
0987                      "Regmap init error\n");
0988 
0989     ret = devm_request_irq(&pdev->dev, spdifrx->irq, stm32_spdifrx_isr, 0,
0990                    dev_name(&pdev->dev), spdifrx);
0991     if (ret) {
0992         dev_err(&pdev->dev, "IRQ request returned %d\n", ret);
0993         return ret;
0994     }
0995 
0996     rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
0997     if (IS_ERR(rst))
0998         return dev_err_probe(&pdev->dev, PTR_ERR(rst),
0999                      "Reset controller error\n");
1000 
1001     reset_control_assert(rst);
1002     udelay(2);
1003     reset_control_deassert(rst);
1004 
1005     pm_runtime_enable(&pdev->dev);
1006 
1007     pcm_config = &stm32_spdifrx_pcm_config;
1008     ret = snd_dmaengine_pcm_register(&pdev->dev, pcm_config, 0);
1009     if (ret)
1010         return dev_err_probe(&pdev->dev, ret, "PCM DMA register error\n");
1011 
1012     ret = snd_soc_register_component(&pdev->dev,
1013                      &stm32_spdifrx_component,
1014                      stm32_spdifrx_dai,
1015                      ARRAY_SIZE(stm32_spdifrx_dai));
1016     if (ret) {
1017         snd_dmaengine_pcm_unregister(&pdev->dev);
1018         return ret;
1019     }
1020 
1021     ret = stm32_spdifrx_dma_ctrl_register(&pdev->dev, spdifrx);
1022     if (ret)
1023         goto error;
1024 
1025     ret = regmap_read(spdifrx->regmap, STM32_SPDIFRX_IDR, &idr);
1026     if (ret)
1027         goto error;
1028 
1029     if (idr == SPDIFRX_IPIDR_NUMBER) {
1030         ret = regmap_read(spdifrx->regmap, STM32_SPDIFRX_VERR, &ver);
1031         if (ret)
1032             goto error;
1033 
1034         dev_dbg(&pdev->dev, "SPDIFRX version: %lu.%lu registered\n",
1035             FIELD_GET(SPDIFRX_VERR_MAJ_MASK, ver),
1036             FIELD_GET(SPDIFRX_VERR_MIN_MASK, ver));
1037     }
1038 
1039     return ret;
1040 
1041 error:
1042     stm32_spdifrx_remove(pdev);
1043 
1044     return ret;
1045 }
1046 
1047 MODULE_DEVICE_TABLE(of, stm32_spdifrx_ids);
1048 
1049 #ifdef CONFIG_PM_SLEEP
1050 static int stm32_spdifrx_suspend(struct device *dev)
1051 {
1052     struct stm32_spdifrx_data *spdifrx = dev_get_drvdata(dev);
1053 
1054     regcache_cache_only(spdifrx->regmap, true);
1055     regcache_mark_dirty(spdifrx->regmap);
1056 
1057     return 0;
1058 }
1059 
1060 static int stm32_spdifrx_resume(struct device *dev)
1061 {
1062     struct stm32_spdifrx_data *spdifrx = dev_get_drvdata(dev);
1063 
1064     regcache_cache_only(spdifrx->regmap, false);
1065 
1066     return regcache_sync(spdifrx->regmap);
1067 }
1068 #endif /* CONFIG_PM_SLEEP */
1069 
1070 static const struct dev_pm_ops stm32_spdifrx_pm_ops = {
1071     SET_SYSTEM_SLEEP_PM_OPS(stm32_spdifrx_suspend, stm32_spdifrx_resume)
1072 };
1073 
1074 static struct platform_driver stm32_spdifrx_driver = {
1075     .driver = {
1076         .name = "st,stm32-spdifrx",
1077         .of_match_table = stm32_spdifrx_ids,
1078         .pm = &stm32_spdifrx_pm_ops,
1079     },
1080     .probe = stm32_spdifrx_probe,
1081     .remove = stm32_spdifrx_remove,
1082 };
1083 
1084 module_platform_driver(stm32_spdifrx_driver);
1085 
1086 MODULE_DESCRIPTION("STM32 Soc spdifrx Interface");
1087 MODULE_AUTHOR("Olivier Moysan, <olivier.moysan@st.com>");
1088 MODULE_ALIAS("platform:stm32-spdifrx");
1089 MODULE_LICENSE("GPL v2");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!