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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * STM32 ALSA SoC Digital Audio Interface (SAI) driver.
0004  *
0005  * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
0006  * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics.
0007  */
0008 
0009 #include <linux/clk.h>
0010 #include <linux/clk-provider.h>
0011 #include <linux/kernel.h>
0012 #include <linux/module.h>
0013 #include <linux/of_irq.h>
0014 #include <linux/of_platform.h>
0015 #include <linux/pm_runtime.h>
0016 #include <linux/regmap.h>
0017 
0018 #include <sound/asoundef.h>
0019 #include <sound/core.h>
0020 #include <sound/dmaengine_pcm.h>
0021 #include <sound/pcm_params.h>
0022 
0023 #include "stm32_sai.h"
0024 
0025 #define SAI_FREE_PROTOCOL   0x0
0026 #define SAI_SPDIF_PROTOCOL  0x1
0027 
0028 #define SAI_SLOT_SIZE_AUTO  0x0
0029 #define SAI_SLOT_SIZE_16    0x1
0030 #define SAI_SLOT_SIZE_32    0x2
0031 
0032 #define SAI_DATASIZE_8      0x2
0033 #define SAI_DATASIZE_10     0x3
0034 #define SAI_DATASIZE_16     0x4
0035 #define SAI_DATASIZE_20     0x5
0036 #define SAI_DATASIZE_24     0x6
0037 #define SAI_DATASIZE_32     0x7
0038 
0039 #define STM_SAI_DAI_NAME_SIZE   15
0040 
0041 #define STM_SAI_IS_PLAYBACK(ip) ((ip)->dir == SNDRV_PCM_STREAM_PLAYBACK)
0042 #define STM_SAI_IS_CAPTURE(ip)  ((ip)->dir == SNDRV_PCM_STREAM_CAPTURE)
0043 
0044 #define STM_SAI_A_ID        0x0
0045 #define STM_SAI_B_ID        0x1
0046 
0047 #define STM_SAI_IS_SUB_A(x) ((x)->id == STM_SAI_A_ID)
0048 
0049 #define SAI_SYNC_NONE       0x0
0050 #define SAI_SYNC_INTERNAL   0x1
0051 #define SAI_SYNC_EXTERNAL   0x2
0052 
0053 #define STM_SAI_PROTOCOL_IS_SPDIF(ip)   ((ip)->spdif)
0054 #define STM_SAI_HAS_SPDIF(x)    ((x)->pdata->conf.has_spdif_pdm)
0055 #define STM_SAI_HAS_PDM(x)  ((x)->pdata->conf.has_spdif_pdm)
0056 #define STM_SAI_HAS_EXT_SYNC(x) (!STM_SAI_IS_F4(sai->pdata))
0057 
0058 #define SAI_IEC60958_BLOCK_FRAMES   192
0059 #define SAI_IEC60958_STATUS_BYTES   24
0060 
0061 #define SAI_MCLK_NAME_LEN       32
0062 #define SAI_RATE_11K            11025
0063 
0064 /**
0065  * struct stm32_sai_sub_data - private data of SAI sub block (block A or B)
0066  * @pdev: device data pointer
0067  * @regmap: SAI register map pointer
0068  * @regmap_config: SAI sub block register map configuration pointer
0069  * @dma_params: dma configuration data for rx or tx channel
0070  * @cpu_dai_drv: DAI driver data pointer
0071  * @cpu_dai: DAI runtime data pointer
0072  * @substream: PCM substream data pointer
0073  * @pdata: SAI block parent data pointer
0074  * @np_sync_provider: synchronization provider node
0075  * @sai_ck: kernel clock feeding the SAI clock generator
0076  * @sai_mclk: master clock from SAI mclk provider
0077  * @phys_addr: SAI registers physical base address
0078  * @mclk_rate: SAI block master clock frequency (Hz). set at init
0079  * @id: SAI sub block id corresponding to sub-block A or B
0080  * @dir: SAI block direction (playback or capture). set at init
0081  * @master: SAI block mode flag. (true=master, false=slave) set at init
0082  * @spdif: SAI S/PDIF iec60958 mode flag. set at init
0083  * @fmt: SAI block format. relevant only for custom protocols. set at init
0084  * @sync: SAI block synchronization mode. (none, internal or external)
0085  * @synco: SAI block ext sync source (provider setting). (none, sub-block A/B)
0086  * @synci: SAI block ext sync source (client setting). (SAI sync provider index)
0087  * @fs_length: frame synchronization length. depends on protocol settings
0088  * @slots: rx or tx slot number
0089  * @slot_width: rx or tx slot width in bits
0090  * @slot_mask: rx or tx active slots mask. set at init or at runtime
0091  * @data_size: PCM data width. corresponds to PCM substream width.
0092  * @spdif_frm_cnt: S/PDIF playback frame counter
0093  * @iec958: iec958 data
0094  * @ctrl_lock: control lock
0095  * @irq_lock: prevent race condition with IRQ
0096  */
0097 struct stm32_sai_sub_data {
0098     struct platform_device *pdev;
0099     struct regmap *regmap;
0100     const struct regmap_config *regmap_config;
0101     struct snd_dmaengine_dai_dma_data dma_params;
0102     struct snd_soc_dai_driver cpu_dai_drv;
0103     struct snd_soc_dai *cpu_dai;
0104     struct snd_pcm_substream *substream;
0105     struct stm32_sai_data *pdata;
0106     struct device_node *np_sync_provider;
0107     struct clk *sai_ck;
0108     struct clk *sai_mclk;
0109     dma_addr_t phys_addr;
0110     unsigned int mclk_rate;
0111     unsigned int id;
0112     int dir;
0113     bool master;
0114     bool spdif;
0115     int fmt;
0116     int sync;
0117     int synco;
0118     int synci;
0119     int fs_length;
0120     int slots;
0121     int slot_width;
0122     int slot_mask;
0123     int data_size;
0124     unsigned int spdif_frm_cnt;
0125     struct snd_aes_iec958 iec958;
0126     struct mutex ctrl_lock; /* protect resources accessed by controls */
0127     spinlock_t irq_lock; /* used to prevent race condition with IRQ */
0128 };
0129 
0130 enum stm32_sai_fifo_th {
0131     STM_SAI_FIFO_TH_EMPTY,
0132     STM_SAI_FIFO_TH_QUARTER,
0133     STM_SAI_FIFO_TH_HALF,
0134     STM_SAI_FIFO_TH_3_QUARTER,
0135     STM_SAI_FIFO_TH_FULL,
0136 };
0137 
0138 static bool stm32_sai_sub_readable_reg(struct device *dev, unsigned int reg)
0139 {
0140     switch (reg) {
0141     case STM_SAI_CR1_REGX:
0142     case STM_SAI_CR2_REGX:
0143     case STM_SAI_FRCR_REGX:
0144     case STM_SAI_SLOTR_REGX:
0145     case STM_SAI_IMR_REGX:
0146     case STM_SAI_SR_REGX:
0147     case STM_SAI_CLRFR_REGX:
0148     case STM_SAI_DR_REGX:
0149     case STM_SAI_PDMCR_REGX:
0150     case STM_SAI_PDMLY_REGX:
0151         return true;
0152     default:
0153         return false;
0154     }
0155 }
0156 
0157 static bool stm32_sai_sub_volatile_reg(struct device *dev, unsigned int reg)
0158 {
0159     switch (reg) {
0160     case STM_SAI_DR_REGX:
0161     case STM_SAI_SR_REGX:
0162         return true;
0163     default:
0164         return false;
0165     }
0166 }
0167 
0168 static bool stm32_sai_sub_writeable_reg(struct device *dev, unsigned int reg)
0169 {
0170     switch (reg) {
0171     case STM_SAI_CR1_REGX:
0172     case STM_SAI_CR2_REGX:
0173     case STM_SAI_FRCR_REGX:
0174     case STM_SAI_SLOTR_REGX:
0175     case STM_SAI_IMR_REGX:
0176     case STM_SAI_CLRFR_REGX:
0177     case STM_SAI_DR_REGX:
0178     case STM_SAI_PDMCR_REGX:
0179     case STM_SAI_PDMLY_REGX:
0180         return true;
0181     default:
0182         return false;
0183     }
0184 }
0185 
0186 static int stm32_sai_sub_reg_up(struct stm32_sai_sub_data *sai,
0187                 unsigned int reg, unsigned int mask,
0188                 unsigned int val)
0189 {
0190     int ret;
0191 
0192     ret = clk_enable(sai->pdata->pclk);
0193     if (ret < 0)
0194         return ret;
0195 
0196     ret = regmap_update_bits(sai->regmap, reg, mask, val);
0197 
0198     clk_disable(sai->pdata->pclk);
0199 
0200     return ret;
0201 }
0202 
0203 static int stm32_sai_sub_reg_wr(struct stm32_sai_sub_data *sai,
0204                 unsigned int reg, unsigned int mask,
0205                 unsigned int val)
0206 {
0207     int ret;
0208 
0209     ret = clk_enable(sai->pdata->pclk);
0210     if (ret < 0)
0211         return ret;
0212 
0213     ret = regmap_write_bits(sai->regmap, reg, mask, val);
0214 
0215     clk_disable(sai->pdata->pclk);
0216 
0217     return ret;
0218 }
0219 
0220 static int stm32_sai_sub_reg_rd(struct stm32_sai_sub_data *sai,
0221                 unsigned int reg, unsigned int *val)
0222 {
0223     int ret;
0224 
0225     ret = clk_enable(sai->pdata->pclk);
0226     if (ret < 0)
0227         return ret;
0228 
0229     ret = regmap_read(sai->regmap, reg, val);
0230 
0231     clk_disable(sai->pdata->pclk);
0232 
0233     return ret;
0234 }
0235 
0236 static const struct regmap_config stm32_sai_sub_regmap_config_f4 = {
0237     .reg_bits = 32,
0238     .reg_stride = 4,
0239     .val_bits = 32,
0240     .max_register = STM_SAI_DR_REGX,
0241     .readable_reg = stm32_sai_sub_readable_reg,
0242     .volatile_reg = stm32_sai_sub_volatile_reg,
0243     .writeable_reg = stm32_sai_sub_writeable_reg,
0244     .fast_io = true,
0245     .cache_type = REGCACHE_FLAT,
0246 };
0247 
0248 static const struct regmap_config stm32_sai_sub_regmap_config_h7 = {
0249     .reg_bits = 32,
0250     .reg_stride = 4,
0251     .val_bits = 32,
0252     .max_register = STM_SAI_PDMLY_REGX,
0253     .readable_reg = stm32_sai_sub_readable_reg,
0254     .volatile_reg = stm32_sai_sub_volatile_reg,
0255     .writeable_reg = stm32_sai_sub_writeable_reg,
0256     .fast_io = true,
0257     .cache_type = REGCACHE_FLAT,
0258 };
0259 
0260 static int snd_pcm_iec958_info(struct snd_kcontrol *kcontrol,
0261                    struct snd_ctl_elem_info *uinfo)
0262 {
0263     uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
0264     uinfo->count = 1;
0265 
0266     return 0;
0267 }
0268 
0269 static int snd_pcm_iec958_get(struct snd_kcontrol *kcontrol,
0270                   struct snd_ctl_elem_value *uctl)
0271 {
0272     struct stm32_sai_sub_data *sai = snd_kcontrol_chip(kcontrol);
0273 
0274     mutex_lock(&sai->ctrl_lock);
0275     memcpy(uctl->value.iec958.status, sai->iec958.status, 4);
0276     mutex_unlock(&sai->ctrl_lock);
0277 
0278     return 0;
0279 }
0280 
0281 static int snd_pcm_iec958_put(struct snd_kcontrol *kcontrol,
0282                   struct snd_ctl_elem_value *uctl)
0283 {
0284     struct stm32_sai_sub_data *sai = snd_kcontrol_chip(kcontrol);
0285 
0286     mutex_lock(&sai->ctrl_lock);
0287     memcpy(sai->iec958.status, uctl->value.iec958.status, 4);
0288     mutex_unlock(&sai->ctrl_lock);
0289 
0290     return 0;
0291 }
0292 
0293 static const struct snd_kcontrol_new iec958_ctls = {
0294     .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
0295             SNDRV_CTL_ELEM_ACCESS_VOLATILE),
0296     .iface = SNDRV_CTL_ELEM_IFACE_PCM,
0297     .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
0298     .info = snd_pcm_iec958_info,
0299     .get = snd_pcm_iec958_get,
0300     .put = snd_pcm_iec958_put,
0301 };
0302 
0303 struct stm32_sai_mclk_data {
0304     struct clk_hw hw;
0305     unsigned long freq;
0306     struct stm32_sai_sub_data *sai_data;
0307 };
0308 
0309 #define to_mclk_data(_hw) container_of(_hw, struct stm32_sai_mclk_data, hw)
0310 #define STM32_SAI_MAX_CLKS 1
0311 
0312 static int stm32_sai_get_clk_div(struct stm32_sai_sub_data *sai,
0313                  unsigned long input_rate,
0314                  unsigned long output_rate)
0315 {
0316     int version = sai->pdata->conf.version;
0317     int div;
0318 
0319     div = DIV_ROUND_CLOSEST(input_rate, output_rate);
0320     if (div > SAI_XCR1_MCKDIV_MAX(version)) {
0321         dev_err(&sai->pdev->dev, "Divider %d out of range\n", div);
0322         return -EINVAL;
0323     }
0324     dev_dbg(&sai->pdev->dev, "SAI divider %d\n", div);
0325 
0326     if (input_rate % div)
0327         dev_dbg(&sai->pdev->dev,
0328             "Rate not accurate. requested (%ld), actual (%ld)\n",
0329             output_rate, input_rate / div);
0330 
0331     return div;
0332 }
0333 
0334 static int stm32_sai_set_clk_div(struct stm32_sai_sub_data *sai,
0335                  unsigned int div)
0336 {
0337     int version = sai->pdata->conf.version;
0338     int ret, cr1, mask;
0339 
0340     if (div > SAI_XCR1_MCKDIV_MAX(version)) {
0341         dev_err(&sai->pdev->dev, "Divider %d out of range\n", div);
0342         return -EINVAL;
0343     }
0344 
0345     mask = SAI_XCR1_MCKDIV_MASK(SAI_XCR1_MCKDIV_WIDTH(version));
0346     cr1 = SAI_XCR1_MCKDIV_SET(div);
0347     ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, mask, cr1);
0348     if (ret < 0)
0349         dev_err(&sai->pdev->dev, "Failed to update CR1 register\n");
0350 
0351     return ret;
0352 }
0353 
0354 static int stm32_sai_set_parent_clock(struct stm32_sai_sub_data *sai,
0355                       unsigned int rate)
0356 {
0357     struct platform_device *pdev = sai->pdev;
0358     struct clk *parent_clk = sai->pdata->clk_x8k;
0359     int ret;
0360 
0361     if (!(rate % SAI_RATE_11K))
0362         parent_clk = sai->pdata->clk_x11k;
0363 
0364     ret = clk_set_parent(sai->sai_ck, parent_clk);
0365     if (ret)
0366         dev_err(&pdev->dev, " Error %d setting sai_ck parent clock. %s",
0367             ret, ret == -EBUSY ?
0368             "Active stream rates conflict\n" : "\n");
0369 
0370     return ret;
0371 }
0372 
0373 static long stm32_sai_mclk_round_rate(struct clk_hw *hw, unsigned long rate,
0374                       unsigned long *prate)
0375 {
0376     struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
0377     struct stm32_sai_sub_data *sai = mclk->sai_data;
0378     int div;
0379 
0380     div = stm32_sai_get_clk_div(sai, *prate, rate);
0381     if (div < 0)
0382         return div;
0383 
0384     mclk->freq = *prate / div;
0385 
0386     return mclk->freq;
0387 }
0388 
0389 static unsigned long stm32_sai_mclk_recalc_rate(struct clk_hw *hw,
0390                         unsigned long parent_rate)
0391 {
0392     struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
0393 
0394     return mclk->freq;
0395 }
0396 
0397 static int stm32_sai_mclk_set_rate(struct clk_hw *hw, unsigned long rate,
0398                    unsigned long parent_rate)
0399 {
0400     struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
0401     struct stm32_sai_sub_data *sai = mclk->sai_data;
0402     int div, ret;
0403 
0404     div = stm32_sai_get_clk_div(sai, parent_rate, rate);
0405     if (div < 0)
0406         return div;
0407 
0408     ret = stm32_sai_set_clk_div(sai, div);
0409     if (ret)
0410         return ret;
0411 
0412     mclk->freq = rate;
0413 
0414     return 0;
0415 }
0416 
0417 static int stm32_sai_mclk_enable(struct clk_hw *hw)
0418 {
0419     struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
0420     struct stm32_sai_sub_data *sai = mclk->sai_data;
0421 
0422     dev_dbg(&sai->pdev->dev, "Enable master clock\n");
0423 
0424     return stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX,
0425                     SAI_XCR1_MCKEN, SAI_XCR1_MCKEN);
0426 }
0427 
0428 static void stm32_sai_mclk_disable(struct clk_hw *hw)
0429 {
0430     struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
0431     struct stm32_sai_sub_data *sai = mclk->sai_data;
0432 
0433     dev_dbg(&sai->pdev->dev, "Disable master clock\n");
0434 
0435     stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, SAI_XCR1_MCKEN, 0);
0436 }
0437 
0438 static const struct clk_ops mclk_ops = {
0439     .enable = stm32_sai_mclk_enable,
0440     .disable = stm32_sai_mclk_disable,
0441     .recalc_rate = stm32_sai_mclk_recalc_rate,
0442     .round_rate = stm32_sai_mclk_round_rate,
0443     .set_rate = stm32_sai_mclk_set_rate,
0444 };
0445 
0446 static int stm32_sai_add_mclk_provider(struct stm32_sai_sub_data *sai)
0447 {
0448     struct clk_hw *hw;
0449     struct stm32_sai_mclk_data *mclk;
0450     struct device *dev = &sai->pdev->dev;
0451     const char *pname = __clk_get_name(sai->sai_ck);
0452     char *mclk_name, *p, *s = (char *)pname;
0453     int ret, i = 0;
0454 
0455     mclk = devm_kzalloc(dev, sizeof(*mclk), GFP_KERNEL);
0456     if (!mclk)
0457         return -ENOMEM;
0458 
0459     mclk_name = devm_kcalloc(dev, sizeof(char),
0460                  SAI_MCLK_NAME_LEN, GFP_KERNEL);
0461     if (!mclk_name)
0462         return -ENOMEM;
0463 
0464     /*
0465      * Forge mclk clock name from parent clock name and suffix.
0466      * String after "_" char is stripped in parent name.
0467      */
0468     p = mclk_name;
0469     while (*s && *s != '_' && (i < (SAI_MCLK_NAME_LEN - 7))) {
0470         *p++ = *s++;
0471         i++;
0472     }
0473     STM_SAI_IS_SUB_A(sai) ? strcat(p, "a_mclk") : strcat(p, "b_mclk");
0474 
0475     mclk->hw.init = CLK_HW_INIT(mclk_name, pname, &mclk_ops, 0);
0476     mclk->sai_data = sai;
0477     hw = &mclk->hw;
0478 
0479     dev_dbg(dev, "Register master clock %s\n", mclk_name);
0480     ret = devm_clk_hw_register(&sai->pdev->dev, hw);
0481     if (ret) {
0482         dev_err(dev, "mclk register returned %d\n", ret);
0483         return ret;
0484     }
0485     sai->sai_mclk = hw->clk;
0486 
0487     /* register mclk provider */
0488     return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
0489 }
0490 
0491 static irqreturn_t stm32_sai_isr(int irq, void *devid)
0492 {
0493     struct stm32_sai_sub_data *sai = (struct stm32_sai_sub_data *)devid;
0494     struct platform_device *pdev = sai->pdev;
0495     unsigned int sr, imr, flags;
0496     snd_pcm_state_t status = SNDRV_PCM_STATE_RUNNING;
0497 
0498     stm32_sai_sub_reg_rd(sai, STM_SAI_IMR_REGX, &imr);
0499     stm32_sai_sub_reg_rd(sai, STM_SAI_SR_REGX, &sr);
0500 
0501     flags = sr & imr;
0502     if (!flags)
0503         return IRQ_NONE;
0504 
0505     stm32_sai_sub_reg_wr(sai, STM_SAI_CLRFR_REGX, SAI_XCLRFR_MASK,
0506                  SAI_XCLRFR_MASK);
0507 
0508     if (!sai->substream) {
0509         dev_err(&pdev->dev, "Device stopped. Spurious IRQ 0x%x\n", sr);
0510         return IRQ_NONE;
0511     }
0512 
0513     if (flags & SAI_XIMR_OVRUDRIE) {
0514         dev_err(&pdev->dev, "IRQ %s\n",
0515             STM_SAI_IS_PLAYBACK(sai) ? "underrun" : "overrun");
0516         status = SNDRV_PCM_STATE_XRUN;
0517     }
0518 
0519     if (flags & SAI_XIMR_MUTEDETIE)
0520         dev_dbg(&pdev->dev, "IRQ mute detected\n");
0521 
0522     if (flags & SAI_XIMR_WCKCFGIE) {
0523         dev_err(&pdev->dev, "IRQ wrong clock configuration\n");
0524         status = SNDRV_PCM_STATE_DISCONNECTED;
0525     }
0526 
0527     if (flags & SAI_XIMR_CNRDYIE)
0528         dev_err(&pdev->dev, "IRQ Codec not ready\n");
0529 
0530     if (flags & SAI_XIMR_AFSDETIE) {
0531         dev_err(&pdev->dev, "IRQ Anticipated frame synchro\n");
0532         status = SNDRV_PCM_STATE_XRUN;
0533     }
0534 
0535     if (flags & SAI_XIMR_LFSDETIE) {
0536         dev_err(&pdev->dev, "IRQ Late frame synchro\n");
0537         status = SNDRV_PCM_STATE_XRUN;
0538     }
0539 
0540     spin_lock(&sai->irq_lock);
0541     if (status != SNDRV_PCM_STATE_RUNNING && sai->substream)
0542         snd_pcm_stop_xrun(sai->substream);
0543     spin_unlock(&sai->irq_lock);
0544 
0545     return IRQ_HANDLED;
0546 }
0547 
0548 static int stm32_sai_set_sysclk(struct snd_soc_dai *cpu_dai,
0549                 int clk_id, unsigned int freq, int dir)
0550 {
0551     struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
0552     int ret;
0553 
0554     if (dir == SND_SOC_CLOCK_OUT && sai->sai_mclk) {
0555         ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX,
0556                        SAI_XCR1_NODIV,
0557                      freq ? 0 : SAI_XCR1_NODIV);
0558         if (ret < 0)
0559             return ret;
0560 
0561         /* Assume shutdown if requested frequency is 0Hz */
0562         if (!freq) {
0563             /* Release mclk rate only if rate was actually set */
0564             if (sai->mclk_rate) {
0565                 clk_rate_exclusive_put(sai->sai_mclk);
0566                 sai->mclk_rate = 0;
0567             }
0568             return 0;
0569         }
0570 
0571         /* If master clock is used, set parent clock now */
0572         ret = stm32_sai_set_parent_clock(sai, freq);
0573         if (ret)
0574             return ret;
0575 
0576         ret = clk_set_rate_exclusive(sai->sai_mclk, freq);
0577         if (ret) {
0578             dev_err(cpu_dai->dev,
0579                 ret == -EBUSY ?
0580                 "Active streams have incompatible rates" :
0581                 "Could not set mclk rate\n");
0582             return ret;
0583         }
0584 
0585         dev_dbg(cpu_dai->dev, "SAI MCLK frequency is %uHz\n", freq);
0586         sai->mclk_rate = freq;
0587     }
0588 
0589     return 0;
0590 }
0591 
0592 static int stm32_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
0593                       u32 rx_mask, int slots, int slot_width)
0594 {
0595     struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
0596     int slotr, slotr_mask, slot_size;
0597 
0598     if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
0599         dev_warn(cpu_dai->dev, "Slot setting relevant only for TDM\n");
0600         return 0;
0601     }
0602 
0603     dev_dbg(cpu_dai->dev, "Masks tx/rx:%#x/%#x, slots:%d, width:%d\n",
0604         tx_mask, rx_mask, slots, slot_width);
0605 
0606     switch (slot_width) {
0607     case 16:
0608         slot_size = SAI_SLOT_SIZE_16;
0609         break;
0610     case 32:
0611         slot_size = SAI_SLOT_SIZE_32;
0612         break;
0613     default:
0614         slot_size = SAI_SLOT_SIZE_AUTO;
0615         break;
0616     }
0617 
0618     slotr = SAI_XSLOTR_SLOTSZ_SET(slot_size) |
0619         SAI_XSLOTR_NBSLOT_SET(slots - 1);
0620     slotr_mask = SAI_XSLOTR_SLOTSZ_MASK | SAI_XSLOTR_NBSLOT_MASK;
0621 
0622     /* tx/rx mask set in machine init, if slot number defined in DT */
0623     if (STM_SAI_IS_PLAYBACK(sai)) {
0624         sai->slot_mask = tx_mask;
0625         slotr |= SAI_XSLOTR_SLOTEN_SET(tx_mask);
0626     }
0627 
0628     if (STM_SAI_IS_CAPTURE(sai)) {
0629         sai->slot_mask = rx_mask;
0630         slotr |= SAI_XSLOTR_SLOTEN_SET(rx_mask);
0631     }
0632 
0633     slotr_mask |= SAI_XSLOTR_SLOTEN_MASK;
0634 
0635     stm32_sai_sub_reg_up(sai, STM_SAI_SLOTR_REGX, slotr_mask, slotr);
0636 
0637     sai->slot_width = slot_width;
0638     sai->slots = slots;
0639 
0640     return 0;
0641 }
0642 
0643 static int stm32_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
0644 {
0645     struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
0646     int cr1, frcr = 0;
0647     int cr1_mask, frcr_mask = 0;
0648     int ret;
0649 
0650     dev_dbg(cpu_dai->dev, "fmt %x\n", fmt);
0651 
0652     /* Do not generate master by default */
0653     cr1 = SAI_XCR1_NODIV;
0654     cr1_mask = SAI_XCR1_NODIV;
0655 
0656     cr1_mask |= SAI_XCR1_PRTCFG_MASK;
0657     if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
0658         cr1 |= SAI_XCR1_PRTCFG_SET(SAI_SPDIF_PROTOCOL);
0659         goto conf_update;
0660     }
0661 
0662     cr1 |= SAI_XCR1_PRTCFG_SET(SAI_FREE_PROTOCOL);
0663 
0664     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0665     /* SCK active high for all protocols */
0666     case SND_SOC_DAIFMT_I2S:
0667         cr1 |= SAI_XCR1_CKSTR;
0668         frcr |= SAI_XFRCR_FSOFF | SAI_XFRCR_FSDEF;
0669         break;
0670     /* Left justified */
0671     case SND_SOC_DAIFMT_MSB:
0672         frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF;
0673         break;
0674     /* Right justified */
0675     case SND_SOC_DAIFMT_LSB:
0676         frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF;
0677         break;
0678     case SND_SOC_DAIFMT_DSP_A:
0679         frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF;
0680         break;
0681     case SND_SOC_DAIFMT_DSP_B:
0682         frcr |= SAI_XFRCR_FSPOL;
0683         break;
0684     default:
0685         dev_err(cpu_dai->dev, "Unsupported protocol %#x\n",
0686             fmt & SND_SOC_DAIFMT_FORMAT_MASK);
0687         return -EINVAL;
0688     }
0689 
0690     cr1_mask |= SAI_XCR1_CKSTR;
0691     frcr_mask |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF |
0692              SAI_XFRCR_FSDEF;
0693 
0694     /* DAI clock strobing. Invert setting previously set */
0695     switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
0696     case SND_SOC_DAIFMT_NB_NF:
0697         break;
0698     case SND_SOC_DAIFMT_IB_NF:
0699         cr1 ^= SAI_XCR1_CKSTR;
0700         break;
0701     case SND_SOC_DAIFMT_NB_IF:
0702         frcr ^= SAI_XFRCR_FSPOL;
0703         break;
0704     case SND_SOC_DAIFMT_IB_IF:
0705         /* Invert fs & sck */
0706         cr1 ^= SAI_XCR1_CKSTR;
0707         frcr ^= SAI_XFRCR_FSPOL;
0708         break;
0709     default:
0710         dev_err(cpu_dai->dev, "Unsupported strobing %#x\n",
0711             fmt & SND_SOC_DAIFMT_INV_MASK);
0712         return -EINVAL;
0713     }
0714     cr1_mask |= SAI_XCR1_CKSTR;
0715     frcr_mask |= SAI_XFRCR_FSPOL;
0716 
0717     stm32_sai_sub_reg_up(sai, STM_SAI_FRCR_REGX, frcr_mask, frcr);
0718 
0719     /* DAI clock master masks */
0720     switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
0721     case SND_SOC_DAIFMT_BC_FC:
0722         /* codec is master */
0723         cr1 |= SAI_XCR1_SLAVE;
0724         sai->master = false;
0725         break;
0726     case SND_SOC_DAIFMT_BP_FP:
0727         sai->master = true;
0728         break;
0729     default:
0730         dev_err(cpu_dai->dev, "Unsupported mode %#x\n",
0731             fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK);
0732         return -EINVAL;
0733     }
0734 
0735     /* Set slave mode if sub-block is synchronized with another SAI */
0736     if (sai->sync) {
0737         dev_dbg(cpu_dai->dev, "Synchronized SAI configured as slave\n");
0738         cr1 |= SAI_XCR1_SLAVE;
0739         sai->master = false;
0740     }
0741 
0742     cr1_mask |= SAI_XCR1_SLAVE;
0743 
0744 conf_update:
0745     ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, cr1_mask, cr1);
0746     if (ret < 0) {
0747         dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
0748         return ret;
0749     }
0750 
0751     sai->fmt = fmt;
0752 
0753     return 0;
0754 }
0755 
0756 static int stm32_sai_startup(struct snd_pcm_substream *substream,
0757                  struct snd_soc_dai *cpu_dai)
0758 {
0759     struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
0760     int imr, cr2, ret;
0761     unsigned long flags;
0762 
0763     spin_lock_irqsave(&sai->irq_lock, flags);
0764     sai->substream = substream;
0765     spin_unlock_irqrestore(&sai->irq_lock, flags);
0766 
0767     if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
0768         snd_pcm_hw_constraint_mask64(substream->runtime,
0769                          SNDRV_PCM_HW_PARAM_FORMAT,
0770                          SNDRV_PCM_FMTBIT_S32_LE);
0771         snd_pcm_hw_constraint_single(substream->runtime,
0772                          SNDRV_PCM_HW_PARAM_CHANNELS, 2);
0773     }
0774 
0775     ret = clk_prepare_enable(sai->sai_ck);
0776     if (ret < 0) {
0777         dev_err(cpu_dai->dev, "Failed to enable clock: %d\n", ret);
0778         return ret;
0779     }
0780 
0781     /* Enable ITs */
0782     stm32_sai_sub_reg_wr(sai, STM_SAI_CLRFR_REGX,
0783                  SAI_XCLRFR_MASK, SAI_XCLRFR_MASK);
0784 
0785     imr = SAI_XIMR_OVRUDRIE;
0786     if (STM_SAI_IS_CAPTURE(sai)) {
0787         stm32_sai_sub_reg_rd(sai, STM_SAI_CR2_REGX, &cr2);
0788         if (cr2 & SAI_XCR2_MUTECNT_MASK)
0789             imr |= SAI_XIMR_MUTEDETIE;
0790     }
0791 
0792     if (sai->master)
0793         imr |= SAI_XIMR_WCKCFGIE;
0794     else
0795         imr |= SAI_XIMR_AFSDETIE | SAI_XIMR_LFSDETIE;
0796 
0797     stm32_sai_sub_reg_up(sai, STM_SAI_IMR_REGX,
0798                  SAI_XIMR_MASK, imr);
0799 
0800     return 0;
0801 }
0802 
0803 static int stm32_sai_set_config(struct snd_soc_dai *cpu_dai,
0804                 struct snd_pcm_substream *substream,
0805                 struct snd_pcm_hw_params *params)
0806 {
0807     struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
0808     int cr1, cr1_mask, ret;
0809 
0810     /*
0811      * DMA bursts increment is set to 4 words.
0812      * SAI fifo threshold is set to half fifo, to keep enough space
0813      * for DMA incoming bursts.
0814      */
0815     stm32_sai_sub_reg_wr(sai, STM_SAI_CR2_REGX,
0816                  SAI_XCR2_FFLUSH | SAI_XCR2_FTH_MASK,
0817                  SAI_XCR2_FFLUSH |
0818                  SAI_XCR2_FTH_SET(STM_SAI_FIFO_TH_HALF));
0819 
0820     /* DS bits in CR1 not set for SPDIF (size forced to 24 bits).*/
0821     if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
0822         sai->spdif_frm_cnt = 0;
0823         return 0;
0824     }
0825 
0826     /* Mode, data format and channel config */
0827     cr1_mask = SAI_XCR1_DS_MASK;
0828     switch (params_format(params)) {
0829     case SNDRV_PCM_FORMAT_S8:
0830         cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_8);
0831         break;
0832     case SNDRV_PCM_FORMAT_S16_LE:
0833         cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_16);
0834         break;
0835     case SNDRV_PCM_FORMAT_S32_LE:
0836         cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_32);
0837         break;
0838     default:
0839         dev_err(cpu_dai->dev, "Data format not supported\n");
0840         return -EINVAL;
0841     }
0842 
0843     cr1_mask |= SAI_XCR1_MONO;
0844     if ((sai->slots == 2) && (params_channels(params) == 1))
0845         cr1 |= SAI_XCR1_MONO;
0846 
0847     ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, cr1_mask, cr1);
0848     if (ret < 0) {
0849         dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
0850         return ret;
0851     }
0852 
0853     return 0;
0854 }
0855 
0856 static int stm32_sai_set_slots(struct snd_soc_dai *cpu_dai)
0857 {
0858     struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
0859     int slotr, slot_sz;
0860 
0861     stm32_sai_sub_reg_rd(sai, STM_SAI_SLOTR_REGX, &slotr);
0862 
0863     /*
0864      * If SLOTSZ is set to auto in SLOTR, align slot width on data size
0865      * By default slot width = data size, if not forced from DT
0866      */
0867     slot_sz = slotr & SAI_XSLOTR_SLOTSZ_MASK;
0868     if (slot_sz == SAI_XSLOTR_SLOTSZ_SET(SAI_SLOT_SIZE_AUTO))
0869         sai->slot_width = sai->data_size;
0870 
0871     if (sai->slot_width < sai->data_size) {
0872         dev_err(cpu_dai->dev,
0873             "Data size %d larger than slot width\n",
0874             sai->data_size);
0875         return -EINVAL;
0876     }
0877 
0878     /* Slot number is set to 2, if not specified in DT */
0879     if (!sai->slots)
0880         sai->slots = 2;
0881 
0882     /* The number of slots in the audio frame is equal to NBSLOT[3:0] + 1*/
0883     stm32_sai_sub_reg_up(sai, STM_SAI_SLOTR_REGX,
0884                  SAI_XSLOTR_NBSLOT_MASK,
0885                  SAI_XSLOTR_NBSLOT_SET((sai->slots - 1)));
0886 
0887     /* Set default slots mask if not already set from DT */
0888     if (!(slotr & SAI_XSLOTR_SLOTEN_MASK)) {
0889         sai->slot_mask = (1 << sai->slots) - 1;
0890         stm32_sai_sub_reg_up(sai,
0891                      STM_SAI_SLOTR_REGX, SAI_XSLOTR_SLOTEN_MASK,
0892                      SAI_XSLOTR_SLOTEN_SET(sai->slot_mask));
0893     }
0894 
0895     dev_dbg(cpu_dai->dev, "Slots %d, slot width %d\n",
0896         sai->slots, sai->slot_width);
0897 
0898     return 0;
0899 }
0900 
0901 static void stm32_sai_set_frame(struct snd_soc_dai *cpu_dai)
0902 {
0903     struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
0904     int fs_active, offset, format;
0905     int frcr, frcr_mask;
0906 
0907     format = sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
0908     sai->fs_length = sai->slot_width * sai->slots;
0909 
0910     fs_active = sai->fs_length / 2;
0911     if ((format == SND_SOC_DAIFMT_DSP_A) ||
0912         (format == SND_SOC_DAIFMT_DSP_B))
0913         fs_active = 1;
0914 
0915     frcr = SAI_XFRCR_FRL_SET((sai->fs_length - 1));
0916     frcr |= SAI_XFRCR_FSALL_SET((fs_active - 1));
0917     frcr_mask = SAI_XFRCR_FRL_MASK | SAI_XFRCR_FSALL_MASK;
0918 
0919     dev_dbg(cpu_dai->dev, "Frame length %d, frame active %d\n",
0920         sai->fs_length, fs_active);
0921 
0922     stm32_sai_sub_reg_up(sai, STM_SAI_FRCR_REGX, frcr_mask, frcr);
0923 
0924     if ((sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_LSB) {
0925         offset = sai->slot_width - sai->data_size;
0926 
0927         stm32_sai_sub_reg_up(sai, STM_SAI_SLOTR_REGX,
0928                      SAI_XSLOTR_FBOFF_MASK,
0929                      SAI_XSLOTR_FBOFF_SET(offset));
0930     }
0931 }
0932 
0933 static void stm32_sai_init_iec958_status(struct stm32_sai_sub_data *sai)
0934 {
0935     unsigned char *cs = sai->iec958.status;
0936 
0937     cs[0] = IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_NONE;
0938     cs[1] = IEC958_AES1_CON_GENERAL;
0939     cs[2] = IEC958_AES2_CON_SOURCE_UNSPEC | IEC958_AES2_CON_CHANNEL_UNSPEC;
0940     cs[3] = IEC958_AES3_CON_CLOCK_1000PPM | IEC958_AES3_CON_FS_NOTID;
0941 }
0942 
0943 static void stm32_sai_set_iec958_status(struct stm32_sai_sub_data *sai,
0944                     struct snd_pcm_runtime *runtime)
0945 {
0946     if (!runtime)
0947         return;
0948 
0949     /* Force the sample rate according to runtime rate */
0950     mutex_lock(&sai->ctrl_lock);
0951     switch (runtime->rate) {
0952     case 22050:
0953         sai->iec958.status[3] = IEC958_AES3_CON_FS_22050;
0954         break;
0955     case 44100:
0956         sai->iec958.status[3] = IEC958_AES3_CON_FS_44100;
0957         break;
0958     case 88200:
0959         sai->iec958.status[3] = IEC958_AES3_CON_FS_88200;
0960         break;
0961     case 176400:
0962         sai->iec958.status[3] = IEC958_AES3_CON_FS_176400;
0963         break;
0964     case 24000:
0965         sai->iec958.status[3] = IEC958_AES3_CON_FS_24000;
0966         break;
0967     case 48000:
0968         sai->iec958.status[3] = IEC958_AES3_CON_FS_48000;
0969         break;
0970     case 96000:
0971         sai->iec958.status[3] = IEC958_AES3_CON_FS_96000;
0972         break;
0973     case 192000:
0974         sai->iec958.status[3] = IEC958_AES3_CON_FS_192000;
0975         break;
0976     case 32000:
0977         sai->iec958.status[3] = IEC958_AES3_CON_FS_32000;
0978         break;
0979     default:
0980         sai->iec958.status[3] = IEC958_AES3_CON_FS_NOTID;
0981         break;
0982     }
0983     mutex_unlock(&sai->ctrl_lock);
0984 }
0985 
0986 static int stm32_sai_configure_clock(struct snd_soc_dai *cpu_dai,
0987                      struct snd_pcm_hw_params *params)
0988 {
0989     struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
0990     int div = 0, cr1 = 0;
0991     int sai_clk_rate, mclk_ratio, den;
0992     unsigned int rate = params_rate(params);
0993     int ret;
0994 
0995     if (!sai->sai_mclk) {
0996         ret = stm32_sai_set_parent_clock(sai, rate);
0997         if (ret)
0998             return ret;
0999     }
1000     sai_clk_rate = clk_get_rate(sai->sai_ck);
1001 
1002     if (STM_SAI_IS_F4(sai->pdata)) {
1003         /* mclk on (NODIV=0)
1004          *   mclk_rate = 256 * fs
1005          *   MCKDIV = 0 if sai_ck < 3/2 * mclk_rate
1006          *   MCKDIV = sai_ck / (2 * mclk_rate) otherwise
1007          * mclk off (NODIV=1)
1008          *   MCKDIV ignored. sck = sai_ck
1009          */
1010         if (!sai->mclk_rate)
1011             return 0;
1012 
1013         if (2 * sai_clk_rate >= 3 * sai->mclk_rate) {
1014             div = stm32_sai_get_clk_div(sai, sai_clk_rate,
1015                             2 * sai->mclk_rate);
1016             if (div < 0)
1017                 return div;
1018         }
1019     } else {
1020         /*
1021          * TDM mode :
1022          *   mclk on
1023          *      MCKDIV = sai_ck / (ws x 256)    (NOMCK=0. OSR=0)
1024          *      MCKDIV = sai_ck / (ws x 512)    (NOMCK=0. OSR=1)
1025          *   mclk off
1026          *      MCKDIV = sai_ck / (frl x ws)    (NOMCK=1)
1027          * Note: NOMCK/NODIV correspond to same bit.
1028          */
1029         if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
1030             div = stm32_sai_get_clk_div(sai, sai_clk_rate,
1031                             rate * 128);
1032             if (div < 0)
1033                 return div;
1034         } else {
1035             if (sai->mclk_rate) {
1036                 mclk_ratio = sai->mclk_rate / rate;
1037                 if (mclk_ratio == 512) {
1038                     cr1 = SAI_XCR1_OSR;
1039                 } else if (mclk_ratio != 256) {
1040                     dev_err(cpu_dai->dev,
1041                         "Wrong mclk ratio %d\n",
1042                         mclk_ratio);
1043                     return -EINVAL;
1044                 }
1045 
1046                 stm32_sai_sub_reg_up(sai,
1047                              STM_SAI_CR1_REGX,
1048                              SAI_XCR1_OSR, cr1);
1049 
1050                 div = stm32_sai_get_clk_div(sai, sai_clk_rate,
1051                                 sai->mclk_rate);
1052                 if (div < 0)
1053                     return div;
1054             } else {
1055                 /* mclk-fs not set, master clock not active */
1056                 den = sai->fs_length * params_rate(params);
1057                 div = stm32_sai_get_clk_div(sai, sai_clk_rate,
1058                                 den);
1059                 if (div < 0)
1060                     return div;
1061             }
1062         }
1063     }
1064 
1065     return stm32_sai_set_clk_div(sai, div);
1066 }
1067 
1068 static int stm32_sai_hw_params(struct snd_pcm_substream *substream,
1069                    struct snd_pcm_hw_params *params,
1070                    struct snd_soc_dai *cpu_dai)
1071 {
1072     struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
1073     int ret;
1074 
1075     sai->data_size = params_width(params);
1076 
1077     if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
1078         /* Rate not already set in runtime structure */
1079         substream->runtime->rate = params_rate(params);
1080         stm32_sai_set_iec958_status(sai, substream->runtime);
1081     } else {
1082         ret = stm32_sai_set_slots(cpu_dai);
1083         if (ret < 0)
1084             return ret;
1085         stm32_sai_set_frame(cpu_dai);
1086     }
1087 
1088     ret = stm32_sai_set_config(cpu_dai, substream, params);
1089     if (ret)
1090         return ret;
1091 
1092     if (sai->master)
1093         ret = stm32_sai_configure_clock(cpu_dai, params);
1094 
1095     return ret;
1096 }
1097 
1098 static int stm32_sai_trigger(struct snd_pcm_substream *substream, int cmd,
1099                  struct snd_soc_dai *cpu_dai)
1100 {
1101     struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
1102     int ret;
1103 
1104     switch (cmd) {
1105     case SNDRV_PCM_TRIGGER_START:
1106     case SNDRV_PCM_TRIGGER_RESUME:
1107     case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1108         dev_dbg(cpu_dai->dev, "Enable DMA and SAI\n");
1109 
1110         stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX,
1111                      SAI_XCR1_DMAEN, SAI_XCR1_DMAEN);
1112 
1113         /* Enable SAI */
1114         ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX,
1115                        SAI_XCR1_SAIEN, SAI_XCR1_SAIEN);
1116         if (ret < 0)
1117             dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
1118         break;
1119     case SNDRV_PCM_TRIGGER_SUSPEND:
1120     case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1121     case SNDRV_PCM_TRIGGER_STOP:
1122         dev_dbg(cpu_dai->dev, "Disable DMA and SAI\n");
1123 
1124         stm32_sai_sub_reg_up(sai, STM_SAI_IMR_REGX,
1125                      SAI_XIMR_MASK, 0);
1126 
1127         stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX,
1128                      SAI_XCR1_SAIEN,
1129                      (unsigned int)~SAI_XCR1_SAIEN);
1130 
1131         ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX,
1132                        SAI_XCR1_DMAEN,
1133                        (unsigned int)~SAI_XCR1_DMAEN);
1134         if (ret < 0)
1135             dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
1136 
1137         if (STM_SAI_PROTOCOL_IS_SPDIF(sai))
1138             sai->spdif_frm_cnt = 0;
1139         break;
1140     default:
1141         return -EINVAL;
1142     }
1143 
1144     return ret;
1145 }
1146 
1147 static void stm32_sai_shutdown(struct snd_pcm_substream *substream,
1148                    struct snd_soc_dai *cpu_dai)
1149 {
1150     struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
1151     unsigned long flags;
1152 
1153     stm32_sai_sub_reg_up(sai, STM_SAI_IMR_REGX, SAI_XIMR_MASK, 0);
1154 
1155     clk_disable_unprepare(sai->sai_ck);
1156 
1157     spin_lock_irqsave(&sai->irq_lock, flags);
1158     sai->substream = NULL;
1159     spin_unlock_irqrestore(&sai->irq_lock, flags);
1160 }
1161 
1162 static int stm32_sai_pcm_new(struct snd_soc_pcm_runtime *rtd,
1163                  struct snd_soc_dai *cpu_dai)
1164 {
1165     struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev);
1166     struct snd_kcontrol_new knew = iec958_ctls;
1167 
1168     if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
1169         dev_dbg(&sai->pdev->dev, "%s: register iec controls", __func__);
1170         knew.device = rtd->pcm->device;
1171         return snd_ctl_add(rtd->pcm->card, snd_ctl_new1(&knew, sai));
1172     }
1173 
1174     return 0;
1175 }
1176 
1177 static int stm32_sai_dai_probe(struct snd_soc_dai *cpu_dai)
1178 {
1179     struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev);
1180     int cr1 = 0, cr1_mask, ret;
1181 
1182     sai->cpu_dai = cpu_dai;
1183 
1184     sai->dma_params.addr = (dma_addr_t)(sai->phys_addr + STM_SAI_DR_REGX);
1185     /*
1186      * DMA supports 4, 8 or 16 burst sizes. Burst size 4 is the best choice,
1187      * as it allows bytes, half-word and words transfers. (See DMA fifos
1188      * constraints).
1189      */
1190     sai->dma_params.maxburst = 4;
1191     if (sai->pdata->conf.fifo_size < 8)
1192         sai->dma_params.maxburst = 1;
1193     /* Buswidth will be set by framework at runtime */
1194     sai->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
1195 
1196     if (STM_SAI_IS_PLAYBACK(sai))
1197         snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params, NULL);
1198     else
1199         snd_soc_dai_init_dma_data(cpu_dai, NULL, &sai->dma_params);
1200 
1201     /* Next settings are not relevant for spdif mode */
1202     if (STM_SAI_PROTOCOL_IS_SPDIF(sai))
1203         return 0;
1204 
1205     cr1_mask = SAI_XCR1_RX_TX;
1206     if (STM_SAI_IS_CAPTURE(sai))
1207         cr1 |= SAI_XCR1_RX_TX;
1208 
1209     /* Configure synchronization */
1210     if (sai->sync == SAI_SYNC_EXTERNAL) {
1211         /* Configure synchro client and provider */
1212         ret = sai->pdata->set_sync(sai->pdata, sai->np_sync_provider,
1213                        sai->synco, sai->synci);
1214         if (ret)
1215             return ret;
1216     }
1217 
1218     cr1_mask |= SAI_XCR1_SYNCEN_MASK;
1219     cr1 |= SAI_XCR1_SYNCEN_SET(sai->sync);
1220 
1221     return stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, cr1_mask, cr1);
1222 }
1223 
1224 static const struct snd_soc_dai_ops stm32_sai_pcm_dai_ops = {
1225     .set_sysclk = stm32_sai_set_sysclk,
1226     .set_fmt    = stm32_sai_set_dai_fmt,
1227     .set_tdm_slot   = stm32_sai_set_dai_tdm_slot,
1228     .startup    = stm32_sai_startup,
1229     .hw_params  = stm32_sai_hw_params,
1230     .trigger    = stm32_sai_trigger,
1231     .shutdown   = stm32_sai_shutdown,
1232 };
1233 
1234 static int stm32_sai_pcm_process_spdif(struct snd_pcm_substream *substream,
1235                        int channel, unsigned long hwoff,
1236                        void *buf, unsigned long bytes)
1237 {
1238     struct snd_pcm_runtime *runtime = substream->runtime;
1239     struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
1240     struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
1241     struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev);
1242     int *ptr = (int *)(runtime->dma_area + hwoff +
1243                channel * (runtime->dma_bytes / runtime->channels));
1244     ssize_t cnt = bytes_to_samples(runtime, bytes);
1245     unsigned int frm_cnt = sai->spdif_frm_cnt;
1246     unsigned int byte;
1247     unsigned int mask;
1248 
1249     do {
1250         *ptr = ((*ptr >> 8) & 0x00ffffff);
1251 
1252         /* Set channel status bit */
1253         byte = frm_cnt >> 3;
1254         mask = 1 << (frm_cnt - (byte << 3));
1255         if (sai->iec958.status[byte] & mask)
1256             *ptr |= 0x04000000;
1257         ptr++;
1258 
1259         if (!(cnt % 2))
1260             frm_cnt++;
1261 
1262         if (frm_cnt == SAI_IEC60958_BLOCK_FRAMES)
1263             frm_cnt = 0;
1264     } while (--cnt);
1265     sai->spdif_frm_cnt = frm_cnt;
1266 
1267     return 0;
1268 }
1269 
1270 /* No support of mmap in S/PDIF mode */
1271 static const struct snd_pcm_hardware stm32_sai_pcm_hw_spdif = {
1272     .info = SNDRV_PCM_INFO_INTERLEAVED,
1273     .buffer_bytes_max = 8 * PAGE_SIZE,
1274     .period_bytes_min = 1024,
1275     .period_bytes_max = PAGE_SIZE,
1276     .periods_min = 2,
1277     .periods_max = 8,
1278 };
1279 
1280 static const struct snd_pcm_hardware stm32_sai_pcm_hw = {
1281     .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP,
1282     .buffer_bytes_max = 8 * PAGE_SIZE,
1283     .period_bytes_min = 1024, /* 5ms at 48kHz */
1284     .period_bytes_max = PAGE_SIZE,
1285     .periods_min = 2,
1286     .periods_max = 8,
1287 };
1288 
1289 static struct snd_soc_dai_driver stm32_sai_playback_dai = {
1290         .probe = stm32_sai_dai_probe,
1291         .pcm_new = stm32_sai_pcm_new,
1292         .id = 1, /* avoid call to fmt_single_name() */
1293         .playback = {
1294             .channels_min = 1,
1295             .channels_max = 16,
1296             .rate_min = 8000,
1297             .rate_max = 192000,
1298             .rates = SNDRV_PCM_RATE_CONTINUOUS,
1299             /* DMA does not support 24 bits transfers */
1300             .formats =
1301                 SNDRV_PCM_FMTBIT_S8 |
1302                 SNDRV_PCM_FMTBIT_S16_LE |
1303                 SNDRV_PCM_FMTBIT_S32_LE,
1304         },
1305         .ops = &stm32_sai_pcm_dai_ops,
1306 };
1307 
1308 static struct snd_soc_dai_driver stm32_sai_capture_dai = {
1309         .probe = stm32_sai_dai_probe,
1310         .id = 1, /* avoid call to fmt_single_name() */
1311         .capture = {
1312             .channels_min = 1,
1313             .channels_max = 16,
1314             .rate_min = 8000,
1315             .rate_max = 192000,
1316             .rates = SNDRV_PCM_RATE_CONTINUOUS,
1317             /* DMA does not support 24 bits transfers */
1318             .formats =
1319                 SNDRV_PCM_FMTBIT_S8 |
1320                 SNDRV_PCM_FMTBIT_S16_LE |
1321                 SNDRV_PCM_FMTBIT_S32_LE,
1322         },
1323         .ops = &stm32_sai_pcm_dai_ops,
1324 };
1325 
1326 static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config = {
1327     .pcm_hardware = &stm32_sai_pcm_hw,
1328     .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1329 };
1330 
1331 static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config_spdif = {
1332     .pcm_hardware = &stm32_sai_pcm_hw_spdif,
1333     .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1334     .process = stm32_sai_pcm_process_spdif,
1335 };
1336 
1337 static const struct snd_soc_component_driver stm32_component = {
1338     .name = "stm32-sai",
1339     .legacy_dai_naming = 1,
1340 };
1341 
1342 static const struct of_device_id stm32_sai_sub_ids[] = {
1343     { .compatible = "st,stm32-sai-sub-a",
1344       .data = (void *)STM_SAI_A_ID},
1345     { .compatible = "st,stm32-sai-sub-b",
1346       .data = (void *)STM_SAI_B_ID},
1347     {}
1348 };
1349 MODULE_DEVICE_TABLE(of, stm32_sai_sub_ids);
1350 
1351 static int stm32_sai_sub_parse_of(struct platform_device *pdev,
1352                   struct stm32_sai_sub_data *sai)
1353 {
1354     struct device_node *np = pdev->dev.of_node;
1355     struct resource *res;
1356     void __iomem *base;
1357     struct of_phandle_args args;
1358     int ret;
1359 
1360     if (!np)
1361         return -ENODEV;
1362 
1363     base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1364     if (IS_ERR(base))
1365         return PTR_ERR(base);
1366 
1367     sai->phys_addr = res->start;
1368 
1369     sai->regmap_config = &stm32_sai_sub_regmap_config_f4;
1370     /* Note: PDM registers not available for sub-block B */
1371     if (STM_SAI_HAS_PDM(sai) && STM_SAI_IS_SUB_A(sai))
1372         sai->regmap_config = &stm32_sai_sub_regmap_config_h7;
1373 
1374     /*
1375      * Do not manage peripheral clock through regmap framework as this
1376      * can lead to circular locking issue with sai master clock provider.
1377      * Manage peripheral clock directly in driver instead.
1378      */
1379     sai->regmap = devm_regmap_init_mmio(&pdev->dev, base,
1380                         sai->regmap_config);
1381     if (IS_ERR(sai->regmap))
1382         return dev_err_probe(&pdev->dev, PTR_ERR(sai->regmap),
1383                      "Regmap init error\n");
1384 
1385     /* Get direction property */
1386     if (of_property_match_string(np, "dma-names", "tx") >= 0) {
1387         sai->dir = SNDRV_PCM_STREAM_PLAYBACK;
1388     } else if (of_property_match_string(np, "dma-names", "rx") >= 0) {
1389         sai->dir = SNDRV_PCM_STREAM_CAPTURE;
1390     } else {
1391         dev_err(&pdev->dev, "Unsupported direction\n");
1392         return -EINVAL;
1393     }
1394 
1395     /* Get spdif iec60958 property */
1396     sai->spdif = false;
1397     if (of_get_property(np, "st,iec60958", NULL)) {
1398         if (!STM_SAI_HAS_SPDIF(sai) ||
1399             sai->dir == SNDRV_PCM_STREAM_CAPTURE) {
1400             dev_err(&pdev->dev, "S/PDIF IEC60958 not supported\n");
1401             return -EINVAL;
1402         }
1403         stm32_sai_init_iec958_status(sai);
1404         sai->spdif = true;
1405         sai->master = true;
1406     }
1407 
1408     /* Get synchronization property */
1409     args.np = NULL;
1410     ret = of_parse_phandle_with_fixed_args(np, "st,sync", 1, 0, &args);
1411     if (ret < 0  && ret != -ENOENT) {
1412         dev_err(&pdev->dev, "Failed to get st,sync property\n");
1413         return ret;
1414     }
1415 
1416     sai->sync = SAI_SYNC_NONE;
1417     if (args.np) {
1418         if (args.np == np) {
1419             dev_err(&pdev->dev, "%pOFn sync own reference\n", np);
1420             of_node_put(args.np);
1421             return -EINVAL;
1422         }
1423 
1424         sai->np_sync_provider  = of_get_parent(args.np);
1425         if (!sai->np_sync_provider) {
1426             dev_err(&pdev->dev, "%pOFn parent node not found\n",
1427                 np);
1428             of_node_put(args.np);
1429             return -ENODEV;
1430         }
1431 
1432         sai->sync = SAI_SYNC_INTERNAL;
1433         if (sai->np_sync_provider != sai->pdata->pdev->dev.of_node) {
1434             if (!STM_SAI_HAS_EXT_SYNC(sai)) {
1435                 dev_err(&pdev->dev,
1436                     "External synchro not supported\n");
1437                 of_node_put(args.np);
1438                 return -EINVAL;
1439             }
1440             sai->sync = SAI_SYNC_EXTERNAL;
1441 
1442             sai->synci = args.args[0];
1443             if (sai->synci < 1 ||
1444                 (sai->synci > (SAI_GCR_SYNCIN_MAX + 1))) {
1445                 dev_err(&pdev->dev, "Wrong SAI index\n");
1446                 of_node_put(args.np);
1447                 return -EINVAL;
1448             }
1449 
1450             if (of_property_match_string(args.np, "compatible",
1451                              "st,stm32-sai-sub-a") >= 0)
1452                 sai->synco = STM_SAI_SYNC_OUT_A;
1453 
1454             if (of_property_match_string(args.np, "compatible",
1455                              "st,stm32-sai-sub-b") >= 0)
1456                 sai->synco = STM_SAI_SYNC_OUT_B;
1457 
1458             if (!sai->synco) {
1459                 dev_err(&pdev->dev, "Unknown SAI sub-block\n");
1460                 of_node_put(args.np);
1461                 return -EINVAL;
1462             }
1463         }
1464 
1465         dev_dbg(&pdev->dev, "%s synchronized with %s\n",
1466             pdev->name, args.np->full_name);
1467     }
1468 
1469     of_node_put(args.np);
1470     sai->sai_ck = devm_clk_get(&pdev->dev, "sai_ck");
1471     if (IS_ERR(sai->sai_ck))
1472         return dev_err_probe(&pdev->dev, PTR_ERR(sai->sai_ck),
1473                      "Missing kernel clock sai_ck\n");
1474 
1475     ret = clk_prepare(sai->pdata->pclk);
1476     if (ret < 0)
1477         return ret;
1478 
1479     if (STM_SAI_IS_F4(sai->pdata))
1480         return 0;
1481 
1482     /* Register mclk provider if requested */
1483     if (of_find_property(np, "#clock-cells", NULL)) {
1484         ret = stm32_sai_add_mclk_provider(sai);
1485         if (ret < 0)
1486             return ret;
1487     } else {
1488         sai->sai_mclk = devm_clk_get(&pdev->dev, "MCLK");
1489         if (IS_ERR(sai->sai_mclk)) {
1490             if (PTR_ERR(sai->sai_mclk) != -ENOENT)
1491                 return PTR_ERR(sai->sai_mclk);
1492             sai->sai_mclk = NULL;
1493         }
1494     }
1495 
1496     return 0;
1497 }
1498 
1499 static int stm32_sai_sub_probe(struct platform_device *pdev)
1500 {
1501     struct stm32_sai_sub_data *sai;
1502     const struct of_device_id *of_id;
1503     const struct snd_dmaengine_pcm_config *conf = &stm32_sai_pcm_config;
1504     int ret;
1505 
1506     sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
1507     if (!sai)
1508         return -ENOMEM;
1509 
1510     of_id = of_match_device(stm32_sai_sub_ids, &pdev->dev);
1511     if (!of_id)
1512         return -EINVAL;
1513     sai->id = (uintptr_t)of_id->data;
1514 
1515     sai->pdev = pdev;
1516     mutex_init(&sai->ctrl_lock);
1517     spin_lock_init(&sai->irq_lock);
1518     platform_set_drvdata(pdev, sai);
1519 
1520     sai->pdata = dev_get_drvdata(pdev->dev.parent);
1521     if (!sai->pdata) {
1522         dev_err(&pdev->dev, "Parent device data not available\n");
1523         return -EINVAL;
1524     }
1525 
1526     ret = stm32_sai_sub_parse_of(pdev, sai);
1527     if (ret)
1528         return ret;
1529 
1530     if (STM_SAI_IS_PLAYBACK(sai))
1531         sai->cpu_dai_drv = stm32_sai_playback_dai;
1532     else
1533         sai->cpu_dai_drv = stm32_sai_capture_dai;
1534     sai->cpu_dai_drv.name = dev_name(&pdev->dev);
1535 
1536     ret = devm_request_irq(&pdev->dev, sai->pdata->irq, stm32_sai_isr,
1537                    IRQF_SHARED, dev_name(&pdev->dev), sai);
1538     if (ret) {
1539         dev_err(&pdev->dev, "IRQ request returned %d\n", ret);
1540         return ret;
1541     }
1542 
1543     if (STM_SAI_PROTOCOL_IS_SPDIF(sai))
1544         conf = &stm32_sai_pcm_config_spdif;
1545 
1546     ret = snd_dmaengine_pcm_register(&pdev->dev, conf, 0);
1547     if (ret)
1548         return dev_err_probe(&pdev->dev, ret, "Could not register pcm dma\n");
1549 
1550     ret = snd_soc_register_component(&pdev->dev, &stm32_component,
1551                      &sai->cpu_dai_drv, 1);
1552     if (ret) {
1553         snd_dmaengine_pcm_unregister(&pdev->dev);
1554         return ret;
1555     }
1556 
1557     pm_runtime_enable(&pdev->dev);
1558 
1559     return 0;
1560 }
1561 
1562 static int stm32_sai_sub_remove(struct platform_device *pdev)
1563 {
1564     struct stm32_sai_sub_data *sai = dev_get_drvdata(&pdev->dev);
1565 
1566     clk_unprepare(sai->pdata->pclk);
1567     snd_dmaengine_pcm_unregister(&pdev->dev);
1568     snd_soc_unregister_component(&pdev->dev);
1569     pm_runtime_disable(&pdev->dev);
1570 
1571     return 0;
1572 }
1573 
1574 #ifdef CONFIG_PM_SLEEP
1575 static int stm32_sai_sub_suspend(struct device *dev)
1576 {
1577     struct stm32_sai_sub_data *sai = dev_get_drvdata(dev);
1578     int ret;
1579 
1580     ret = clk_enable(sai->pdata->pclk);
1581     if (ret < 0)
1582         return ret;
1583 
1584     regcache_cache_only(sai->regmap, true);
1585     regcache_mark_dirty(sai->regmap);
1586 
1587     clk_disable(sai->pdata->pclk);
1588 
1589     return 0;
1590 }
1591 
1592 static int stm32_sai_sub_resume(struct device *dev)
1593 {
1594     struct stm32_sai_sub_data *sai = dev_get_drvdata(dev);
1595     int ret;
1596 
1597     ret = clk_enable(sai->pdata->pclk);
1598     if (ret < 0)
1599         return ret;
1600 
1601     regcache_cache_only(sai->regmap, false);
1602     ret = regcache_sync(sai->regmap);
1603 
1604     clk_disable(sai->pdata->pclk);
1605 
1606     return ret;
1607 }
1608 #endif /* CONFIG_PM_SLEEP */
1609 
1610 static const struct dev_pm_ops stm32_sai_sub_pm_ops = {
1611     SET_SYSTEM_SLEEP_PM_OPS(stm32_sai_sub_suspend, stm32_sai_sub_resume)
1612 };
1613 
1614 static struct platform_driver stm32_sai_sub_driver = {
1615     .driver = {
1616         .name = "st,stm32-sai-sub",
1617         .of_match_table = stm32_sai_sub_ids,
1618         .pm = &stm32_sai_sub_pm_ops,
1619     },
1620     .probe = stm32_sai_sub_probe,
1621     .remove = stm32_sai_sub_remove,
1622 };
1623 
1624 module_platform_driver(stm32_sai_sub_driver);
1625 
1626 MODULE_DESCRIPTION("STM32 Soc SAI sub-block Interface");
1627 MODULE_AUTHOR("Olivier Moysan <olivier.moysan@st.com>");
1628 MODULE_ALIAS("platform:st,stm32-sai-sub");
1629 MODULE_LICENSE("GPL v2");
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