soc/stm/stm32_sai.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * STM32 ALSA SoC Digital Audio Interface (SAI) driver.
0004  *
0005  * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
0006  * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics.
0007  */
0008
0009 #include <linux/bitfield.h>
0010
0011 /******************** SAI Register Map **************************************/
0012
0013 /* Global configuration register */
0014 #define STM_SAI_GCR     0x00
0015
0016 /* Sub-block A&B registers offsets, relative to A&B sub-block addresses */
0017 #define STM_SAI_CR1_REGX    0x00    /* A offset: 0x04. B offset: 0x24 */
0018 #define STM_SAI_CR2_REGX    0x04
0019 #define STM_SAI_FRCR_REGX   0x08
0020 #define STM_SAI_SLOTR_REGX  0x0C
0021 #define STM_SAI_IMR_REGX    0x10
0022 #define STM_SAI_SR_REGX     0x14
0023 #define STM_SAI_CLRFR_REGX  0x18
0024 #define STM_SAI_DR_REGX     0x1C
0025
0026 /* Sub-block A registers, relative to sub-block A address */
0027 #define STM_SAI_PDMCR_REGX  0x40
0028 #define STM_SAI_PDMLY_REGX  0x44
0029
0030 /* Hardware configuration registers */
0031 #define STM_SAI_HWCFGR      0x3F0
0032 #define STM_SAI_VERR        0x3F4
0033 #define STM_SAI_IDR     0x3F8
0034 #define STM_SAI_SIDR        0x3FC
0035
0036 /******************** Bit definition for SAI_GCR register *******************/
0037 #define SAI_GCR_SYNCIN_SHIFT    0
0038 #define SAI_GCR_SYNCIN_WDTH 2
0039 #define SAI_GCR_SYNCIN_MASK GENMASK(1, SAI_GCR_SYNCIN_SHIFT)
0040 #define SAI_GCR_SYNCIN_MAX  FIELD_GET(SAI_GCR_SYNCIN_MASK,\
0041                 SAI_GCR_SYNCIN_MASK)
0042
0043 #define SAI_GCR_SYNCOUT_SHIFT   4
0044 #define SAI_GCR_SYNCOUT_MASK    GENMASK(5, SAI_GCR_SYNCOUT_SHIFT)
0045
0046 /******************* Bit definition for SAI_XCR1 register *******************/
0047 #define SAI_XCR1_RX_TX_SHIFT    0
0048 #define SAI_XCR1_RX_TX      BIT(SAI_XCR1_RX_TX_SHIFT)
0049 #define SAI_XCR1_SLAVE_SHIFT    1
0050 #define SAI_XCR1_SLAVE      BIT(SAI_XCR1_SLAVE_SHIFT)
0051
0052 #define SAI_XCR1_PRTCFG_SHIFT   2
0053 #define SAI_XCR1_PRTCFG_MASK    GENMASK(3, SAI_XCR1_PRTCFG_SHIFT)
0054 #define SAI_XCR1_PRTCFG_SET(x)  ((x) << SAI_XCR1_PRTCFG_SHIFT)
0055
0056 #define SAI_XCR1_DS_SHIFT   5
0057 #define SAI_XCR1_DS_MASK    GENMASK(7, SAI_XCR1_DS_SHIFT)
0058 #define SAI_XCR1_DS_SET(x)  ((x) << SAI_XCR1_DS_SHIFT)
0059
0060 #define SAI_XCR1_LSBFIRST_SHIFT 8
0061 #define SAI_XCR1_LSBFIRST   BIT(SAI_XCR1_LSBFIRST_SHIFT)
0062 #define SAI_XCR1_CKSTR_SHIFT    9
0063 #define SAI_XCR1_CKSTR      BIT(SAI_XCR1_CKSTR_SHIFT)
0064
0065 #define SAI_XCR1_SYNCEN_SHIFT   10
0066 #define SAI_XCR1_SYNCEN_MASK    GENMASK(11, SAI_XCR1_SYNCEN_SHIFT)
0067 #define SAI_XCR1_SYNCEN_SET(x)  ((x) << SAI_XCR1_SYNCEN_SHIFT)
0068
0069 #define SAI_XCR1_MONO_SHIFT 12
0070 #define SAI_XCR1_MONO       BIT(SAI_XCR1_MONO_SHIFT)
0071 #define SAI_XCR1_OUTDRIV_SHIFT  13
0072 #define SAI_XCR1_OUTDRIV    BIT(SAI_XCR1_OUTDRIV_SHIFT)
0073 #define SAI_XCR1_SAIEN_SHIFT    16
0074 #define SAI_XCR1_SAIEN      BIT(SAI_XCR1_SAIEN_SHIFT)
0075 #define SAI_XCR1_DMAEN_SHIFT    17
0076 #define SAI_XCR1_DMAEN      BIT(SAI_XCR1_DMAEN_SHIFT)
0077 #define SAI_XCR1_NODIV_SHIFT    19
0078 #define SAI_XCR1_NODIV      BIT(SAI_XCR1_NODIV_SHIFT)
0079
0080 #define SAI_XCR1_MCKDIV_SHIFT   20
0081 #define SAI_XCR1_MCKDIV_WIDTH(x)    (((x) == STM_SAI_STM32F4) ? 4 : 6)
0082 #define SAI_XCR1_MCKDIV_MASK(x) GENMASK((SAI_XCR1_MCKDIV_SHIFT + (x) - 1),\
0083                 SAI_XCR1_MCKDIV_SHIFT)
0084 #define SAI_XCR1_MCKDIV_SET(x)  ((x) << SAI_XCR1_MCKDIV_SHIFT)
0085 #define SAI_XCR1_MCKDIV_MAX(x)  ((1 << SAI_XCR1_MCKDIV_WIDTH(x)) - 1)
0086
0087 #define SAI_XCR1_OSR_SHIFT  26
0088 #define SAI_XCR1_OSR        BIT(SAI_XCR1_OSR_SHIFT)
0089
0090 #define SAI_XCR1_MCKEN_SHIFT    27
0091 #define SAI_XCR1_MCKEN      BIT(SAI_XCR1_MCKEN_SHIFT)
0092
0093 /******************* Bit definition for SAI_XCR2 register *******************/
0094 #define SAI_XCR2_FTH_SHIFT  0
0095 #define SAI_XCR2_FTH_MASK   GENMASK(2, SAI_XCR2_FTH_SHIFT)
0096 #define SAI_XCR2_FTH_SET(x) ((x) << SAI_XCR2_FTH_SHIFT)
0097
0098 #define SAI_XCR2_FFLUSH_SHIFT   3
0099 #define SAI_XCR2_FFLUSH     BIT(SAI_XCR2_FFLUSH_SHIFT)
0100 #define SAI_XCR2_TRIS_SHIFT 4
0101 #define SAI_XCR2_TRIS       BIT(SAI_XCR2_TRIS_SHIFT)
0102 #define SAI_XCR2_MUTE_SHIFT 5
0103 #define SAI_XCR2_MUTE       BIT(SAI_XCR2_MUTE_SHIFT)
0104 #define SAI_XCR2_MUTEVAL_SHIFT  6
0105 #define SAI_XCR2_MUTEVAL    BIT(SAI_XCR2_MUTEVAL_SHIFT)
0106
0107 #define SAI_XCR2_MUTECNT_SHIFT  7
0108 #define SAI_XCR2_MUTECNT_MASK   GENMASK(12, SAI_XCR2_MUTECNT_SHIFT)
0109 #define SAI_XCR2_MUTECNT_SET(x) ((x) << SAI_XCR2_MUTECNT_SHIFT)
0110
0111 #define SAI_XCR2_CPL_SHIFT  13
0112 #define SAI_XCR2_CPL        BIT(SAI_XCR2_CPL_SHIFT)
0113
0114 #define SAI_XCR2_COMP_SHIFT 14
0115 #define SAI_XCR2_COMP_MASK  GENMASK(15, SAI_XCR2_COMP_SHIFT)
0116 #define SAI_XCR2_COMP_SET(x)    ((x) << SAI_XCR2_COMP_SHIFT)
0117
0118 /****************** Bit definition for SAI_XFRCR register *******************/
0119 #define SAI_XFRCR_FRL_SHIFT 0
0120 #define SAI_XFRCR_FRL_MASK  GENMASK(7, SAI_XFRCR_FRL_SHIFT)
0121 #define SAI_XFRCR_FRL_SET(x)    ((x) << SAI_XFRCR_FRL_SHIFT)
0122
0123 #define SAI_XFRCR_FSALL_SHIFT   8
0124 #define SAI_XFRCR_FSALL_MASK    GENMASK(14, SAI_XFRCR_FSALL_SHIFT)
0125 #define SAI_XFRCR_FSALL_SET(x)  ((x) << SAI_XFRCR_FSALL_SHIFT)
0126
0127 #define SAI_XFRCR_FSDEF_SHIFT   16
0128 #define SAI_XFRCR_FSDEF     BIT(SAI_XFRCR_FSDEF_SHIFT)
0129 #define SAI_XFRCR_FSPOL_SHIFT   17
0130 #define SAI_XFRCR_FSPOL     BIT(SAI_XFRCR_FSPOL_SHIFT)
0131 #define SAI_XFRCR_FSOFF_SHIFT   18
0132 #define SAI_XFRCR_FSOFF     BIT(SAI_XFRCR_FSOFF_SHIFT)
0133
0134 /****************** Bit definition for SAI_XSLOTR register ******************/
0135 #define SAI_XSLOTR_FBOFF_SHIFT  0
0136 #define SAI_XSLOTR_FBOFF_MASK   GENMASK(4, SAI_XSLOTR_FBOFF_SHIFT)
0137 #define SAI_XSLOTR_FBOFF_SET(x) ((x) << SAI_XSLOTR_FBOFF_SHIFT)
0138
0139 #define SAI_XSLOTR_SLOTSZ_SHIFT 6
0140 #define SAI_XSLOTR_SLOTSZ_MASK  GENMASK(7, SAI_XSLOTR_SLOTSZ_SHIFT)
0141 #define SAI_XSLOTR_SLOTSZ_SET(x)    ((x) << SAI_XSLOTR_SLOTSZ_SHIFT)
0142
0143 #define SAI_XSLOTR_NBSLOT_SHIFT 8
0144 #define SAI_XSLOTR_NBSLOT_MASK  GENMASK(11, SAI_XSLOTR_NBSLOT_SHIFT)
0145 #define SAI_XSLOTR_NBSLOT_SET(x) ((x) << SAI_XSLOTR_NBSLOT_SHIFT)
0146
0147 #define SAI_XSLOTR_SLOTEN_SHIFT 16
0148 #define SAI_XSLOTR_SLOTEN_WIDTH 16
0149 #define SAI_XSLOTR_SLOTEN_MASK  GENMASK(31, SAI_XSLOTR_SLOTEN_SHIFT)
0150 #define SAI_XSLOTR_SLOTEN_SET(x) ((x) << SAI_XSLOTR_SLOTEN_SHIFT)
0151
0152 /******************* Bit definition for SAI_XIMR register *******************/
0153 #define SAI_XIMR_OVRUDRIE   BIT(0)
0154 #define SAI_XIMR_MUTEDETIE  BIT(1)
0155 #define SAI_XIMR_WCKCFGIE   BIT(2)
0156 #define SAI_XIMR_FREQIE     BIT(3)
0157 #define SAI_XIMR_CNRDYIE    BIT(4)
0158 #define SAI_XIMR_AFSDETIE   BIT(5)
0159 #define SAI_XIMR_LFSDETIE   BIT(6)
0160
0161 #define SAI_XIMR_SHIFT  0
0162 #define SAI_XIMR_MASK       GENMASK(6, SAI_XIMR_SHIFT)
0163
0164 /******************** Bit definition for SAI_XSR register *******************/
0165 #define SAI_XSR_OVRUDR      BIT(0)
0166 #define SAI_XSR_MUTEDET     BIT(1)
0167 #define SAI_XSR_WCKCFG      BIT(2)
0168 #define SAI_XSR_FREQ        BIT(3)
0169 #define SAI_XSR_CNRDY       BIT(4)
0170 #define SAI_XSR_AFSDET      BIT(5)
0171 #define SAI_XSR_LFSDET      BIT(6)
0172
0173 #define SAI_XSR_SHIFT   0
0174 #define SAI_XSR_MASK        GENMASK(6, SAI_XSR_SHIFT)
0175
0176 /****************** Bit definition for SAI_XCLRFR register ******************/
0177 #define SAI_XCLRFR_COVRUDR  BIT(0)
0178 #define SAI_XCLRFR_CMUTEDET BIT(1)
0179 #define SAI_XCLRFR_CWCKCFG  BIT(2)
0180 #define SAI_XCLRFR_CFREQ    BIT(3)
0181 #define SAI_XCLRFR_CCNRDY   BIT(4)
0182 #define SAI_XCLRFR_CAFSDET  BIT(5)
0183 #define SAI_XCLRFR_CLFSDET  BIT(6)
0184
0185 #define SAI_XCLRFR_SHIFT    0
0186 #define SAI_XCLRFR_MASK     GENMASK(6, SAI_XCLRFR_SHIFT)
0187
0188 /****************** Bit definition for SAI_PDMCR register ******************/
0189 #define SAI_PDMCR_PDMEN     BIT(0)
0190
0191 #define SAI_PDMCR_MICNBR_SHIFT  4
0192 #define SAI_PDMCR_MICNBR_MASK   GENMASK(5, SAI_PDMCR_MICNBR_SHIFT)
0193 #define SAI_PDMCR_MICNBR_SET(x) ((x) << SAI_PDMCR_MICNBR_SHIFT)
0194
0195 #define SAI_PDMCR_CKEN1     BIT(8)
0196 #define SAI_PDMCR_CKEN2     BIT(9)
0197 #define SAI_PDMCR_CKEN3     BIT(10)
0198 #define SAI_PDMCR_CKEN4     BIT(11)
0199
0200 /****************** Bit definition for (SAI_PDMDLY register ****************/
0201 #define SAI_PDMDLY_1L_SHIFT 0
0202 #define SAI_PDMDLY_1L_MASK  GENMASK(2, SAI_PDMDLY_1L_SHIFT)
0203 #define SAI_PDMDLY_1L_WIDTH 3
0204
0205 #define SAI_PDMDLY_1R_SHIFT 4
0206 #define SAI_PDMDLY_1R_MASK  GENMASK(6, SAI_PDMDLY_1R_SHIFT)
0207 #define SAI_PDMDLY_1R_WIDTH 3
0208
0209 #define SAI_PDMDLY_2L_SHIFT 8
0210 #define SAI_PDMDLY_2L_MASK  GENMASK(10, SAI_PDMDLY_2L_SHIFT)
0211 #define SAI_PDMDLY_2L_WIDTH 3
0212
0213 #define SAI_PDMDLY_2R_SHIFT 12
0214 #define SAI_PDMDLY_2R_MASK  GENMASK(14, SAI_PDMDLY_2R_SHIFT)
0215 #define SAI_PDMDLY_2R_WIDTH 3
0216
0217 #define SAI_PDMDLY_3L_SHIFT 16
0218 #define SAI_PDMDLY_3L_MASK  GENMASK(18, SAI_PDMDLY_3L_SHIFT)
0219 #define SAI_PDMDLY_3L_WIDTH 3
0220
0221 #define SAI_PDMDLY_3R_SHIFT 20
0222 #define SAI_PDMDLY_3R_MASK  GENMASK(22, SAI_PDMDLY_3R_SHIFT)
0223 #define SAI_PDMDLY_3R_WIDTH 3
0224
0225 #define SAI_PDMDLY_4L_SHIFT 24
0226 #define SAI_PDMDLY_4L_MASK  GENMASK(26, SAI_PDMDLY_4L_SHIFT)
0227 #define SAI_PDMDLY_4L_WIDTH 3
0228
0229 #define SAI_PDMDLY_4R_SHIFT 28
0230 #define SAI_PDMDLY_4R_MASK  GENMASK(30, SAI_PDMDLY_4R_SHIFT)
0231 #define SAI_PDMDLY_4R_WIDTH 3
0232
0233 /* Registers below apply to SAI version 2.1 and more */
0234
0235 /* Bit definition for SAI_HWCFGR register */
0236 #define SAI_HWCFGR_FIFO_SIZE    GENMASK(7, 0)
0237 #define SAI_HWCFGR_SPDIF_PDM    GENMASK(11, 8)
0238 #define SAI_HWCFGR_REGOUT   GENMASK(19, 12)
0239
0240 /* Bit definition for SAI_VERR register */
0241 #define SAI_VERR_MIN_MASK   GENMASK(3, 0)
0242 #define SAI_VERR_MAJ_MASK   GENMASK(7, 4)
0243
0244 /* Bit definition for SAI_IDR register */
0245 #define SAI_IDR_ID_MASK     GENMASK(31, 0)
0246
0247 /* Bit definition for SAI_SIDR register */
0248 #define SAI_SIDR_ID_MASK    GENMASK(31, 0)
0249
0250 #define SAI_IPIDR_NUMBER    0x00130031
0251
0252 /* SAI version numbers are 1.x for F4. Major version number set to 1 for F4 */
0253 #define STM_SAI_STM32F4     BIT(4)
0254 /* Dummy version number for H7 socs and next */
0255 #define STM_SAI_STM32H7     0x0
0256
0257 #define STM_SAI_IS_F4(ip)   ((ip)->conf.version == STM_SAI_STM32F4)
0258 #define STM_SAI_HAS_SPDIF_PDM(ip)\
0259                 ((ip)->pdata->conf.has_spdif_pdm)
0260
0261 enum stm32_sai_syncout {
0262     STM_SAI_SYNC_OUT_NONE,
0263     STM_SAI_SYNC_OUT_A,
0264     STM_SAI_SYNC_OUT_B,
0265 };
0266
0267 /**
0268  * struct stm32_sai_conf - SAI configuration
0269  * @version: SAI version
0270  * @fifo_size: SAI fifo size as words number
0271  * @has_spdif_pdm: SAI S/PDIF and PDM features support flag
0272  */
0273 struct stm32_sai_conf {
0274     u32 version;
0275     u32 fifo_size;
0276     bool has_spdif_pdm;
0277 };
0278
0279 /**
0280  * struct stm32_sai_data - private data of SAI instance driver
0281  * @pdev: device data pointer
0282  * @base: common register bank virtual base address
0283  * @pclk: SAI bus clock
0284  * @clk_x8k: SAI parent clock for sampling frequencies multiple of 8kHz
0285  * @clk_x11k: SAI parent clock for sampling frequencies multiple of 11kHz
0286  * @conf: SAI hardware capabitilites
0287  * @irq: SAI interrupt line
0288  * @set_sync: pointer to synchro mode configuration callback
0289  * @gcr: SAI Global Configuration Register
0290  */
0291 struct stm32_sai_data {
0292     struct platform_device *pdev;
0293     void __iomem *base;
0294     struct clk *pclk;
0295     struct clk *clk_x8k;
0296     struct clk *clk_x11k;
0297     struct stm32_sai_conf conf;
0298     int irq;
0299     int (*set_sync)(struct stm32_sai_data *sai,
0300             struct device_node *np_provider, int synco, int synci);
0301     u32 gcr;
0302 };