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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *  STM32 ALSA SoC Digital Audio Interface (I2S) driver.
0004  *
0005  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
0006  * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics.
0007  */
0008 
0009 #include <linux/bitfield.h>
0010 #include <linux/clk.h>
0011 #include <linux/clk-provider.h>
0012 #include <linux/delay.h>
0013 #include <linux/module.h>
0014 #include <linux/of_irq.h>
0015 #include <linux/of_platform.h>
0016 #include <linux/pm_runtime.h>
0017 #include <linux/regmap.h>
0018 #include <linux/reset.h>
0019 #include <linux/spinlock.h>
0020 
0021 #include <sound/dmaengine_pcm.h>
0022 #include <sound/pcm_params.h>
0023 
0024 #define STM32_I2S_CR1_REG   0x0
0025 #define STM32_I2S_CFG1_REG  0x08
0026 #define STM32_I2S_CFG2_REG  0x0C
0027 #define STM32_I2S_IER_REG   0x10
0028 #define STM32_I2S_SR_REG    0x14
0029 #define STM32_I2S_IFCR_REG  0x18
0030 #define STM32_I2S_TXDR_REG  0X20
0031 #define STM32_I2S_RXDR_REG  0x30
0032 #define STM32_I2S_CGFR_REG  0X50
0033 #define STM32_I2S_HWCFGR_REG    0x3F0
0034 #define STM32_I2S_VERR_REG  0x3F4
0035 #define STM32_I2S_IPIDR_REG 0x3F8
0036 #define STM32_I2S_SIDR_REG  0x3FC
0037 
0038 /* Bit definition for SPI2S_CR1 register */
0039 #define I2S_CR1_SPE     BIT(0)
0040 #define I2S_CR1_CSTART      BIT(9)
0041 #define I2S_CR1_CSUSP       BIT(10)
0042 #define I2S_CR1_HDDIR       BIT(11)
0043 #define I2S_CR1_SSI     BIT(12)
0044 #define I2S_CR1_CRC33_17    BIT(13)
0045 #define I2S_CR1_RCRCI       BIT(14)
0046 #define I2S_CR1_TCRCI       BIT(15)
0047 
0048 /* Bit definition for SPI_CFG2 register */
0049 #define I2S_CFG2_IOSWP_SHIFT    15
0050 #define I2S_CFG2_IOSWP      BIT(I2S_CFG2_IOSWP_SHIFT)
0051 #define I2S_CFG2_LSBFRST    BIT(23)
0052 #define I2S_CFG2_AFCNTR     BIT(31)
0053 
0054 /* Bit definition for SPI_CFG1 register */
0055 #define I2S_CFG1_FTHVL_SHIFT    5
0056 #define I2S_CFG1_FTHVL_MASK GENMASK(8, I2S_CFG1_FTHVL_SHIFT)
0057 #define I2S_CFG1_FTHVL_SET(x)   ((x) << I2S_CFG1_FTHVL_SHIFT)
0058 
0059 #define I2S_CFG1_TXDMAEN    BIT(15)
0060 #define I2S_CFG1_RXDMAEN    BIT(14)
0061 
0062 /* Bit definition for SPI2S_IER register */
0063 #define I2S_IER_RXPIE       BIT(0)
0064 #define I2S_IER_TXPIE       BIT(1)
0065 #define I2S_IER_DPXPIE      BIT(2)
0066 #define I2S_IER_EOTIE       BIT(3)
0067 #define I2S_IER_TXTFIE      BIT(4)
0068 #define I2S_IER_UDRIE       BIT(5)
0069 #define I2S_IER_OVRIE       BIT(6)
0070 #define I2S_IER_CRCEIE      BIT(7)
0071 #define I2S_IER_TIFREIE     BIT(8)
0072 #define I2S_IER_MODFIE      BIT(9)
0073 #define I2S_IER_TSERFIE     BIT(10)
0074 
0075 /* Bit definition for SPI2S_SR register */
0076 #define I2S_SR_RXP      BIT(0)
0077 #define I2S_SR_TXP      BIT(1)
0078 #define I2S_SR_DPXP     BIT(2)
0079 #define I2S_SR_EOT      BIT(3)
0080 #define I2S_SR_TXTF     BIT(4)
0081 #define I2S_SR_UDR      BIT(5)
0082 #define I2S_SR_OVR      BIT(6)
0083 #define I2S_SR_CRCERR       BIT(7)
0084 #define I2S_SR_TIFRE        BIT(8)
0085 #define I2S_SR_MODF     BIT(9)
0086 #define I2S_SR_TSERF        BIT(10)
0087 #define I2S_SR_SUSP     BIT(11)
0088 #define I2S_SR_TXC      BIT(12)
0089 #define I2S_SR_RXPLVL       GENMASK(14, 13)
0090 #define I2S_SR_RXWNE        BIT(15)
0091 
0092 #define I2S_SR_MASK     GENMASK(15, 0)
0093 
0094 /* Bit definition for SPI_IFCR register */
0095 #define I2S_IFCR_EOTC       BIT(3)
0096 #define I2S_IFCR_TXTFC      BIT(4)
0097 #define I2S_IFCR_UDRC       BIT(5)
0098 #define I2S_IFCR_OVRC       BIT(6)
0099 #define I2S_IFCR_CRCEC      BIT(7)
0100 #define I2S_IFCR_TIFREC     BIT(8)
0101 #define I2S_IFCR_MODFC      BIT(9)
0102 #define I2S_IFCR_TSERFC     BIT(10)
0103 #define I2S_IFCR_SUSPC      BIT(11)
0104 
0105 #define I2S_IFCR_MASK       GENMASK(11, 3)
0106 
0107 /* Bit definition for SPI_I2SCGFR register */
0108 #define I2S_CGFR_I2SMOD     BIT(0)
0109 
0110 #define I2S_CGFR_I2SCFG_SHIFT   1
0111 #define I2S_CGFR_I2SCFG_MASK    GENMASK(3, I2S_CGFR_I2SCFG_SHIFT)
0112 #define I2S_CGFR_I2SCFG_SET(x)  ((x) << I2S_CGFR_I2SCFG_SHIFT)
0113 
0114 #define I2S_CGFR_I2SSTD_SHIFT   4
0115 #define I2S_CGFR_I2SSTD_MASK    GENMASK(5, I2S_CGFR_I2SSTD_SHIFT)
0116 #define I2S_CGFR_I2SSTD_SET(x)  ((x) << I2S_CGFR_I2SSTD_SHIFT)
0117 
0118 #define I2S_CGFR_PCMSYNC    BIT(7)
0119 
0120 #define I2S_CGFR_DATLEN_SHIFT   8
0121 #define I2S_CGFR_DATLEN_MASK    GENMASK(9, I2S_CGFR_DATLEN_SHIFT)
0122 #define I2S_CGFR_DATLEN_SET(x)  ((x) << I2S_CGFR_DATLEN_SHIFT)
0123 
0124 #define I2S_CGFR_CHLEN_SHIFT    10
0125 #define I2S_CGFR_CHLEN      BIT(I2S_CGFR_CHLEN_SHIFT)
0126 #define I2S_CGFR_CKPOL      BIT(11)
0127 #define I2S_CGFR_FIXCH      BIT(12)
0128 #define I2S_CGFR_WSINV      BIT(13)
0129 #define I2S_CGFR_DATFMT     BIT(14)
0130 
0131 #define I2S_CGFR_I2SDIV_SHIFT   16
0132 #define I2S_CGFR_I2SDIV_BIT_H   23
0133 #define I2S_CGFR_I2SDIV_MASK    GENMASK(I2S_CGFR_I2SDIV_BIT_H,\
0134                 I2S_CGFR_I2SDIV_SHIFT)
0135 #define I2S_CGFR_I2SDIV_SET(x)  ((x) << I2S_CGFR_I2SDIV_SHIFT)
0136 #define I2S_CGFR_I2SDIV_MAX ((1 << (I2S_CGFR_I2SDIV_BIT_H -\
0137                 I2S_CGFR_I2SDIV_SHIFT)) - 1)
0138 
0139 #define I2S_CGFR_ODD_SHIFT  24
0140 #define I2S_CGFR_ODD        BIT(I2S_CGFR_ODD_SHIFT)
0141 #define I2S_CGFR_MCKOE      BIT(25)
0142 
0143 /* Registers below apply to I2S version 1.1 and more */
0144 
0145 /* Bit definition for SPI_HWCFGR register */
0146 #define I2S_HWCFGR_I2S_SUPPORT_MASK GENMASK(15, 12)
0147 
0148 /* Bit definition for SPI_VERR register */
0149 #define I2S_VERR_MIN_MASK   GENMASK(3, 0)
0150 #define I2S_VERR_MAJ_MASK   GENMASK(7, 4)
0151 
0152 /* Bit definition for SPI_IPIDR register */
0153 #define I2S_IPIDR_ID_MASK   GENMASK(31, 0)
0154 
0155 /* Bit definition for SPI_SIDR register */
0156 #define I2S_SIDR_ID_MASK    GENMASK(31, 0)
0157 
0158 #define I2S_IPIDR_NUMBER    0x00130022
0159 
0160 enum i2s_master_mode {
0161     I2S_MS_NOT_SET,
0162     I2S_MS_MASTER,
0163     I2S_MS_SLAVE,
0164 };
0165 
0166 enum i2s_mode {
0167     I2S_I2SMOD_TX_SLAVE,
0168     I2S_I2SMOD_RX_SLAVE,
0169     I2S_I2SMOD_TX_MASTER,
0170     I2S_I2SMOD_RX_MASTER,
0171     I2S_I2SMOD_FD_SLAVE,
0172     I2S_I2SMOD_FD_MASTER,
0173 };
0174 
0175 enum i2s_fifo_th {
0176     I2S_FIFO_TH_NONE,
0177     I2S_FIFO_TH_ONE_QUARTER,
0178     I2S_FIFO_TH_HALF,
0179     I2S_FIFO_TH_THREE_QUARTER,
0180     I2S_FIFO_TH_FULL,
0181 };
0182 
0183 enum i2s_std {
0184     I2S_STD_I2S,
0185     I2S_STD_LEFT_J,
0186     I2S_STD_RIGHT_J,
0187     I2S_STD_DSP,
0188 };
0189 
0190 enum i2s_datlen {
0191     I2S_I2SMOD_DATLEN_16,
0192     I2S_I2SMOD_DATLEN_24,
0193     I2S_I2SMOD_DATLEN_32,
0194 };
0195 
0196 #define STM32_I2S_FIFO_SIZE     16
0197 
0198 #define STM32_I2S_IS_MASTER(x)      ((x)->ms_flg == I2S_MS_MASTER)
0199 #define STM32_I2S_IS_SLAVE(x)       ((x)->ms_flg == I2S_MS_SLAVE)
0200 
0201 #define STM32_I2S_NAME_LEN      32
0202 #define STM32_I2S_RATE_11K      11025
0203 
0204 /**
0205  * struct stm32_i2s_data - private data of I2S
0206  * @regmap_conf: I2S register map configuration pointer
0207  * @regmap: I2S register map pointer
0208  * @pdev: device data pointer
0209  * @dai_drv: DAI driver pointer
0210  * @dma_data_tx: dma configuration data for tx channel
0211  * @dma_data_rx: dma configuration data for tx channel
0212  * @substream: PCM substream data pointer
0213  * @i2sclk: kernel clock feeding the I2S clock generator
0214  * @i2smclk: master clock from I2S mclk provider
0215  * @pclk: peripheral clock driving bus interface
0216  * @x8kclk: I2S parent clock for sampling frequencies multiple of 8kHz
0217  * @x11kclk: I2S parent clock for sampling frequencies multiple of 11kHz
0218  * @base:  mmio register base virtual address
0219  * @phys_addr: I2S registers physical base address
0220  * @lock_fd: lock to manage race conditions in full duplex mode
0221  * @irq_lock: prevent race condition with IRQ
0222  * @mclk_rate: master clock frequency (Hz)
0223  * @fmt: DAI protocol
0224  * @divider: prescaler division ratio
0225  * @div: prescaler div field
0226  * @odd: prescaler odd field
0227  * @refcount: keep count of opened streams on I2S
0228  * @ms_flg: master mode flag.
0229  */
0230 struct stm32_i2s_data {
0231     const struct regmap_config *regmap_conf;
0232     struct regmap *regmap;
0233     struct platform_device *pdev;
0234     struct snd_soc_dai_driver *dai_drv;
0235     struct snd_dmaengine_dai_dma_data dma_data_tx;
0236     struct snd_dmaengine_dai_dma_data dma_data_rx;
0237     struct snd_pcm_substream *substream;
0238     struct clk *i2sclk;
0239     struct clk *i2smclk;
0240     struct clk *pclk;
0241     struct clk *x8kclk;
0242     struct clk *x11kclk;
0243     void __iomem *base;
0244     dma_addr_t phys_addr;
0245     spinlock_t lock_fd; /* Manage race conditions for full duplex */
0246     spinlock_t irq_lock; /* used to prevent race condition with IRQ */
0247     unsigned int mclk_rate;
0248     unsigned int fmt;
0249     unsigned int divider;
0250     unsigned int div;
0251     bool odd;
0252     int refcount;
0253     int ms_flg;
0254 };
0255 
0256 struct stm32_i2smclk_data {
0257     struct clk_hw hw;
0258     unsigned long freq;
0259     struct stm32_i2s_data *i2s_data;
0260 };
0261 
0262 #define to_mclk_data(_hw) container_of(_hw, struct stm32_i2smclk_data, hw)
0263 
0264 static int stm32_i2s_calc_clk_div(struct stm32_i2s_data *i2s,
0265                   unsigned long input_rate,
0266                   unsigned long output_rate)
0267 {
0268     unsigned int ratio, div, divider = 1;
0269     bool odd;
0270 
0271     ratio = DIV_ROUND_CLOSEST(input_rate, output_rate);
0272 
0273     /* Check the parity of the divider */
0274     odd = ratio & 0x1;
0275 
0276     /* Compute the div prescaler */
0277     div = ratio >> 1;
0278 
0279     /* If div is 0 actual divider is 1 */
0280     if (div) {
0281         divider = ((2 * div) + odd);
0282         dev_dbg(&i2s->pdev->dev, "Divider: 2*%d(div)+%d(odd) = %d\n",
0283             div, odd, divider);
0284     }
0285 
0286     /* Division by three is not allowed by I2S prescaler */
0287     if ((div == 1 && odd) || div > I2S_CGFR_I2SDIV_MAX) {
0288         dev_err(&i2s->pdev->dev, "Wrong divider setting\n");
0289         return -EINVAL;
0290     }
0291 
0292     if (input_rate % divider)
0293         dev_dbg(&i2s->pdev->dev,
0294             "Rate not accurate. requested (%ld), actual (%ld)\n",
0295             output_rate, input_rate / divider);
0296 
0297     i2s->div = div;
0298     i2s->odd = odd;
0299     i2s->divider = divider;
0300 
0301     return 0;
0302 }
0303 
0304 static int stm32_i2s_set_clk_div(struct stm32_i2s_data *i2s)
0305 {
0306     u32 cgfr, cgfr_mask;
0307 
0308     cgfr = I2S_CGFR_I2SDIV_SET(i2s->div) | (i2s->odd << I2S_CGFR_ODD_SHIFT);
0309     cgfr_mask = I2S_CGFR_I2SDIV_MASK | I2S_CGFR_ODD;
0310 
0311     return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
0312                   cgfr_mask, cgfr);
0313 }
0314 
0315 static int stm32_i2s_set_parent_clock(struct stm32_i2s_data *i2s,
0316                       unsigned int rate)
0317 {
0318     struct platform_device *pdev = i2s->pdev;
0319     struct clk *parent_clk;
0320     int ret;
0321 
0322     if (!(rate % STM32_I2S_RATE_11K))
0323         parent_clk = i2s->x11kclk;
0324     else
0325         parent_clk = i2s->x8kclk;
0326 
0327     ret = clk_set_parent(i2s->i2sclk, parent_clk);
0328     if (ret)
0329         dev_err(&pdev->dev,
0330             "Error %d setting i2sclk parent clock\n", ret);
0331 
0332     return ret;
0333 }
0334 
0335 static long stm32_i2smclk_round_rate(struct clk_hw *hw, unsigned long rate,
0336                      unsigned long *prate)
0337 {
0338     struct stm32_i2smclk_data *mclk = to_mclk_data(hw);
0339     struct stm32_i2s_data *i2s = mclk->i2s_data;
0340     int ret;
0341 
0342     ret = stm32_i2s_calc_clk_div(i2s, *prate, rate);
0343     if (ret)
0344         return ret;
0345 
0346     mclk->freq = *prate / i2s->divider;
0347 
0348     return mclk->freq;
0349 }
0350 
0351 static unsigned long stm32_i2smclk_recalc_rate(struct clk_hw *hw,
0352                            unsigned long parent_rate)
0353 {
0354     struct stm32_i2smclk_data *mclk = to_mclk_data(hw);
0355 
0356     return mclk->freq;
0357 }
0358 
0359 static int stm32_i2smclk_set_rate(struct clk_hw *hw, unsigned long rate,
0360                   unsigned long parent_rate)
0361 {
0362     struct stm32_i2smclk_data *mclk = to_mclk_data(hw);
0363     struct stm32_i2s_data *i2s = mclk->i2s_data;
0364     int ret;
0365 
0366     ret = stm32_i2s_calc_clk_div(i2s, parent_rate, rate);
0367     if (ret)
0368         return ret;
0369 
0370     ret = stm32_i2s_set_clk_div(i2s);
0371     if (ret)
0372         return ret;
0373 
0374     mclk->freq = rate;
0375 
0376     return 0;
0377 }
0378 
0379 static int stm32_i2smclk_enable(struct clk_hw *hw)
0380 {
0381     struct stm32_i2smclk_data *mclk = to_mclk_data(hw);
0382     struct stm32_i2s_data *i2s = mclk->i2s_data;
0383 
0384     dev_dbg(&i2s->pdev->dev, "Enable master clock\n");
0385 
0386     return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
0387                     I2S_CGFR_MCKOE, I2S_CGFR_MCKOE);
0388 }
0389 
0390 static void stm32_i2smclk_disable(struct clk_hw *hw)
0391 {
0392     struct stm32_i2smclk_data *mclk = to_mclk_data(hw);
0393     struct stm32_i2s_data *i2s = mclk->i2s_data;
0394 
0395     dev_dbg(&i2s->pdev->dev, "Disable master clock\n");
0396 
0397     regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG, I2S_CGFR_MCKOE, 0);
0398 }
0399 
0400 static const struct clk_ops mclk_ops = {
0401     .enable = stm32_i2smclk_enable,
0402     .disable = stm32_i2smclk_disable,
0403     .recalc_rate = stm32_i2smclk_recalc_rate,
0404     .round_rate = stm32_i2smclk_round_rate,
0405     .set_rate = stm32_i2smclk_set_rate,
0406 };
0407 
0408 static int stm32_i2s_add_mclk_provider(struct stm32_i2s_data *i2s)
0409 {
0410     struct clk_hw *hw;
0411     struct stm32_i2smclk_data *mclk;
0412     struct device *dev = &i2s->pdev->dev;
0413     const char *pname = __clk_get_name(i2s->i2sclk);
0414     char *mclk_name, *p, *s = (char *)pname;
0415     int ret, i = 0;
0416 
0417     mclk = devm_kzalloc(dev, sizeof(*mclk), GFP_KERNEL);
0418     if (!mclk)
0419         return -ENOMEM;
0420 
0421     mclk_name = devm_kcalloc(dev, sizeof(char),
0422                  STM32_I2S_NAME_LEN, GFP_KERNEL);
0423     if (!mclk_name)
0424         return -ENOMEM;
0425 
0426     /*
0427      * Forge mclk clock name from parent clock name and suffix.
0428      * String after "_" char is stripped in parent name.
0429      */
0430     p = mclk_name;
0431     while (*s && *s != '_' && (i < (STM32_I2S_NAME_LEN - 7))) {
0432         *p++ = *s++;
0433         i++;
0434     }
0435     strcat(p, "_mclk");
0436 
0437     mclk->hw.init = CLK_HW_INIT(mclk_name, pname, &mclk_ops, 0);
0438     mclk->i2s_data = i2s;
0439     hw = &mclk->hw;
0440 
0441     dev_dbg(dev, "Register master clock %s\n", mclk_name);
0442     ret = devm_clk_hw_register(&i2s->pdev->dev, hw);
0443     if (ret) {
0444         dev_err(dev, "mclk register fails with error %d\n", ret);
0445         return ret;
0446     }
0447     i2s->i2smclk = hw->clk;
0448 
0449     /* register mclk provider */
0450     return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
0451 }
0452 
0453 static irqreturn_t stm32_i2s_isr(int irq, void *devid)
0454 {
0455     struct stm32_i2s_data *i2s = (struct stm32_i2s_data *)devid;
0456     struct platform_device *pdev = i2s->pdev;
0457     u32 sr, ier;
0458     unsigned long flags;
0459     int err = 0;
0460 
0461     regmap_read(i2s->regmap, STM32_I2S_SR_REG, &sr);
0462     regmap_read(i2s->regmap, STM32_I2S_IER_REG, &ier);
0463 
0464     flags = sr & ier;
0465     if (!flags) {
0466         dev_dbg(&pdev->dev, "Spurious IRQ sr=0x%08x, ier=0x%08x\n",
0467             sr, ier);
0468         return IRQ_NONE;
0469     }
0470 
0471     regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,
0472               I2S_IFCR_MASK, flags);
0473 
0474     if (flags & I2S_SR_OVR) {
0475         dev_dbg(&pdev->dev, "Overrun\n");
0476         err = 1;
0477     }
0478 
0479     if (flags & I2S_SR_UDR) {
0480         dev_dbg(&pdev->dev, "Underrun\n");
0481         err = 1;
0482     }
0483 
0484     if (flags & I2S_SR_TIFRE)
0485         dev_dbg(&pdev->dev, "Frame error\n");
0486 
0487     spin_lock(&i2s->irq_lock);
0488     if (err && i2s->substream)
0489         snd_pcm_stop_xrun(i2s->substream);
0490     spin_unlock(&i2s->irq_lock);
0491 
0492     return IRQ_HANDLED;
0493 }
0494 
0495 static bool stm32_i2s_readable_reg(struct device *dev, unsigned int reg)
0496 {
0497     switch (reg) {
0498     case STM32_I2S_CR1_REG:
0499     case STM32_I2S_CFG1_REG:
0500     case STM32_I2S_CFG2_REG:
0501     case STM32_I2S_IER_REG:
0502     case STM32_I2S_SR_REG:
0503     case STM32_I2S_RXDR_REG:
0504     case STM32_I2S_CGFR_REG:
0505     case STM32_I2S_HWCFGR_REG:
0506     case STM32_I2S_VERR_REG:
0507     case STM32_I2S_IPIDR_REG:
0508     case STM32_I2S_SIDR_REG:
0509         return true;
0510     default:
0511         return false;
0512     }
0513 }
0514 
0515 static bool stm32_i2s_volatile_reg(struct device *dev, unsigned int reg)
0516 {
0517     switch (reg) {
0518     case STM32_I2S_SR_REG:
0519     case STM32_I2S_RXDR_REG:
0520         return true;
0521     default:
0522         return false;
0523     }
0524 }
0525 
0526 static bool stm32_i2s_writeable_reg(struct device *dev, unsigned int reg)
0527 {
0528     switch (reg) {
0529     case STM32_I2S_CR1_REG:
0530     case STM32_I2S_CFG1_REG:
0531     case STM32_I2S_CFG2_REG:
0532     case STM32_I2S_IER_REG:
0533     case STM32_I2S_IFCR_REG:
0534     case STM32_I2S_TXDR_REG:
0535     case STM32_I2S_CGFR_REG:
0536         return true;
0537     default:
0538         return false;
0539     }
0540 }
0541 
0542 static int stm32_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
0543 {
0544     struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
0545     u32 cgfr;
0546     u32 cgfr_mask =  I2S_CGFR_I2SSTD_MASK | I2S_CGFR_CKPOL |
0547              I2S_CGFR_WSINV | I2S_CGFR_I2SCFG_MASK;
0548 
0549     dev_dbg(cpu_dai->dev, "fmt %x\n", fmt);
0550 
0551     /*
0552      * winv = 0 : default behavior (high/low) for all standards
0553      * ckpol = 0 for all standards.
0554      */
0555     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0556     case SND_SOC_DAIFMT_I2S:
0557         cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_I2S);
0558         break;
0559     case SND_SOC_DAIFMT_MSB:
0560         cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_LEFT_J);
0561         break;
0562     case SND_SOC_DAIFMT_LSB:
0563         cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_RIGHT_J);
0564         break;
0565     case SND_SOC_DAIFMT_DSP_A:
0566         cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_DSP);
0567         break;
0568     /* DSP_B not mapped on I2S PCM long format. 1 bit offset does not fit */
0569     default:
0570         dev_err(cpu_dai->dev, "Unsupported protocol %#x\n",
0571             fmt & SND_SOC_DAIFMT_FORMAT_MASK);
0572         return -EINVAL;
0573     }
0574 
0575     /* DAI clock strobing */
0576     switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
0577     case SND_SOC_DAIFMT_NB_NF:
0578         break;
0579     case SND_SOC_DAIFMT_IB_NF:
0580         cgfr |= I2S_CGFR_CKPOL;
0581         break;
0582     case SND_SOC_DAIFMT_NB_IF:
0583         cgfr |= I2S_CGFR_WSINV;
0584         break;
0585     case SND_SOC_DAIFMT_IB_IF:
0586         cgfr |= I2S_CGFR_CKPOL;
0587         cgfr |= I2S_CGFR_WSINV;
0588         break;
0589     default:
0590         dev_err(cpu_dai->dev, "Unsupported strobing %#x\n",
0591             fmt & SND_SOC_DAIFMT_INV_MASK);
0592         return -EINVAL;
0593     }
0594 
0595     /* DAI clock master masks */
0596     switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
0597     case SND_SOC_DAIFMT_BC_FC:
0598         i2s->ms_flg = I2S_MS_SLAVE;
0599         break;
0600     case SND_SOC_DAIFMT_BP_FP:
0601         i2s->ms_flg = I2S_MS_MASTER;
0602         break;
0603     default:
0604         dev_err(cpu_dai->dev, "Unsupported mode %#x\n",
0605             fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK);
0606         return -EINVAL;
0607     }
0608 
0609     i2s->fmt = fmt;
0610     return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
0611                   cgfr_mask, cgfr);
0612 }
0613 
0614 static int stm32_i2s_set_sysclk(struct snd_soc_dai *cpu_dai,
0615                 int clk_id, unsigned int freq, int dir)
0616 {
0617     struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
0618     int ret = 0;
0619 
0620     dev_dbg(cpu_dai->dev, "I2S MCLK frequency is %uHz. mode: %s, dir: %s\n",
0621         freq, STM32_I2S_IS_MASTER(i2s) ? "master" : "slave",
0622         dir ? "output" : "input");
0623 
0624     /* MCLK generation is available only in master mode */
0625     if (dir == SND_SOC_CLOCK_OUT && STM32_I2S_IS_MASTER(i2s)) {
0626         if (!i2s->i2smclk) {
0627             dev_dbg(cpu_dai->dev, "No MCLK registered\n");
0628             return 0;
0629         }
0630 
0631         /* Assume shutdown if requested frequency is 0Hz */
0632         if (!freq) {
0633             /* Release mclk rate only if rate was actually set */
0634             if (i2s->mclk_rate) {
0635                 clk_rate_exclusive_put(i2s->i2smclk);
0636                 i2s->mclk_rate = 0;
0637             }
0638             return regmap_update_bits(i2s->regmap,
0639                           STM32_I2S_CGFR_REG,
0640                           I2S_CGFR_MCKOE, 0);
0641         }
0642         /* If master clock is used, set parent clock now */
0643         ret = stm32_i2s_set_parent_clock(i2s, freq);
0644         if (ret)
0645             return ret;
0646         ret = clk_set_rate_exclusive(i2s->i2smclk, freq);
0647         if (ret) {
0648             dev_err(cpu_dai->dev, "Could not set mclk rate\n");
0649             return ret;
0650         }
0651         ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
0652                      I2S_CGFR_MCKOE, I2S_CGFR_MCKOE);
0653         if (!ret)
0654             i2s->mclk_rate = freq;
0655     }
0656 
0657     return ret;
0658 }
0659 
0660 static int stm32_i2s_configure_clock(struct snd_soc_dai *cpu_dai,
0661                      struct snd_pcm_hw_params *params)
0662 {
0663     struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
0664     unsigned long i2s_clock_rate;
0665     unsigned int nb_bits, frame_len;
0666     unsigned int rate = params_rate(params);
0667     u32 cgfr;
0668     int ret;
0669 
0670     if (!(rate % 11025))
0671         clk_set_parent(i2s->i2sclk, i2s->x11kclk);
0672     else
0673         clk_set_parent(i2s->i2sclk, i2s->x8kclk);
0674     i2s_clock_rate = clk_get_rate(i2s->i2sclk);
0675 
0676     /*
0677      * mckl = mclk_ratio x ws
0678      *   i2s mode : mclk_ratio = 256
0679      *   dsp mode : mclk_ratio = 128
0680      *
0681      * mclk on
0682      *   i2s mode : div = i2s_clk / (mclk_ratio * ws)
0683      *   dsp mode : div = i2s_clk / (mclk_ratio * ws)
0684      * mclk off
0685      *   i2s mode : div = i2s_clk / (nb_bits x ws)
0686      *   dsp mode : div = i2s_clk / (nb_bits x ws)
0687      */
0688     if (i2s->mclk_rate) {
0689         ret = stm32_i2s_calc_clk_div(i2s, i2s_clock_rate,
0690                          i2s->mclk_rate);
0691         if (ret)
0692             return ret;
0693     } else {
0694         frame_len = 32;
0695         if ((i2s->fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==
0696             SND_SOC_DAIFMT_DSP_A)
0697             frame_len = 16;
0698 
0699         /* master clock not enabled */
0700         ret = regmap_read(i2s->regmap, STM32_I2S_CGFR_REG, &cgfr);
0701         if (ret < 0)
0702             return ret;
0703 
0704         nb_bits = frame_len * (FIELD_GET(I2S_CGFR_CHLEN, cgfr) + 1);
0705         ret = stm32_i2s_calc_clk_div(i2s, i2s_clock_rate,
0706                          (nb_bits * rate));
0707         if (ret)
0708             return ret;
0709     }
0710 
0711     ret = stm32_i2s_set_clk_div(i2s);
0712     if (ret < 0)
0713         return ret;
0714 
0715     /* Set bitclock and frameclock to their inactive state */
0716     return regmap_update_bits(i2s->regmap, STM32_I2S_CFG2_REG,
0717                   I2S_CFG2_AFCNTR, I2S_CFG2_AFCNTR);
0718 }
0719 
0720 static int stm32_i2s_configure(struct snd_soc_dai *cpu_dai,
0721                    struct snd_pcm_hw_params *params,
0722                    struct snd_pcm_substream *substream)
0723 {
0724     struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
0725     int format = params_width(params);
0726     u32 cfgr, cfgr_mask, cfg1;
0727     unsigned int fthlv;
0728     int ret;
0729 
0730     switch (format) {
0731     case 16:
0732         cfgr = I2S_CGFR_DATLEN_SET(I2S_I2SMOD_DATLEN_16);
0733         cfgr_mask = I2S_CGFR_DATLEN_MASK | I2S_CGFR_CHLEN;
0734         break;
0735     case 32:
0736         cfgr = I2S_CGFR_DATLEN_SET(I2S_I2SMOD_DATLEN_32) |
0737                        I2S_CGFR_CHLEN;
0738         cfgr_mask = I2S_CGFR_DATLEN_MASK | I2S_CGFR_CHLEN;
0739         break;
0740     default:
0741         dev_err(cpu_dai->dev, "Unexpected format %d", format);
0742         return -EINVAL;
0743     }
0744 
0745     if (STM32_I2S_IS_SLAVE(i2s)) {
0746         cfgr |= I2S_CGFR_I2SCFG_SET(I2S_I2SMOD_FD_SLAVE);
0747 
0748         /* As data length is either 16 or 32 bits, fixch always set */
0749         cfgr |= I2S_CGFR_FIXCH;
0750         cfgr_mask |= I2S_CGFR_FIXCH;
0751     } else {
0752         cfgr |= I2S_CGFR_I2SCFG_SET(I2S_I2SMOD_FD_MASTER);
0753     }
0754     cfgr_mask |= I2S_CGFR_I2SCFG_MASK;
0755 
0756     ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
0757                  cfgr_mask, cfgr);
0758     if (ret < 0)
0759         return ret;
0760 
0761     fthlv = STM32_I2S_FIFO_SIZE * I2S_FIFO_TH_ONE_QUARTER / 4;
0762     cfg1 = I2S_CFG1_FTHVL_SET(fthlv - 1);
0763 
0764     return regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,
0765                   I2S_CFG1_FTHVL_MASK, cfg1);
0766 }
0767 
0768 static int stm32_i2s_startup(struct snd_pcm_substream *substream,
0769                  struct snd_soc_dai *cpu_dai)
0770 {
0771     struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
0772     unsigned long flags;
0773     int ret;
0774 
0775     spin_lock_irqsave(&i2s->irq_lock, flags);
0776     i2s->substream = substream;
0777     spin_unlock_irqrestore(&i2s->irq_lock, flags);
0778 
0779     if ((i2s->fmt & SND_SOC_DAIFMT_FORMAT_MASK) != SND_SOC_DAIFMT_DSP_A)
0780         snd_pcm_hw_constraint_single(substream->runtime,
0781                          SNDRV_PCM_HW_PARAM_CHANNELS, 2);
0782 
0783     ret = clk_prepare_enable(i2s->i2sclk);
0784     if (ret < 0) {
0785         dev_err(cpu_dai->dev, "Failed to enable clock: %d\n", ret);
0786         return ret;
0787     }
0788 
0789     return regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,
0790                  I2S_IFCR_MASK, I2S_IFCR_MASK);
0791 }
0792 
0793 static int stm32_i2s_hw_params(struct snd_pcm_substream *substream,
0794                    struct snd_pcm_hw_params *params,
0795                    struct snd_soc_dai *cpu_dai)
0796 {
0797     struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
0798     int ret;
0799 
0800     ret = stm32_i2s_configure(cpu_dai, params, substream);
0801     if (ret < 0) {
0802         dev_err(cpu_dai->dev, "Configuration returned error %d\n", ret);
0803         return ret;
0804     }
0805 
0806     if (STM32_I2S_IS_MASTER(i2s))
0807         ret = stm32_i2s_configure_clock(cpu_dai, params);
0808 
0809     return ret;
0810 }
0811 
0812 static int stm32_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
0813                  struct snd_soc_dai *cpu_dai)
0814 {
0815     struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
0816     bool playback_flg = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
0817     u32 cfg1_mask, ier;
0818     int ret;
0819 
0820     switch (cmd) {
0821     case SNDRV_PCM_TRIGGER_START:
0822     case SNDRV_PCM_TRIGGER_RESUME:
0823     case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
0824         /* Enable i2s */
0825         dev_dbg(cpu_dai->dev, "start I2S %s\n",
0826             playback_flg ? "playback" : "capture");
0827 
0828         cfg1_mask = I2S_CFG1_RXDMAEN | I2S_CFG1_TXDMAEN;
0829         regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,
0830                    cfg1_mask, cfg1_mask);
0831 
0832         ret = regmap_update_bits(i2s->regmap, STM32_I2S_CR1_REG,
0833                      I2S_CR1_SPE, I2S_CR1_SPE);
0834         if (ret < 0) {
0835             dev_err(cpu_dai->dev, "Error %d enabling I2S\n", ret);
0836             return ret;
0837         }
0838 
0839         ret = regmap_write_bits(i2s->regmap, STM32_I2S_CR1_REG,
0840                     I2S_CR1_CSTART, I2S_CR1_CSTART);
0841         if (ret < 0) {
0842             dev_err(cpu_dai->dev, "Error %d starting I2S\n", ret);
0843             return ret;
0844         }
0845 
0846         regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,
0847                   I2S_IFCR_MASK, I2S_IFCR_MASK);
0848 
0849         spin_lock(&i2s->lock_fd);
0850         i2s->refcount++;
0851         if (playback_flg) {
0852             ier = I2S_IER_UDRIE;
0853         } else {
0854             ier = I2S_IER_OVRIE;
0855 
0856             if (STM32_I2S_IS_MASTER(i2s) && i2s->refcount == 1)
0857                 /* dummy write to gate bus clocks */
0858                 regmap_write(i2s->regmap,
0859                          STM32_I2S_TXDR_REG, 0);
0860         }
0861         spin_unlock(&i2s->lock_fd);
0862 
0863         if (STM32_I2S_IS_SLAVE(i2s))
0864             ier |= I2S_IER_TIFREIE;
0865 
0866         regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG, ier, ier);
0867         break;
0868     case SNDRV_PCM_TRIGGER_STOP:
0869     case SNDRV_PCM_TRIGGER_SUSPEND:
0870     case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
0871         dev_dbg(cpu_dai->dev, "stop I2S %s\n",
0872             playback_flg ? "playback" : "capture");
0873 
0874         if (playback_flg)
0875             regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG,
0876                        I2S_IER_UDRIE,
0877                        (unsigned int)~I2S_IER_UDRIE);
0878         else
0879             regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG,
0880                        I2S_IER_OVRIE,
0881                        (unsigned int)~I2S_IER_OVRIE);
0882 
0883         spin_lock(&i2s->lock_fd);
0884         i2s->refcount--;
0885         if (i2s->refcount) {
0886             spin_unlock(&i2s->lock_fd);
0887             break;
0888         }
0889 
0890         ret = regmap_update_bits(i2s->regmap, STM32_I2S_CR1_REG,
0891                      I2S_CR1_SPE, 0);
0892         if (ret < 0) {
0893             dev_err(cpu_dai->dev, "Error %d disabling I2S\n", ret);
0894             spin_unlock(&i2s->lock_fd);
0895             return ret;
0896         }
0897         spin_unlock(&i2s->lock_fd);
0898 
0899         cfg1_mask = I2S_CFG1_RXDMAEN | I2S_CFG1_TXDMAEN;
0900         regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,
0901                    cfg1_mask, 0);
0902         break;
0903     default:
0904         return -EINVAL;
0905     }
0906 
0907     return 0;
0908 }
0909 
0910 static void stm32_i2s_shutdown(struct snd_pcm_substream *substream,
0911                    struct snd_soc_dai *cpu_dai)
0912 {
0913     struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
0914     unsigned long flags;
0915 
0916     clk_disable_unprepare(i2s->i2sclk);
0917 
0918     spin_lock_irqsave(&i2s->irq_lock, flags);
0919     i2s->substream = NULL;
0920     spin_unlock_irqrestore(&i2s->irq_lock, flags);
0921 }
0922 
0923 static int stm32_i2s_dai_probe(struct snd_soc_dai *cpu_dai)
0924 {
0925     struct stm32_i2s_data *i2s = dev_get_drvdata(cpu_dai->dev);
0926     struct snd_dmaengine_dai_dma_data *dma_data_tx = &i2s->dma_data_tx;
0927     struct snd_dmaengine_dai_dma_data *dma_data_rx = &i2s->dma_data_rx;
0928 
0929     /* Buswidth will be set by framework */
0930     dma_data_tx->addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
0931     dma_data_tx->addr = (dma_addr_t)(i2s->phys_addr) + STM32_I2S_TXDR_REG;
0932     dma_data_tx->maxburst = 1;
0933     dma_data_rx->addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
0934     dma_data_rx->addr = (dma_addr_t)(i2s->phys_addr) + STM32_I2S_RXDR_REG;
0935     dma_data_rx->maxburst = 1;
0936 
0937     snd_soc_dai_init_dma_data(cpu_dai, dma_data_tx, dma_data_rx);
0938 
0939     return 0;
0940 }
0941 
0942 static const struct regmap_config stm32_h7_i2s_regmap_conf = {
0943     .reg_bits = 32,
0944     .reg_stride = 4,
0945     .val_bits = 32,
0946     .max_register = STM32_I2S_SIDR_REG,
0947     .readable_reg = stm32_i2s_readable_reg,
0948     .volatile_reg = stm32_i2s_volatile_reg,
0949     .writeable_reg = stm32_i2s_writeable_reg,
0950     .num_reg_defaults_raw = STM32_I2S_SIDR_REG / sizeof(u32) + 1,
0951     .fast_io = true,
0952     .cache_type = REGCACHE_FLAT,
0953 };
0954 
0955 static const struct snd_soc_dai_ops stm32_i2s_pcm_dai_ops = {
0956     .set_sysclk = stm32_i2s_set_sysclk,
0957     .set_fmt    = stm32_i2s_set_dai_fmt,
0958     .startup    = stm32_i2s_startup,
0959     .hw_params  = stm32_i2s_hw_params,
0960     .trigger    = stm32_i2s_trigger,
0961     .shutdown   = stm32_i2s_shutdown,
0962 };
0963 
0964 static const struct snd_pcm_hardware stm32_i2s_pcm_hw = {
0965     .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP,
0966     .buffer_bytes_max = 8 * PAGE_SIZE,
0967     .period_bytes_min = 1024,
0968     .period_bytes_max = 4 * PAGE_SIZE,
0969     .periods_min = 2,
0970     .periods_max = 8,
0971 };
0972 
0973 static const struct snd_dmaengine_pcm_config stm32_i2s_pcm_config = {
0974     .pcm_hardware   = &stm32_i2s_pcm_hw,
0975     .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
0976     .prealloc_buffer_size = PAGE_SIZE * 8,
0977 };
0978 
0979 static const struct snd_soc_component_driver stm32_i2s_component = {
0980     .name = "stm32-i2s",
0981     .legacy_dai_naming = 1,
0982 };
0983 
0984 static void stm32_i2s_dai_init(struct snd_soc_pcm_stream *stream,
0985                    char *stream_name)
0986 {
0987     stream->stream_name = stream_name;
0988     stream->channels_min = 1;
0989     stream->channels_max = 2;
0990     stream->rates = SNDRV_PCM_RATE_8000_192000;
0991     stream->formats = SNDRV_PCM_FMTBIT_S16_LE |
0992                    SNDRV_PCM_FMTBIT_S32_LE;
0993 }
0994 
0995 static int stm32_i2s_dais_init(struct platform_device *pdev,
0996                    struct stm32_i2s_data *i2s)
0997 {
0998     struct snd_soc_dai_driver *dai_ptr;
0999 
1000     dai_ptr = devm_kzalloc(&pdev->dev, sizeof(struct snd_soc_dai_driver),
1001                    GFP_KERNEL);
1002     if (!dai_ptr)
1003         return -ENOMEM;
1004 
1005     dai_ptr->probe = stm32_i2s_dai_probe;
1006     dai_ptr->ops = &stm32_i2s_pcm_dai_ops;
1007     dai_ptr->id = 1;
1008     stm32_i2s_dai_init(&dai_ptr->playback, "playback");
1009     stm32_i2s_dai_init(&dai_ptr->capture, "capture");
1010     i2s->dai_drv = dai_ptr;
1011 
1012     return 0;
1013 }
1014 
1015 static const struct of_device_id stm32_i2s_ids[] = {
1016     {
1017         .compatible = "st,stm32h7-i2s",
1018         .data = &stm32_h7_i2s_regmap_conf
1019     },
1020     {},
1021 };
1022 
1023 static int stm32_i2s_parse_dt(struct platform_device *pdev,
1024                   struct stm32_i2s_data *i2s)
1025 {
1026     struct device_node *np = pdev->dev.of_node;
1027     const struct of_device_id *of_id;
1028     struct reset_control *rst;
1029     struct resource *res;
1030     int irq, ret;
1031 
1032     if (!np)
1033         return -ENODEV;
1034 
1035     of_id = of_match_device(stm32_i2s_ids, &pdev->dev);
1036     if (of_id)
1037         i2s->regmap_conf = (const struct regmap_config *)of_id->data;
1038     else
1039         return -EINVAL;
1040 
1041     i2s->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1042     if (IS_ERR(i2s->base))
1043         return PTR_ERR(i2s->base);
1044 
1045     i2s->phys_addr = res->start;
1046 
1047     /* Get clocks */
1048     i2s->pclk = devm_clk_get(&pdev->dev, "pclk");
1049     if (IS_ERR(i2s->pclk))
1050         return dev_err_probe(&pdev->dev, PTR_ERR(i2s->pclk),
1051                      "Could not get pclk\n");
1052 
1053     i2s->i2sclk = devm_clk_get(&pdev->dev, "i2sclk");
1054     if (IS_ERR(i2s->i2sclk))
1055         return dev_err_probe(&pdev->dev, PTR_ERR(i2s->i2sclk),
1056                      "Could not get i2sclk\n");
1057 
1058     i2s->x8kclk = devm_clk_get(&pdev->dev, "x8k");
1059     if (IS_ERR(i2s->x8kclk))
1060         return dev_err_probe(&pdev->dev, PTR_ERR(i2s->x8kclk),
1061                      "Could not get x8k parent clock\n");
1062 
1063     i2s->x11kclk = devm_clk_get(&pdev->dev, "x11k");
1064     if (IS_ERR(i2s->x11kclk))
1065         return dev_err_probe(&pdev->dev, PTR_ERR(i2s->x11kclk),
1066                      "Could not get x11k parent clock\n");
1067 
1068     /* Register mclk provider if requested */
1069     if (of_find_property(np, "#clock-cells", NULL)) {
1070         ret = stm32_i2s_add_mclk_provider(i2s);
1071         if (ret < 0)
1072             return ret;
1073     }
1074 
1075     /* Get irqs */
1076     irq = platform_get_irq(pdev, 0);
1077     if (irq < 0)
1078         return irq;
1079 
1080     ret = devm_request_irq(&pdev->dev, irq, stm32_i2s_isr, IRQF_ONESHOT,
1081                    dev_name(&pdev->dev), i2s);
1082     if (ret) {
1083         dev_err(&pdev->dev, "irq request returned %d\n", ret);
1084         return ret;
1085     }
1086 
1087     /* Reset */
1088     rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
1089     if (IS_ERR(rst))
1090         return dev_err_probe(&pdev->dev, PTR_ERR(rst),
1091                      "Reset controller error\n");
1092 
1093     reset_control_assert(rst);
1094     udelay(2);
1095     reset_control_deassert(rst);
1096 
1097     return 0;
1098 }
1099 
1100 static int stm32_i2s_remove(struct platform_device *pdev)
1101 {
1102     snd_dmaengine_pcm_unregister(&pdev->dev);
1103     snd_soc_unregister_component(&pdev->dev);
1104     pm_runtime_disable(&pdev->dev);
1105 
1106     return 0;
1107 }
1108 
1109 static int stm32_i2s_probe(struct platform_device *pdev)
1110 {
1111     struct stm32_i2s_data *i2s;
1112     u32 val;
1113     int ret;
1114 
1115     i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
1116     if (!i2s)
1117         return -ENOMEM;
1118 
1119     i2s->pdev = pdev;
1120     i2s->ms_flg = I2S_MS_NOT_SET;
1121     spin_lock_init(&i2s->lock_fd);
1122     spin_lock_init(&i2s->irq_lock);
1123     platform_set_drvdata(pdev, i2s);
1124 
1125     ret = stm32_i2s_parse_dt(pdev, i2s);
1126     if (ret)
1127         return ret;
1128 
1129     ret = stm32_i2s_dais_init(pdev, i2s);
1130     if (ret)
1131         return ret;
1132 
1133     i2s->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "pclk",
1134                         i2s->base, i2s->regmap_conf);
1135     if (IS_ERR(i2s->regmap))
1136         return dev_err_probe(&pdev->dev, PTR_ERR(i2s->regmap),
1137                      "Regmap init error\n");
1138 
1139     pm_runtime_enable(&pdev->dev);
1140 
1141     ret = snd_dmaengine_pcm_register(&pdev->dev, &stm32_i2s_pcm_config, 0);
1142     if (ret)
1143         return dev_err_probe(&pdev->dev, ret, "PCM DMA register error\n");
1144 
1145     ret = snd_soc_register_component(&pdev->dev, &stm32_i2s_component,
1146                      i2s->dai_drv, 1);
1147     if (ret) {
1148         snd_dmaengine_pcm_unregister(&pdev->dev);
1149         return ret;
1150     }
1151 
1152     /* Set SPI/I2S in i2s mode */
1153     ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
1154                  I2S_CGFR_I2SMOD, I2S_CGFR_I2SMOD);
1155     if (ret)
1156         goto error;
1157 
1158     ret = regmap_read(i2s->regmap, STM32_I2S_IPIDR_REG, &val);
1159     if (ret)
1160         goto error;
1161 
1162     if (val == I2S_IPIDR_NUMBER) {
1163         ret = regmap_read(i2s->regmap, STM32_I2S_HWCFGR_REG, &val);
1164         if (ret)
1165             goto error;
1166 
1167         if (!FIELD_GET(I2S_HWCFGR_I2S_SUPPORT_MASK, val)) {
1168             dev_err(&pdev->dev,
1169                 "Device does not support i2s mode\n");
1170             ret = -EPERM;
1171             goto error;
1172         }
1173 
1174         ret = regmap_read(i2s->regmap, STM32_I2S_VERR_REG, &val);
1175         if (ret)
1176             goto error;
1177 
1178         dev_dbg(&pdev->dev, "I2S version: %lu.%lu registered\n",
1179             FIELD_GET(I2S_VERR_MAJ_MASK, val),
1180             FIELD_GET(I2S_VERR_MIN_MASK, val));
1181     }
1182 
1183     return ret;
1184 
1185 error:
1186     stm32_i2s_remove(pdev);
1187 
1188     return ret;
1189 }
1190 
1191 MODULE_DEVICE_TABLE(of, stm32_i2s_ids);
1192 
1193 #ifdef CONFIG_PM_SLEEP
1194 static int stm32_i2s_suspend(struct device *dev)
1195 {
1196     struct stm32_i2s_data *i2s = dev_get_drvdata(dev);
1197 
1198     regcache_cache_only(i2s->regmap, true);
1199     regcache_mark_dirty(i2s->regmap);
1200 
1201     return 0;
1202 }
1203 
1204 static int stm32_i2s_resume(struct device *dev)
1205 {
1206     struct stm32_i2s_data *i2s = dev_get_drvdata(dev);
1207 
1208     regcache_cache_only(i2s->regmap, false);
1209     return regcache_sync(i2s->regmap);
1210 }
1211 #endif /* CONFIG_PM_SLEEP */
1212 
1213 static const struct dev_pm_ops stm32_i2s_pm_ops = {
1214     SET_SYSTEM_SLEEP_PM_OPS(stm32_i2s_suspend, stm32_i2s_resume)
1215 };
1216 
1217 static struct platform_driver stm32_i2s_driver = {
1218     .driver = {
1219         .name = "st,stm32-i2s",
1220         .of_match_table = stm32_i2s_ids,
1221         .pm = &stm32_i2s_pm_ops,
1222     },
1223     .probe = stm32_i2s_probe,
1224     .remove = stm32_i2s_remove,
1225 };
1226 
1227 module_platform_driver(stm32_i2s_driver);
1228 
1229 MODULE_DESCRIPTION("STM32 Soc i2s Interface");
1230 MODULE_AUTHOR("Olivier Moysan, <olivier.moysan@st.com>");
1231 MODULE_ALIAS("platform:stm32-i2s");
1232 MODULE_LICENSE("GPL v2");
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