sof/intel/tgl.c

0001 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
0002 //
0003 // Copyright(c) 2020 Intel Corporation. All rights reserved.
0004 //
0005 // Authors: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
0006 //
0007
0008 /*
0009  * Hardware interface for audio DSP on Tigerlake.
0010  */
0011
0012 #include <sound/sof/ext_manifest4.h>
0013 #include "../ipc4-priv.h"
0014 #include "../ops.h"
0015 #include "hda.h"
0016 #include "hda-ipc.h"
0017 #include "../sof-audio.h"
0018
0019 static const struct snd_sof_debugfs_map tgl_dsp_debugfs[] = {
0020     {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS},
0021     {"pp", HDA_DSP_PP_BAR,  0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS},
0022     {"dsp", HDA_DSP_BAR,  0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
0023 };
0024
0025 static int tgl_dsp_core_get(struct snd_sof_dev *sdev, int core)
0026 {
0027     const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm;
0028
0029     /* power up primary core if not already powered up and return */
0030     if (core == SOF_DSP_PRIMARY_CORE)
0031         return hda_dsp_enable_core(sdev, BIT(core));
0032
0033     if (pm_ops->set_core_state)
0034         return pm_ops->set_core_state(sdev, core, true);
0035
0036     return 0;
0037 }
0038
0039 static int tgl_dsp_core_put(struct snd_sof_dev *sdev, int core)
0040 {
0041     const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm;
0042
0043     /* power down primary core and return */
0044     if (core == SOF_DSP_PRIMARY_CORE)
0045         return hda_dsp_core_reset_power_down(sdev, BIT(core));
0046
0047     if (pm_ops->set_core_state)
0048         return pm_ops->set_core_state(sdev, core, false);
0049
0050     return 0;
0051 }
0052
0053 /* Tigerlake ops */
0054 struct snd_sof_dsp_ops sof_tgl_ops;
0055 EXPORT_SYMBOL_NS(sof_tgl_ops, SND_SOC_SOF_INTEL_HDA_COMMON);
0056
0057 int sof_tgl_ops_init(struct snd_sof_dev *sdev)
0058 {
0059     /* common defaults */
0060     memcpy(&sof_tgl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops));
0061
0062     /* probe/remove/shutdown */
0063     sof_tgl_ops.shutdown    = hda_dsp_shutdown;
0064
0065     if (sdev->pdata->ipc_type == SOF_IPC) {
0066         /* doorbell */
0067         sof_tgl_ops.irq_thread  = cnl_ipc_irq_thread;
0068
0069         /* ipc */
0070         sof_tgl_ops.send_msg    = cnl_ipc_send_msg;
0071     }
0072
0073     if (sdev->pdata->ipc_type == SOF_INTEL_IPC4) {
0074         struct sof_ipc4_fw_data *ipc4_data;
0075
0076         sdev->private = devm_kzalloc(sdev->dev, sizeof(*ipc4_data), GFP_KERNEL);
0077         if (!sdev->private)
0078             return -ENOMEM;
0079
0080         ipc4_data = sdev->private;
0081         ipc4_data->manifest_fw_hdr_offset = SOF_MAN4_FW_HDR_OFFSET;
0082
0083         /* doorbell */
0084         sof_tgl_ops.irq_thread  = cnl_ipc4_irq_thread;
0085
0086         /* ipc */
0087         sof_tgl_ops.send_msg    = cnl_ipc4_send_msg;
0088     }
0089
0090     /* set DAI driver ops */
0091     hda_set_dai_drv_ops(sdev, &sof_tgl_ops);
0092
0093     /* debug */
0094     sof_tgl_ops.debug_map   = tgl_dsp_debugfs;
0095     sof_tgl_ops.debug_map_count = ARRAY_SIZE(tgl_dsp_debugfs);
0096     sof_tgl_ops.ipc_dump    = cnl_ipc_dump;
0097
0098     /* pre/post fw run */
0099     sof_tgl_ops.post_fw_run = hda_dsp_post_fw_run;
0100
0101     /* firmware run */
0102     sof_tgl_ops.run = hda_dsp_cl_boot_firmware_iccmax;
0103
0104     /* dsp core get/put */
0105     sof_tgl_ops.core_get = tgl_dsp_core_get;
0106     sof_tgl_ops.core_put = tgl_dsp_core_put;
0107
0108     return 0;
0109 };
0110 EXPORT_SYMBOL_NS(sof_tgl_ops_init, SND_SOC_SOF_INTEL_HDA_COMMON);
0111
0112 const struct sof_intel_dsp_desc tgl_chip_info = {
0113     /* Tigerlake , Alderlake */
0114     .cores_num = 4,
0115     .init_core_mask = 1,
0116     .host_managed_cores_mask = BIT(0),
0117     .ipc_req = CNL_DSP_REG_HIPCIDR,
0118     .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
0119     .ipc_ack = CNL_DSP_REG_HIPCIDA,
0120     .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
0121     .ipc_ctl = CNL_DSP_REG_HIPCCTL,
0122     .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
0123     .rom_init_timeout   = 300,
0124     .ssp_count = ICL_SSP_COUNT,
0125     .ssp_base_offset = CNL_SSP_BASE_OFFSET,
0126     .sdw_shim_base = SDW_SHIM_BASE,
0127     .sdw_alh_base = SDW_ALH_BASE,
0128     .check_sdw_irq  = hda_common_check_sdw_irq,
0129     .check_ipc_irq  = hda_dsp_check_ipc_irq,
0130     .cl_init = cl_dsp_init,
0131     .hw_ip_version = SOF_INTEL_CAVS_2_5,
0132 };
0133 EXPORT_SYMBOL_NS(tgl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
0134
0135 const struct sof_intel_dsp_desc tglh_chip_info = {
0136     /* Tigerlake-H */
0137     .cores_num = 2,
0138     .init_core_mask = 1,
0139     .host_managed_cores_mask = BIT(0),
0140     .ipc_req = CNL_DSP_REG_HIPCIDR,
0141     .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
0142     .ipc_ack = CNL_DSP_REG_HIPCIDA,
0143     .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
0144     .ipc_ctl = CNL_DSP_REG_HIPCCTL,
0145     .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
0146     .rom_init_timeout   = 300,
0147     .ssp_count = ICL_SSP_COUNT,
0148     .ssp_base_offset = CNL_SSP_BASE_OFFSET,
0149     .sdw_shim_base = SDW_SHIM_BASE,
0150     .sdw_alh_base = SDW_ALH_BASE,
0151     .check_sdw_irq  = hda_common_check_sdw_irq,
0152     .check_ipc_irq  = hda_dsp_check_ipc_irq,
0153     .cl_init = cl_dsp_init,
0154     .hw_ip_version = SOF_INTEL_CAVS_2_5,
0155 };
0156 EXPORT_SYMBOL_NS(tglh_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
0157
0158 const struct sof_intel_dsp_desc ehl_chip_info = {
0159     /* Elkhartlake */
0160     .cores_num = 4,
0161     .init_core_mask = 1,
0162     .host_managed_cores_mask = BIT(0),
0163     .ipc_req = CNL_DSP_REG_HIPCIDR,
0164     .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
0165     .ipc_ack = CNL_DSP_REG_HIPCIDA,
0166     .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
0167     .ipc_ctl = CNL_DSP_REG_HIPCCTL,
0168     .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
0169     .rom_init_timeout   = 300,
0170     .ssp_count = ICL_SSP_COUNT,
0171     .ssp_base_offset = CNL_SSP_BASE_OFFSET,
0172     .sdw_shim_base = SDW_SHIM_BASE,
0173     .sdw_alh_base = SDW_ALH_BASE,
0174     .check_sdw_irq  = hda_common_check_sdw_irq,
0175     .check_ipc_irq  = hda_dsp_check_ipc_irq,
0176     .cl_init = cl_dsp_init,
0177     .hw_ip_version = SOF_INTEL_CAVS_2_5,
0178 };
0179 EXPORT_SYMBOL_NS(ehl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
0180
0181 const struct sof_intel_dsp_desc adls_chip_info = {
0182     /* Alderlake-S */
0183     .cores_num = 2,
0184     .init_core_mask = BIT(0),
0185     .host_managed_cores_mask = BIT(0),
0186     .ipc_req = CNL_DSP_REG_HIPCIDR,
0187     .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
0188     .ipc_ack = CNL_DSP_REG_HIPCIDA,
0189     .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
0190     .ipc_ctl = CNL_DSP_REG_HIPCCTL,
0191     .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
0192     .rom_init_timeout   = 300,
0193     .ssp_count = ICL_SSP_COUNT,
0194     .ssp_base_offset = CNL_SSP_BASE_OFFSET,
0195     .sdw_shim_base = SDW_SHIM_BASE,
0196     .sdw_alh_base = SDW_ALH_BASE,
0197     .check_sdw_irq  = hda_common_check_sdw_irq,
0198     .check_ipc_irq  = hda_dsp_check_ipc_irq,
0199     .cl_init = cl_dsp_init,
0200     .hw_ip_version = SOF_INTEL_CAVS_2_5,
0201 };
0202 EXPORT_SYMBOL_NS(adls_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);