sof/intel/shim.h

0001 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
0002 /*
0003  * This file is provided under a dual BSD/GPLv2 license.  When using or
0004  * redistributing this file, you may do so under either license.
0005  *
0006  * Copyright(c) 2017 Intel Corporation. All rights reserved.
0007  *
0008  * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
0009  */
0010
0011 #ifndef __SOF_INTEL_SHIM_H
0012 #define __SOF_INTEL_SHIM_H
0013
0014 enum sof_intel_hw_ip_version {
0015     SOF_INTEL_TANGIER,
0016     SOF_INTEL_BAYTRAIL,
0017     SOF_INTEL_BROADWELL,
0018     SOF_INTEL_CAVS_1_5, /* SkyLake, KabyLake, AmberLake */
0019     SOF_INTEL_CAVS_1_5_PLUS,/* ApolloLake, GeminiLake */
0020     SOF_INTEL_CAVS_1_8, /* CannonLake, CometLake, CoffeeLake */
0021     SOF_INTEL_CAVS_2_0, /* IceLake, JasperLake */
0022     SOF_INTEL_CAVS_2_5, /* TigerLake, AlderLake */
0023     SOF_INTEL_ACE_1_0,  /* MeteorLake */
0024 };
0025
0026 /*
0027  * SHIM registers for BYT, BSW, CHT, BDW
0028  */
0029
0030 #define SHIM_CSR        (SHIM_OFFSET + 0x00)
0031 #define SHIM_PISR       (SHIM_OFFSET + 0x08)
0032 #define SHIM_PIMR       (SHIM_OFFSET + 0x10)
0033 #define SHIM_ISRX       (SHIM_OFFSET + 0x18)
0034 #define SHIM_ISRD       (SHIM_OFFSET + 0x20)
0035 #define SHIM_IMRX       (SHIM_OFFSET + 0x28)
0036 #define SHIM_IMRD       (SHIM_OFFSET + 0x30)
0037 #define SHIM_IPCX       (SHIM_OFFSET + 0x38)
0038 #define SHIM_IPCD       (SHIM_OFFSET + 0x40)
0039 #define SHIM_ISRSC      (SHIM_OFFSET + 0x48)
0040 #define SHIM_ISRLPESC       (SHIM_OFFSET + 0x50)
0041 #define SHIM_IMRSC      (SHIM_OFFSET + 0x58)
0042 #define SHIM_IMRLPESC       (SHIM_OFFSET + 0x60)
0043 #define SHIM_IPCSC      (SHIM_OFFSET + 0x68)
0044 #define SHIM_IPCLPESC       (SHIM_OFFSET + 0x70)
0045 #define SHIM_CLKCTL     (SHIM_OFFSET + 0x78)
0046 #define SHIM_CSR2       (SHIM_OFFSET + 0x80)
0047 #define SHIM_LTRC       (SHIM_OFFSET + 0xE0)
0048 #define SHIM_HMDC       (SHIM_OFFSET + 0xE8)
0049
0050 #define SHIM_PWMCTRL        0x1000
0051
0052 /*
0053  * SST SHIM register bits for BYT, BSW, CHT, BDW
0054  * Register bit naming and functionaility can differ between devices.
0055  */
0056
0057 /* CSR / CS */
0058 #define SHIM_CSR_RST        BIT(1)
0059 #define SHIM_CSR_SBCS0      BIT(2)
0060 #define SHIM_CSR_SBCS1      BIT(3)
0061 #define SHIM_CSR_DCS(x)     ((x) << 4)
0062 #define SHIM_CSR_DCS_MASK   (0x7 << 4)
0063 #define SHIM_CSR_STALL      BIT(10)
0064 #define SHIM_CSR_S0IOCS     BIT(21)
0065 #define SHIM_CSR_S1IOCS     BIT(23)
0066 #define SHIM_CSR_LPCS       BIT(31)
0067 #define SHIM_CSR_24MHZ_LPCS \
0068     (SHIM_CSR_SBCS0 | SHIM_CSR_SBCS1 | SHIM_CSR_LPCS)
0069 #define SHIM_CSR_24MHZ_NO_LPCS  (SHIM_CSR_SBCS0 | SHIM_CSR_SBCS1)
0070 #define SHIM_BYT_CSR_RST    BIT(0)
0071 #define SHIM_BYT_CSR_VECTOR_SEL BIT(1)
0072 #define SHIM_BYT_CSR_STALL  BIT(2)
0073 #define SHIM_BYT_CSR_PWAITMODE  BIT(3)
0074
0075 /*  ISRX / ISC */
0076 #define SHIM_ISRX_BUSY      BIT(1)
0077 #define SHIM_ISRX_DONE      BIT(0)
0078 #define SHIM_BYT_ISRX_REQUEST   BIT(1)
0079
0080 /*  ISRD / ISD */
0081 #define SHIM_ISRD_BUSY      BIT(1)
0082 #define SHIM_ISRD_DONE      BIT(0)
0083
0084 /* IMRX / IMC */
0085 #define SHIM_IMRX_BUSY      BIT(1)
0086 #define SHIM_IMRX_DONE      BIT(0)
0087 #define SHIM_BYT_IMRX_REQUEST   BIT(1)
0088
0089 /* IMRD / IMD */
0090 #define SHIM_IMRD_DONE      BIT(0)
0091 #define SHIM_IMRD_BUSY      BIT(1)
0092 #define SHIM_IMRD_SSP0      BIT(16)
0093 #define SHIM_IMRD_DMAC0     BIT(21)
0094 #define SHIM_IMRD_DMAC1     BIT(22)
0095 #define SHIM_IMRD_DMAC      (SHIM_IMRD_DMAC0 | SHIM_IMRD_DMAC1)
0096
0097 /*  IPCX / IPCC */
0098 #define SHIM_IPCX_DONE      BIT(30)
0099 #define SHIM_IPCX_BUSY      BIT(31)
0100 #define SHIM_BYT_IPCX_DONE  BIT_ULL(62)
0101 #define SHIM_BYT_IPCX_BUSY  BIT_ULL(63)
0102
0103 /*  IPCD */
0104 #define SHIM_IPCD_DONE      BIT(30)
0105 #define SHIM_IPCD_BUSY      BIT(31)
0106 #define SHIM_BYT_IPCD_DONE  BIT_ULL(62)
0107 #define SHIM_BYT_IPCD_BUSY  BIT_ULL(63)
0108
0109 /* CLKCTL */
0110 #define SHIM_CLKCTL_SMOS(x) ((x) << 24)
0111 #define SHIM_CLKCTL_MASK    (3 << 24)
0112 #define SHIM_CLKCTL_DCPLCG  BIT(18)
0113 #define SHIM_CLKCTL_SCOE1   BIT(17)
0114 #define SHIM_CLKCTL_SCOE0   BIT(16)
0115
0116 /* CSR2 / CS2 */
0117 #define SHIM_CSR2_SDFD_SSP0 BIT(1)
0118 #define SHIM_CSR2_SDFD_SSP1 BIT(2)
0119
0120 /* LTRC */
0121 #define SHIM_LTRC_VAL(x)    ((x) << 0)
0122
0123 /* HMDC */
0124 #define SHIM_HMDC_HDDA0(x)  ((x) << 0)
0125 #define SHIM_HMDC_HDDA1(x)  ((x) << 7)
0126 #define SHIM_HMDC_HDDA_E0_CH0   1
0127 #define SHIM_HMDC_HDDA_E0_CH1   2
0128 #define SHIM_HMDC_HDDA_E0_CH2   4
0129 #define SHIM_HMDC_HDDA_E0_CH3   8
0130 #define SHIM_HMDC_HDDA_E1_CH0   SHIM_HMDC_HDDA1(SHIM_HMDC_HDDA_E0_CH0)
0131 #define SHIM_HMDC_HDDA_E1_CH1   SHIM_HMDC_HDDA1(SHIM_HMDC_HDDA_E0_CH1)
0132 #define SHIM_HMDC_HDDA_E1_CH2   SHIM_HMDC_HDDA1(SHIM_HMDC_HDDA_E0_CH2)
0133 #define SHIM_HMDC_HDDA_E1_CH3   SHIM_HMDC_HDDA1(SHIM_HMDC_HDDA_E0_CH3)
0134 #define SHIM_HMDC_HDDA_E0_ALLCH \
0135     (SHIM_HMDC_HDDA_E0_CH0 | SHIM_HMDC_HDDA_E0_CH1 | \
0136      SHIM_HMDC_HDDA_E0_CH2 | SHIM_HMDC_HDDA_E0_CH3)
0137 #define SHIM_HMDC_HDDA_E1_ALLCH \
0138     (SHIM_HMDC_HDDA_E1_CH0 | SHIM_HMDC_HDDA_E1_CH1 | \
0139      SHIM_HMDC_HDDA_E1_CH2 | SHIM_HMDC_HDDA_E1_CH3)
0140
0141 /* Audio DSP PCI registers */
0142 #define PCI_VDRTCTL0        0xa0
0143 #define PCI_VDRTCTL1        0xa4
0144 #define PCI_VDRTCTL2        0xa8
0145 #define PCI_VDRTCTL3        0xaC
0146
0147 /* VDRTCTL0 */
0148 #define PCI_VDRTCL0_D3PGD       BIT(0)
0149 #define PCI_VDRTCL0_D3SRAMPGD       BIT(1)
0150 #define PCI_VDRTCL0_DSRAMPGE_SHIFT  12
0151 #define PCI_VDRTCL0_DSRAMPGE_MASK   GENMASK(PCI_VDRTCL0_DSRAMPGE_SHIFT + 19,\
0152                         PCI_VDRTCL0_DSRAMPGE_SHIFT)
0153 #define PCI_VDRTCL0_ISRAMPGE_SHIFT  2
0154 #define PCI_VDRTCL0_ISRAMPGE_MASK   GENMASK(PCI_VDRTCL0_ISRAMPGE_SHIFT + 9,\
0155                         PCI_VDRTCL0_ISRAMPGE_SHIFT)
0156
0157 /* VDRTCTL2 */
0158 #define PCI_VDRTCL2_DCLCGE      BIT(1)
0159 #define PCI_VDRTCL2_DTCGE       BIT(10)
0160 #define PCI_VDRTCL2_APLLSE_MASK     BIT(31)
0161
0162 /* PMCS */
0163 #define PCI_PMCS        0x84
0164 #define PCI_PMCS_PS_MASK    0x3
0165
0166 /* Intel quirks */
0167 #define SOF_INTEL_PROCEN_FMT_QUIRK BIT(0)
0168
0169 /* DSP hardware descriptor */
0170 struct sof_intel_dsp_desc {
0171     int cores_num;
0172     int host_managed_cores_mask;
0173     int init_core_mask; /* cores available after fw boot */
0174     int ipc_req;
0175     int ipc_req_mask;
0176     int ipc_ack;
0177     int ipc_ack_mask;
0178     int ipc_ctl;
0179     int rom_status_reg;
0180     int rom_init_timeout;
0181     int ssp_count;          /* ssp count of the platform */
0182     int ssp_base_offset;        /* base address of the SSPs */
0183     u32 sdw_shim_base;
0184     u32 sdw_alh_base;
0185     u32 quirks;
0186     enum sof_intel_hw_ip_version hw_ip_version;
0187     bool (*check_sdw_irq)(struct snd_sof_dev *sdev);
0188     bool (*check_ipc_irq)(struct snd_sof_dev *sdev);
0189     int (*cl_init)(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot);
0190 };
0191
0192 extern struct snd_sof_dsp_ops sof_tng_ops;
0193
0194 extern const struct sof_intel_dsp_desc tng_chip_info;
0195
0196 struct sof_intel_stream {
0197     size_t posn_offset;
0198 };
0199
0200 static inline const struct sof_intel_dsp_desc *get_chip_info(struct snd_sof_pdata *pdata)
0201 {
0202     const struct sof_dev_desc *desc = pdata->desc;
0203
0204     return desc->chip_info;
0205 }
0206
0207 #endif