sof/intel/pci-tng.c

0001 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
0002 //
0003 // This file is provided under a dual BSD/GPLv2 license.  When using or
0004 // redistributing this file, you may do so under either license.
0005 //
0006 // Copyright(c) 2018-2021 Intel Corporation. All rights reserved.
0007 //
0008 // Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
0009 //
0010
0011 #include <linux/module.h>
0012 #include <linux/pci.h>
0013 #include <sound/soc-acpi.h>
0014 #include <sound/soc-acpi-intel-match.h>
0015 #include <sound/sof.h>
0016 #include "../ops.h"
0017 #include "atom.h"
0018 #include "../sof-pci-dev.h"
0019 #include "../sof-audio.h"
0020
0021 /* platform specific devices */
0022 #include "shim.h"
0023
0024 static struct snd_soc_acpi_mach sof_tng_machines[] = {
0025     {
0026         .id = "INT343A",
0027         .drv_name = "edison",
0028         .sof_tplg_filename = "sof-byt.tplg",
0029     },
0030     {}
0031 };
0032
0033 static const struct snd_sof_debugfs_map tng_debugfs[] = {
0034     {"dmac0", DSP_BAR, DMAC0_OFFSET, DMAC_SIZE,
0035      SOF_DEBUGFS_ACCESS_ALWAYS},
0036     {"dmac1", DSP_BAR, DMAC1_OFFSET, DMAC_SIZE,
0037      SOF_DEBUGFS_ACCESS_ALWAYS},
0038     {"ssp0", DSP_BAR, SSP0_OFFSET, SSP_SIZE,
0039      SOF_DEBUGFS_ACCESS_ALWAYS},
0040     {"ssp1", DSP_BAR, SSP1_OFFSET, SSP_SIZE,
0041      SOF_DEBUGFS_ACCESS_ALWAYS},
0042     {"ssp2", DSP_BAR, SSP2_OFFSET, SSP_SIZE,
0043      SOF_DEBUGFS_ACCESS_ALWAYS},
0044     {"iram", DSP_BAR, IRAM_OFFSET, IRAM_SIZE,
0045      SOF_DEBUGFS_ACCESS_D0_ONLY},
0046     {"dram", DSP_BAR, DRAM_OFFSET, DRAM_SIZE,
0047      SOF_DEBUGFS_ACCESS_D0_ONLY},
0048     {"shim", DSP_BAR, SHIM_OFFSET, SHIM_SIZE_BYT,
0049      SOF_DEBUGFS_ACCESS_ALWAYS},
0050 };
0051
0052 static int tangier_pci_probe(struct snd_sof_dev *sdev)
0053 {
0054     struct snd_sof_pdata *pdata = sdev->pdata;
0055     const struct sof_dev_desc *desc = pdata->desc;
0056     struct pci_dev *pci = to_pci_dev(sdev->dev);
0057     const struct sof_intel_dsp_desc *chip;
0058     u32 base, size;
0059     int ret;
0060
0061     chip = get_chip_info(sdev->pdata);
0062     if (!chip) {
0063         dev_err(sdev->dev, "error: no such device supported\n");
0064         return -EIO;
0065     }
0066
0067     sdev->num_cores = chip->cores_num;
0068
0069     /* DSP DMA can only access low 31 bits of host memory */
0070     ret = dma_coerce_mask_and_coherent(&pci->dev, DMA_BIT_MASK(31));
0071     if (ret < 0) {
0072         dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret);
0073         return ret;
0074     }
0075
0076     /* LPE base */
0077     base = pci_resource_start(pci, desc->resindex_lpe_base) - IRAM_OFFSET;
0078     size = pci_resource_len(pci, desc->resindex_lpe_base);
0079     if (size < PCI_BAR_SIZE) {
0080         dev_err(sdev->dev, "error: I/O region is too small.\n");
0081         return -ENODEV;
0082     }
0083
0084     dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size);
0085     sdev->bar[DSP_BAR] = devm_ioremap(sdev->dev, base, size);
0086     if (!sdev->bar[DSP_BAR]) {
0087         dev_err(sdev->dev, "error: failed to ioremap LPE base 0x%x size 0x%x\n",
0088             base, size);
0089         return -ENODEV;
0090     }
0091     dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[DSP_BAR]);
0092
0093     /* IMR base - optional */
0094     if (desc->resindex_imr_base == -1)
0095         goto irq;
0096
0097     base = pci_resource_start(pci, desc->resindex_imr_base);
0098     size = pci_resource_len(pci, desc->resindex_imr_base);
0099
0100     /* some BIOSes don't map IMR */
0101     if (base == 0x55aa55aa || base == 0x0) {
0102         dev_info(sdev->dev, "IMR not set by BIOS. Ignoring\n");
0103         goto irq;
0104     }
0105
0106     dev_dbg(sdev->dev, "IMR base at 0x%x size 0x%x", base, size);
0107     sdev->bar[IMR_BAR] = devm_ioremap(sdev->dev, base, size);
0108     if (!sdev->bar[IMR_BAR]) {
0109         dev_err(sdev->dev, "error: failed to ioremap IMR base 0x%x size 0x%x\n",
0110             base, size);
0111         return -ENODEV;
0112     }
0113     dev_dbg(sdev->dev, "IMR VADDR %p\n", sdev->bar[IMR_BAR]);
0114
0115 irq:
0116     /* register our IRQ */
0117     sdev->ipc_irq = pci->irq;
0118     dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq);
0119     ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq,
0120                     atom_irq_handler, atom_irq_thread,
0121                     0, "AudioDSP", sdev);
0122     if (ret < 0) {
0123         dev_err(sdev->dev, "error: failed to register IRQ %d\n",
0124             sdev->ipc_irq);
0125         return ret;
0126     }
0127
0128     /* enable BUSY and disable DONE Interrupt by default */
0129     snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_IMRX,
0130                   SHIM_IMRX_BUSY | SHIM_IMRX_DONE,
0131                   SHIM_IMRX_DONE);
0132
0133     /* set default mailbox offset for FW ready message */
0134     sdev->dsp_box.offset = MBOX_OFFSET;
0135
0136     return ret;
0137 }
0138
0139 struct snd_sof_dsp_ops sof_tng_ops = {
0140     /* device init */
0141     .probe      = tangier_pci_probe,
0142
0143     /* DSP core boot / reset */
0144     .run        = atom_run,
0145     .reset      = atom_reset,
0146
0147     /* Register IO */
0148     .write      = sof_io_write,
0149     .read       = sof_io_read,
0150     .write64    = sof_io_write64,
0151     .read64     = sof_io_read64,
0152
0153     /* Block IO */
0154     .block_read = sof_block_read,
0155     .block_write    = sof_block_write,
0156
0157     /* Mailbox IO */
0158     .mailbox_read   = sof_mailbox_read,
0159     .mailbox_write  = sof_mailbox_write,
0160
0161     /* doorbell */
0162     .irq_handler    = atom_irq_handler,
0163     .irq_thread = atom_irq_thread,
0164
0165     /* ipc */
0166     .send_msg   = atom_send_msg,
0167     .get_mailbox_offset = atom_get_mailbox_offset,
0168     .get_window_offset = atom_get_window_offset,
0169
0170     .ipc_msg_data   = sof_ipc_msg_data,
0171     .set_stream_data_offset = sof_set_stream_data_offset,
0172
0173     /* machine driver */
0174     .machine_select = atom_machine_select,
0175     .machine_register = sof_machine_register,
0176     .machine_unregister = sof_machine_unregister,
0177     .set_mach_params = atom_set_mach_params,
0178
0179     /* debug */
0180     .debug_map  = tng_debugfs,
0181     .debug_map_count    = ARRAY_SIZE(tng_debugfs),
0182     .dbg_dump   = atom_dump,
0183     .debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem,
0184
0185     /* stream callbacks */
0186     .pcm_open   = sof_stream_pcm_open,
0187     .pcm_close  = sof_stream_pcm_close,
0188
0189     /*Firmware loading */
0190     .load_firmware  = snd_sof_load_firmware_memcpy,
0191
0192     /* DAI drivers */
0193     .drv = atom_dai,
0194     .num_drv = 3, /* we have only 3 SSPs on byt*/
0195
0196     /* ALSA HW info flags */
0197     .hw_info =  SNDRV_PCM_INFO_MMAP |
0198             SNDRV_PCM_INFO_MMAP_VALID |
0199             SNDRV_PCM_INFO_INTERLEAVED |
0200             SNDRV_PCM_INFO_PAUSE |
0201             SNDRV_PCM_INFO_BATCH,
0202
0203     .dsp_arch_ops = &sof_xtensa_arch_ops,
0204 };
0205
0206 const struct sof_intel_dsp_desc tng_chip_info = {
0207     .cores_num = 1,
0208     .host_managed_cores_mask = 1,
0209     .hw_ip_version = SOF_INTEL_TANGIER,
0210 };
0211
0212 static const struct sof_dev_desc tng_desc = {
0213     .machines       = sof_tng_machines,
0214     .resindex_lpe_base  = 3,    /* IRAM, but subtract IRAM offset */
0215     .resindex_pcicfg_base   = -1,
0216     .resindex_imr_base  = 0,
0217     .irqindex_host_ipc  = -1,
0218     .chip_info = &tng_chip_info,
0219     .ipc_supported_mask = BIT(SOF_IPC),
0220     .ipc_default        = SOF_IPC,
0221     .default_fw_path = {
0222         [SOF_IPC] = "intel/sof",
0223     },
0224     .default_tplg_path = {
0225         [SOF_IPC] = "intel/sof-tplg",
0226     },
0227     .default_fw_filename = {
0228         [SOF_IPC] = "sof-byt.ri",
0229     },
0230     .nocodec_tplg_filename = "sof-byt.tplg",
0231     .ops = &sof_tng_ops,
0232 };
0233
0234 /* PCI IDs */
0235 static const struct pci_device_id sof_pci_ids[] = {
0236     { PCI_DEVICE(0x8086, 0x119a),
0237         .driver_data = (unsigned long)&tng_desc},
0238     { 0, }
0239 };
0240 MODULE_DEVICE_TABLE(pci, sof_pci_ids);
0241
0242 /* pci_driver definition */
0243 static struct pci_driver snd_sof_pci_intel_tng_driver = {
0244     .name = "sof-audio-pci-intel-tng",
0245     .id_table = sof_pci_ids,
0246     .probe = sof_pci_probe,
0247     .remove = sof_pci_remove,
0248     .shutdown = sof_pci_shutdown,
0249     .driver = {
0250         .pm = &sof_pci_pm,
0251     },
0252 };
0253 module_pci_driver(snd_sof_pci_intel_tng_driver);
0254
0255 MODULE_LICENSE("Dual BSD/GPL");
0256 MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_HIFI_EP_IPC);
0257 MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA);
0258 MODULE_IMPORT_NS(SND_SOC_SOF_PCI_DEV);
0259 MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_ATOM_HIFI_EP);