sof/intel/mtl.h

0001 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
0002 /*
0003  * This file is provided under a dual BSD/GPLv2 license.  When using or
0004  * redistributing this file, you may do so under either license.
0005  *
0006  * Copyright(c) 2020-2022 Intel Corporation. All rights reserved.
0007  */
0008
0009 /* DSP Registers */
0010 #define MTL_HFDSSCS         0x1000
0011 #define MTL_HFDSSCS_SPA_MASK        BIT(16)
0012 #define MTL_HFDSSCS_CPA_MASK        BIT(24)
0013 #define MTL_HFSNDWIE            0x114C
0014 #define MTL_HFPWRCTL            0x1D18
0015 #define MTL_HfPWRCTL_WPIOXPG(x)     BIT((x) + 8)
0016 #define MTL_HFPWRCTL_WPDSPHPXPG     BIT(0)
0017 #define MTL_HFPWRSTS            0x1D1C
0018 #define MTL_HFPWRSTS_DSPHPXPGS_MASK BIT(0)
0019 #define MTL_HFINTIPPTR          0x1108
0020 #define MTL_IRQ_INTEN_L_HOST_IPC_MASK   BIT(0)
0021 #define MTL_IRQ_INTEN_L_SOUNDWIRE_MASK  BIT(6)
0022 #define MTL_HFINTIPPTR_PTR_MASK     GENMASK(20, 0)
0023
0024 #define MTL_DSP2CXCAP_PRIMARY_CORE  0x178D00
0025 #define MTL_DSP2CXCTL_PRIMARY_CORE  0x178D04
0026 #define MTL_DSP2CXCTL_PRIMARY_CORE_SPA_MASK BIT(0)
0027 #define MTL_DSP2CXCTL_PRIMARY_CORE_CPA_MASK BIT(8)
0028 #define MTL_DSP2CXCTL_PRIMARY_CORE_OSEL GENMASK(25, 24)
0029 #define MTL_DSP2CXCTL_PRIMARY_CORE_OSEL_SHIFT 24
0030
0031 /* IPC Registers */
0032 #define MTL_DSP_REG_HFIPCXTDR       0x73200
0033 #define MTL_DSP_REG_HFIPCXTDR_BUSY  BIT(31)
0034 #define MTL_DSP_REG_HFIPCXTDR_MSG_MASK GENMASK(30, 0)
0035 #define MTL_DSP_REG_HFIPCXTDA       0x73204
0036 #define MTL_DSP_REG_HFIPCXTDA_BUSY  BIT(31)
0037 #define MTL_DSP_REG_HFIPCXIDR       0x73210
0038 #define MTL_DSP_REG_HFIPCXIDR_BUSY  BIT(31)
0039 #define MTL_DSP_REG_HFIPCXIDR_MSG_MASK GENMASK(30, 0)
0040 #define MTL_DSP_REG_HFIPCXIDA       0x73214
0041 #define MTL_DSP_REG_HFIPCXIDA_DONE  BIT(31)
0042 #define MTL_DSP_REG_HFIPCXIDA_MSG_MASK GENMASK(30, 0)
0043 #define MTL_DSP_REG_HFIPCXCTL       0x73228
0044 #define MTL_DSP_REG_HFIPCXCTL_BUSY  BIT(0)
0045 #define MTL_DSP_REG_HFIPCXCTL_DONE  BIT(1)
0046 #define MTL_DSP_REG_HFIPCXTDDY      0x73300
0047 #define MTL_DSP_REG_HFIPCXIDDY      0x73380
0048 #define MTL_DSP_REG_HfHIPCIE        0x1140
0049 #define MTL_DSP_REG_HfHIPCIE_IE_MASK    BIT(0)
0050 #define MTL_DSP_REG_HfSNDWIE        0x114C
0051 #define MTL_DSP_REG_HfSNDWIE_IE_MASK    GENMASK(3, 0)
0052
0053 #define MTL_DSP_IRQSTS          0x20
0054 #define MTL_DSP_IRQSTS_IPC      BIT(0)
0055 #define MTL_DSP_IRQSTS_SDW      BIT(6)
0056
0057 #define MTL_DSP_PURGE_TIMEOUT_US    20000000 /* 20s */
0058 #define MTL_DSP_REG_POLL_INTERVAL_US    10  /* 10 us */
0059
0060 /* Memory windows */
0061 #define MTL_SRAM_WINDOW_OFFSET(x)   (0x180000 + 0x8000 * (x))
0062
0063 #define MTL_DSP_MBOX_UPLINK_OFFSET  (MTL_SRAM_WINDOW_OFFSET(0) + 0x1000)
0064 #define MTL_DSP_MBOX_UPLINK_SIZE    0x1000
0065 #define MTL_DSP_MBOX_DOWNLINK_OFFSET    MTL_SRAM_WINDOW_OFFSET(1)
0066 #define MTL_DSP_MBOX_DOWNLINK_SIZE  0x1000
0067
0068 /* FW registers */
0069 #define MTL_DSP_ROM_STS         MTL_SRAM_WINDOW_OFFSET(0) /* ROM status */
0070 #define MTL_DSP_ROM_ERROR       (MTL_SRAM_WINDOW_OFFSET(0) + 0x4) /* ROM error code */
0071
0072 #define MTL_DSP_REG_HFFLGPXQWY      0x163200 /* ROM debug status */
0073 #define MTL_DSP_REG_HFFLGPXQWY_ERROR    0x163204 /* ROM debug error code */
0074 #define MTL_DSP_REG_HfIMRIS1        0x162088
0075 #define MTL_DSP_REG_HfIMRIS1_IU_MASK    BIT(0)
0076