sof/intel/icl.c

0001 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
0002 //
0003 // Copyright(c) 2020 Intel Corporation. All rights reserved.
0004 //
0005 // Author: Fred Oh <fred.oh@linux.intel.com>
0006 //
0007
0008 /*
0009  * Hardware interface for audio DSP on IceLake.
0010  */
0011
0012 #include <linux/kernel.h>
0013 #include <linux/kconfig.h>
0014 #include <linux/export.h>
0015 #include <linux/bits.h>
0016 #include "../ops.h"
0017 #include "hda.h"
0018 #include "hda-ipc.h"
0019 #include "../sof-audio.h"
0020
0021 #define ICL_DSP_HPRO_CORE_ID 3
0022
0023 static const struct snd_sof_debugfs_map icl_dsp_debugfs[] = {
0024     {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS},
0025     {"pp", HDA_DSP_PP_BAR,  0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS},
0026     {"dsp", HDA_DSP_BAR,  0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
0027 };
0028
0029 static int icl_dsp_core_stall(struct snd_sof_dev *sdev, unsigned int core_mask)
0030 {
0031     struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
0032     const struct sof_intel_dsp_desc *chip = hda->desc;
0033
0034     /* make sure core_mask in host managed cores */
0035     core_mask &= chip->host_managed_cores_mask;
0036     if (!core_mask) {
0037         dev_err(sdev->dev, "error: core_mask is not in host managed cores\n");
0038         return -EINVAL;
0039     }
0040
0041     /* stall core */
0042     snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS,
0043                      HDA_DSP_ADSPCS_CSTALL_MASK(core_mask),
0044                      HDA_DSP_ADSPCS_CSTALL_MASK(core_mask));
0045
0046     return 0;
0047 }
0048
0049 /*
0050  * post fw run operation for ICL.
0051  * Core 3 will be powered up and in stall when HPRO is enabled
0052  */
0053 static int icl_dsp_post_fw_run(struct snd_sof_dev *sdev)
0054 {
0055     struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
0056     int ret;
0057
0058     if (sdev->first_boot) {
0059         struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
0060
0061         ret = hda_sdw_startup(sdev);
0062         if (ret < 0) {
0063             dev_err(sdev->dev, "error: could not startup SoundWire links\n");
0064             return ret;
0065         }
0066
0067         /* Check if IMR boot is usable */
0068         if (!sof_debug_check_flag(SOF_DBG_IGNORE_D3_PERSISTENT) &&
0069             sdev->fw_ready.flags & SOF_IPC_INFO_D3_PERSISTENT)
0070             hdev->imrboot_supported = true;
0071     }
0072
0073     hda_sdw_int_enable(sdev, true);
0074
0075     /*
0076      * The recommended HW programming sequence for ICL is to
0077      * power up core 3 and keep it in stall if HPRO is enabled.
0078      */
0079     if (!hda->clk_config_lpro) {
0080         ret = hda_dsp_enable_core(sdev, BIT(ICL_DSP_HPRO_CORE_ID));
0081         if (ret < 0) {
0082             dev_err(sdev->dev, "error: dsp core power up failed on core %d\n",
0083                 ICL_DSP_HPRO_CORE_ID);
0084             return ret;
0085         }
0086
0087         sdev->enabled_cores_mask |= BIT(ICL_DSP_HPRO_CORE_ID);
0088         sdev->dsp_core_ref_count[ICL_DSP_HPRO_CORE_ID]++;
0089
0090         snd_sof_dsp_stall(sdev, BIT(ICL_DSP_HPRO_CORE_ID));
0091     }
0092
0093     /* re-enable clock gating and power gating */
0094     return hda_dsp_ctrl_clock_power_gating(sdev, true);
0095 }
0096
0097 /* Icelake ops */
0098 struct snd_sof_dsp_ops sof_icl_ops;
0099 EXPORT_SYMBOL_NS(sof_icl_ops, SND_SOC_SOF_INTEL_HDA_COMMON);
0100
0101 int sof_icl_ops_init(struct snd_sof_dev *sdev)
0102 {
0103     /* common defaults */
0104     memcpy(&sof_icl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops));
0105
0106     /* probe/remove/shutdown */
0107     sof_icl_ops.shutdown    = hda_dsp_shutdown;
0108
0109     /* doorbell */
0110     sof_icl_ops.irq_thread  = cnl_ipc_irq_thread;
0111
0112     /* ipc */
0113     sof_icl_ops.send_msg    = cnl_ipc_send_msg;
0114
0115     /* debug */
0116     sof_icl_ops.debug_map   = icl_dsp_debugfs;
0117     sof_icl_ops.debug_map_count = ARRAY_SIZE(icl_dsp_debugfs);
0118     sof_icl_ops.ipc_dump    = cnl_ipc_dump;
0119
0120     /* pre/post fw run */
0121     sof_icl_ops.post_fw_run = icl_dsp_post_fw_run;
0122
0123     /* firmware run */
0124     sof_icl_ops.run = hda_dsp_cl_boot_firmware_iccmax;
0125     sof_icl_ops.stall = icl_dsp_core_stall;
0126
0127     /* dsp core get/put */
0128     sof_icl_ops.core_get = hda_dsp_core_get;
0129
0130     /* set DAI driver ops */
0131     hda_set_dai_drv_ops(sdev, &sof_icl_ops);
0132
0133     return 0;
0134 };
0135 EXPORT_SYMBOL_NS(sof_icl_ops_init, SND_SOC_SOF_INTEL_HDA_COMMON);
0136
0137 const struct sof_intel_dsp_desc icl_chip_info = {
0138     /* Icelake */
0139     .cores_num = 4,
0140     .init_core_mask = 1,
0141     .host_managed_cores_mask = GENMASK(3, 0),
0142     .ipc_req = CNL_DSP_REG_HIPCIDR,
0143     .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
0144     .ipc_ack = CNL_DSP_REG_HIPCIDA,
0145     .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
0146     .ipc_ctl = CNL_DSP_REG_HIPCCTL,
0147     .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
0148     .rom_init_timeout   = 300,
0149     .ssp_count = ICL_SSP_COUNT,
0150     .ssp_base_offset = CNL_SSP_BASE_OFFSET,
0151     .sdw_shim_base = SDW_SHIM_BASE,
0152     .sdw_alh_base = SDW_ALH_BASE,
0153     .check_sdw_irq  = hda_common_check_sdw_irq,
0154     .check_ipc_irq  = hda_dsp_check_ipc_irq,
0155     .cl_init = cl_dsp_init,
0156     .hw_ip_version = SOF_INTEL_CAVS_2_0,
0157 };
0158 EXPORT_SYMBOL_NS(icl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);