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0001 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
0002 //
0003 // This file is provided under a dual BSD/GPLv2 license.  When using or
0004 // redistributing this file, you may do so under either license.
0005 //
0006 // Copyright(c) 2018 Intel Corporation. All rights reserved.
0007 //
0008 // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
0009 //      Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
0010 //      Rander Wang <rander.wang@intel.com>
0011 //          Keyon Jie <yang.jie@linux.intel.com>
0012 //
0013 
0014 /*
0015  * Hardware interface for generic Intel audio DSP HDA IP
0016  */
0017 
0018 #include <linux/pm_runtime.h>
0019 #include <sound/hdaudio_ext.h>
0020 #include <sound/hda_register.h>
0021 #include <sound/sof.h>
0022 #include "../ops.h"
0023 #include "../sof-audio.h"
0024 #include "hda.h"
0025 
0026 #define HDA_LTRP_GB_VALUE_US    95
0027 
0028 static inline const char *hda_hstream_direction_str(struct hdac_stream *hstream)
0029 {
0030     if (hstream->direction == SNDRV_PCM_STREAM_PLAYBACK)
0031         return "Playback";
0032     else
0033         return "Capture";
0034 }
0035 
0036 static char *hda_hstream_dbg_get_stream_info_str(struct hdac_stream *hstream)
0037 {
0038     struct snd_soc_pcm_runtime *rtd;
0039 
0040     if (hstream->substream)
0041         rtd = asoc_substream_to_rtd(hstream->substream);
0042     else if (hstream->cstream)
0043         rtd = hstream->cstream->private_data;
0044     else
0045         /* Non audio DMA user, like dma-trace */
0046         return kasprintf(GFP_KERNEL, "-- (%s, stream_tag: %u)",
0047                  hda_hstream_direction_str(hstream),
0048                  hstream->stream_tag);
0049 
0050     return kasprintf(GFP_KERNEL, "dai_link \"%s\" (%s, stream_tag: %u)",
0051              rtd->dai_link->name, hda_hstream_direction_str(hstream),
0052              hstream->stream_tag);
0053 }
0054 
0055 /*
0056  * set up one of BDL entries for a stream
0057  */
0058 static int hda_setup_bdle(struct snd_sof_dev *sdev,
0059               struct snd_dma_buffer *dmab,
0060               struct hdac_stream *hstream,
0061               struct sof_intel_dsp_bdl **bdlp,
0062               int offset, int size, int ioc)
0063 {
0064     struct hdac_bus *bus = sof_to_bus(sdev);
0065     struct sof_intel_dsp_bdl *bdl = *bdlp;
0066 
0067     while (size > 0) {
0068         dma_addr_t addr;
0069         int chunk;
0070 
0071         if (hstream->frags >= HDA_DSP_MAX_BDL_ENTRIES) {
0072             dev_err(sdev->dev, "error: stream frags exceeded\n");
0073             return -EINVAL;
0074         }
0075 
0076         addr = snd_sgbuf_get_addr(dmab, offset);
0077         /* program BDL addr */
0078         bdl->addr_l = cpu_to_le32(lower_32_bits(addr));
0079         bdl->addr_h = cpu_to_le32(upper_32_bits(addr));
0080         /* program BDL size */
0081         chunk = snd_sgbuf_get_chunk_size(dmab, offset, size);
0082         /* one BDLE should not cross 4K boundary */
0083         if (bus->align_bdle_4k) {
0084             u32 remain = 0x1000 - (offset & 0xfff);
0085 
0086             if (chunk > remain)
0087                 chunk = remain;
0088         }
0089         bdl->size = cpu_to_le32(chunk);
0090         /* only program IOC when the whole segment is processed */
0091         size -= chunk;
0092         bdl->ioc = (size || !ioc) ? 0 : cpu_to_le32(0x01);
0093         bdl++;
0094         hstream->frags++;
0095         offset += chunk;
0096 
0097         dev_vdbg(sdev->dev, "bdl, frags:%d, chunk size:0x%x;\n",
0098              hstream->frags, chunk);
0099     }
0100 
0101     *bdlp = bdl;
0102     return offset;
0103 }
0104 
0105 /*
0106  * set up Buffer Descriptor List (BDL) for host memory transfer
0107  * BDL describes the location of the individual buffers and is little endian.
0108  */
0109 int hda_dsp_stream_setup_bdl(struct snd_sof_dev *sdev,
0110                  struct snd_dma_buffer *dmab,
0111                  struct hdac_stream *hstream)
0112 {
0113     struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
0114     struct sof_intel_dsp_bdl *bdl;
0115     int i, offset, period_bytes, periods;
0116     int remain, ioc;
0117 
0118     period_bytes = hstream->period_bytes;
0119     dev_dbg(sdev->dev, "period_bytes:0x%x\n", period_bytes);
0120     if (!period_bytes)
0121         period_bytes = hstream->bufsize;
0122 
0123     periods = hstream->bufsize / period_bytes;
0124 
0125     dev_dbg(sdev->dev, "periods:%d\n", periods);
0126 
0127     remain = hstream->bufsize % period_bytes;
0128     if (remain)
0129         periods++;
0130 
0131     /* program the initial BDL entries */
0132     bdl = (struct sof_intel_dsp_bdl *)hstream->bdl.area;
0133     offset = 0;
0134     hstream->frags = 0;
0135 
0136     /*
0137      * set IOC if don't use position IPC
0138      * and period_wakeup needed.
0139      */
0140     ioc = hda->no_ipc_position ?
0141           !hstream->no_period_wakeup : 0;
0142 
0143     for (i = 0; i < periods; i++) {
0144         if (i == (periods - 1) && remain)
0145             /* set the last small entry */
0146             offset = hda_setup_bdle(sdev, dmab,
0147                         hstream, &bdl, offset,
0148                         remain, 0);
0149         else
0150             offset = hda_setup_bdle(sdev, dmab,
0151                         hstream, &bdl, offset,
0152                         period_bytes, ioc);
0153     }
0154 
0155     return offset;
0156 }
0157 
0158 int hda_dsp_stream_spib_config(struct snd_sof_dev *sdev,
0159                    struct hdac_ext_stream *hext_stream,
0160                    int enable, u32 size)
0161 {
0162     struct hdac_stream *hstream = &hext_stream->hstream;
0163     u32 mask;
0164 
0165     if (!sdev->bar[HDA_DSP_SPIB_BAR]) {
0166         dev_err(sdev->dev, "error: address of spib capability is NULL\n");
0167         return -EINVAL;
0168     }
0169 
0170     mask = (1 << hstream->index);
0171 
0172     /* enable/disable SPIB for the stream */
0173     snd_sof_dsp_update_bits(sdev, HDA_DSP_SPIB_BAR,
0174                 SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCCTL, mask,
0175                 enable << hstream->index);
0176 
0177     /* set the SPIB value */
0178     sof_io_write(sdev, hext_stream->spib_addr, size);
0179 
0180     return 0;
0181 }
0182 
0183 /* get next unused stream */
0184 struct hdac_ext_stream *
0185 hda_dsp_stream_get(struct snd_sof_dev *sdev, int direction, u32 flags)
0186 {
0187     struct hdac_bus *bus = sof_to_bus(sdev);
0188     struct sof_intel_hda_stream *hda_stream;
0189     struct hdac_ext_stream *hext_stream = NULL;
0190     struct hdac_stream *s;
0191 
0192     spin_lock_irq(&bus->reg_lock);
0193 
0194     /* get an unused stream */
0195     list_for_each_entry(s, &bus->stream_list, list) {
0196         if (s->direction == direction && !s->opened) {
0197             hext_stream = stream_to_hdac_ext_stream(s);
0198             hda_stream = container_of(hext_stream,
0199                           struct sof_intel_hda_stream,
0200                           hext_stream);
0201             /* check if the host DMA channel is reserved */
0202             if (hda_stream->host_reserved)
0203                 continue;
0204 
0205             s->opened = true;
0206             break;
0207         }
0208     }
0209 
0210     spin_unlock_irq(&bus->reg_lock);
0211 
0212     /* stream found ? */
0213     if (!hext_stream) {
0214         dev_err(sdev->dev, "error: no free %s streams\n",
0215             direction == SNDRV_PCM_STREAM_PLAYBACK ?
0216             "playback" : "capture");
0217         return hext_stream;
0218     }
0219 
0220     hda_stream->flags = flags;
0221 
0222     /*
0223      * Prevent DMI Link L1 entry for streams that don't support it.
0224      * Workaround to address a known issue with host DMA that results
0225      * in xruns during pause/release in capture scenarios.
0226      */
0227     if (!(flags & SOF_HDA_STREAM_DMI_L1_COMPATIBLE))
0228         snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
0229                     HDA_VS_INTEL_EM2,
0230                     HDA_VS_INTEL_EM2_L1SEN, 0);
0231 
0232     return hext_stream;
0233 }
0234 
0235 /* free a stream */
0236 int hda_dsp_stream_put(struct snd_sof_dev *sdev, int direction, int stream_tag)
0237 {
0238     struct hdac_bus *bus = sof_to_bus(sdev);
0239     struct sof_intel_hda_stream *hda_stream;
0240     struct hdac_ext_stream *hext_stream;
0241     struct hdac_stream *s;
0242     bool dmi_l1_enable = true;
0243     bool found = false;
0244 
0245     spin_lock_irq(&bus->reg_lock);
0246 
0247     /*
0248      * close stream matching the stream tag and check if there are any open streams
0249      * that are DMI L1 incompatible.
0250      */
0251     list_for_each_entry(s, &bus->stream_list, list) {
0252         hext_stream = stream_to_hdac_ext_stream(s);
0253         hda_stream = container_of(hext_stream, struct sof_intel_hda_stream, hext_stream);
0254 
0255         if (!s->opened)
0256             continue;
0257 
0258         if (s->direction == direction && s->stream_tag == stream_tag) {
0259             s->opened = false;
0260             found = true;
0261         } else if (!(hda_stream->flags & SOF_HDA_STREAM_DMI_L1_COMPATIBLE)) {
0262             dmi_l1_enable = false;
0263         }
0264     }
0265 
0266     spin_unlock_irq(&bus->reg_lock);
0267 
0268     /* Enable DMI L1 if permitted */
0269     if (dmi_l1_enable)
0270         snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, HDA_VS_INTEL_EM2,
0271                     HDA_VS_INTEL_EM2_L1SEN, HDA_VS_INTEL_EM2_L1SEN);
0272 
0273     if (!found) {
0274         dev_err(sdev->dev, "%s: stream_tag %d not opened!\n",
0275             __func__, stream_tag);
0276         return -ENODEV;
0277     }
0278 
0279     return 0;
0280 }
0281 
0282 static int hda_dsp_stream_reset(struct snd_sof_dev *sdev, struct hdac_stream *hstream)
0283 {
0284     int sd_offset = SOF_STREAM_SD_OFFSET(hstream);
0285     int timeout = HDA_DSP_STREAM_RESET_TIMEOUT;
0286     u32 val;
0287 
0288     /* enter stream reset */
0289     snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset, SOF_STREAM_SD_OFFSET_CRST,
0290                 SOF_STREAM_SD_OFFSET_CRST);
0291     do {
0292         val = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, sd_offset);
0293         if (val & SOF_STREAM_SD_OFFSET_CRST)
0294             break;
0295     } while (--timeout);
0296     if (timeout == 0) {
0297         dev_err(sdev->dev, "timeout waiting for stream reset\n");
0298         return -ETIMEDOUT;
0299     }
0300 
0301     timeout = HDA_DSP_STREAM_RESET_TIMEOUT;
0302 
0303     /* exit stream reset and wait to read a zero before reading any other register */
0304     snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset, SOF_STREAM_SD_OFFSET_CRST, 0x0);
0305 
0306     /* wait for hardware to report that stream is out of reset */
0307     udelay(3);
0308     do {
0309         val = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, sd_offset);
0310         if ((val & SOF_STREAM_SD_OFFSET_CRST) == 0)
0311             break;
0312     } while (--timeout);
0313     if (timeout == 0) {
0314         dev_err(sdev->dev, "timeout waiting for stream to exit reset\n");
0315         return -ETIMEDOUT;
0316     }
0317 
0318     return 0;
0319 }
0320 
0321 int hda_dsp_stream_trigger(struct snd_sof_dev *sdev,
0322                struct hdac_ext_stream *hext_stream, int cmd)
0323 {
0324     struct hdac_stream *hstream = &hext_stream->hstream;
0325     int sd_offset = SOF_STREAM_SD_OFFSET(hstream);
0326     u32 dma_start = SOF_HDA_SD_CTL_DMA_START;
0327     int ret = 0;
0328     u32 run;
0329 
0330     /* cmd must be for audio stream */
0331     switch (cmd) {
0332     case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
0333     case SNDRV_PCM_TRIGGER_START:
0334         snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
0335                     1 << hstream->index,
0336                     1 << hstream->index);
0337 
0338         snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
0339                     sd_offset,
0340                     SOF_HDA_SD_CTL_DMA_START |
0341                     SOF_HDA_CL_DMA_SD_INT_MASK,
0342                     SOF_HDA_SD_CTL_DMA_START |
0343                     SOF_HDA_CL_DMA_SD_INT_MASK);
0344 
0345         ret = snd_sof_dsp_read_poll_timeout(sdev,
0346                     HDA_DSP_HDA_BAR,
0347                     sd_offset, run,
0348                     ((run & dma_start) == dma_start),
0349                     HDA_DSP_REG_POLL_INTERVAL_US,
0350                     HDA_DSP_STREAM_RUN_TIMEOUT);
0351 
0352         if (ret >= 0)
0353             hstream->running = true;
0354 
0355         break;
0356     case SNDRV_PCM_TRIGGER_SUSPEND:
0357     case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
0358     case SNDRV_PCM_TRIGGER_STOP:
0359         snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
0360                     sd_offset,
0361                     SOF_HDA_SD_CTL_DMA_START |
0362                     SOF_HDA_CL_DMA_SD_INT_MASK, 0x0);
0363 
0364         ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_HDA_BAR,
0365                         sd_offset, run,
0366                         !(run & dma_start),
0367                         HDA_DSP_REG_POLL_INTERVAL_US,
0368                         HDA_DSP_STREAM_RUN_TIMEOUT);
0369 
0370         if (ret >= 0) {
0371             snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
0372                       sd_offset + SOF_HDA_ADSP_REG_CL_SD_STS,
0373                       SOF_HDA_CL_DMA_SD_INT_MASK);
0374 
0375             hstream->running = false;
0376             snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
0377                         SOF_HDA_INTCTL,
0378                         1 << hstream->index, 0x0);
0379         }
0380         break;
0381     default:
0382         dev_err(sdev->dev, "error: unknown command: %d\n", cmd);
0383         return -EINVAL;
0384     }
0385 
0386     if (ret < 0) {
0387         char *stream_name = hda_hstream_dbg_get_stream_info_str(hstream);
0388 
0389         dev_err(sdev->dev,
0390             "%s: cmd %d on %s: timeout on STREAM_SD_OFFSET read\n",
0391             __func__, cmd, stream_name ? stream_name : "unknown stream");
0392         kfree(stream_name);
0393     }
0394 
0395     return ret;
0396 }
0397 
0398 /* minimal recommended programming for ICCMAX stream */
0399 int hda_dsp_iccmax_stream_hw_params(struct snd_sof_dev *sdev, struct hdac_ext_stream *hext_stream,
0400                     struct snd_dma_buffer *dmab,
0401                     struct snd_pcm_hw_params *params)
0402 {
0403     struct hdac_bus *bus = sof_to_bus(sdev);
0404     struct hdac_stream *hstream = &hext_stream->hstream;
0405     int sd_offset = SOF_STREAM_SD_OFFSET(hstream);
0406     int ret;
0407     u32 mask = 0x1 << hstream->index;
0408 
0409     if (!hext_stream) {
0410         dev_err(sdev->dev, "error: no stream available\n");
0411         return -ENODEV;
0412     }
0413 
0414     if (!dmab) {
0415         dev_err(sdev->dev, "error: no dma buffer allocated!\n");
0416         return -ENODEV;
0417     }
0418 
0419     if (hstream->posbuf)
0420         *hstream->posbuf = 0;
0421 
0422     /* reset BDL address */
0423     snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
0424               sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPL,
0425               0x0);
0426     snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
0427               sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPU,
0428               0x0);
0429 
0430     hstream->frags = 0;
0431 
0432     ret = hda_dsp_stream_setup_bdl(sdev, dmab, hstream);
0433     if (ret < 0) {
0434         dev_err(sdev->dev, "error: set up of BDL failed\n");
0435         return ret;
0436     }
0437 
0438     /* program BDL address */
0439     snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
0440               sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPL,
0441               (u32)hstream->bdl.addr);
0442     snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
0443               sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPU,
0444               upper_32_bits(hstream->bdl.addr));
0445 
0446     /* program cyclic buffer length */
0447     snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
0448               sd_offset + SOF_HDA_ADSP_REG_CL_SD_CBL,
0449               hstream->bufsize);
0450 
0451     /* program last valid index */
0452     snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
0453                 sd_offset + SOF_HDA_ADSP_REG_CL_SD_LVI,
0454                 0xffff, (hstream->frags - 1));
0455 
0456     /* decouple host and link DMA, enable DSP features */
0457     snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
0458                 mask, mask);
0459 
0460     /* Follow HW recommendation to set the guardband value to 95us during FW boot */
0461     snd_hdac_chip_updateb(bus, VS_LTRP, HDA_VS_INTEL_LTRP_GB_MASK, HDA_LTRP_GB_VALUE_US);
0462 
0463     /* start DMA */
0464     snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset,
0465                 SOF_HDA_SD_CTL_DMA_START, SOF_HDA_SD_CTL_DMA_START);
0466 
0467     return 0;
0468 }
0469 
0470 /*
0471  * prepare for common hdac registers settings, for both code loader
0472  * and normal stream.
0473  */
0474 int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev,
0475                  struct hdac_ext_stream *hext_stream,
0476                  struct snd_dma_buffer *dmab,
0477                  struct snd_pcm_hw_params *params)
0478 {
0479     const struct sof_intel_dsp_desc *chip = get_chip_info(sdev->pdata);
0480     struct hdac_bus *bus = sof_to_bus(sdev);
0481     struct hdac_stream *hstream = &hext_stream->hstream;
0482     int sd_offset = SOF_STREAM_SD_OFFSET(hstream);
0483     int ret;
0484     u32 dma_start = SOF_HDA_SD_CTL_DMA_START;
0485     u32 mask;
0486     u32 run;
0487 
0488     if (!hext_stream) {
0489         dev_err(sdev->dev, "error: no stream available\n");
0490         return -ENODEV;
0491     }
0492 
0493     if (!dmab) {
0494         dev_err(sdev->dev, "error: no dma buffer allocated!\n");
0495         return -ENODEV;
0496     }
0497 
0498     /* decouple host and link DMA */
0499     mask = 0x1 << hstream->index;
0500     snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
0501                 mask, mask);
0502 
0503     /* clear stream status */
0504     snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset,
0505                 SOF_HDA_CL_DMA_SD_INT_MASK |
0506                 SOF_HDA_SD_CTL_DMA_START, 0);
0507 
0508     ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_HDA_BAR,
0509                         sd_offset, run,
0510                         !(run & dma_start),
0511                         HDA_DSP_REG_POLL_INTERVAL_US,
0512                         HDA_DSP_STREAM_RUN_TIMEOUT);
0513 
0514     if (ret < 0) {
0515         char *stream_name = hda_hstream_dbg_get_stream_info_str(hstream);
0516 
0517         dev_err(sdev->dev,
0518             "%s: on %s: timeout on STREAM_SD_OFFSET read1\n",
0519             __func__, stream_name ? stream_name : "unknown stream");
0520         kfree(stream_name);
0521         return ret;
0522     }
0523 
0524     snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
0525                 sd_offset + SOF_HDA_ADSP_REG_CL_SD_STS,
0526                 SOF_HDA_CL_DMA_SD_INT_MASK,
0527                 SOF_HDA_CL_DMA_SD_INT_MASK);
0528 
0529     /* stream reset */
0530     ret = hda_dsp_stream_reset(sdev, hstream);
0531     if (ret < 0)
0532         return ret;
0533 
0534     if (hstream->posbuf)
0535         *hstream->posbuf = 0;
0536 
0537     /* reset BDL address */
0538     snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
0539               sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPL,
0540               0x0);
0541     snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
0542               sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPU,
0543               0x0);
0544 
0545     /* clear stream status */
0546     snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset,
0547                 SOF_HDA_CL_DMA_SD_INT_MASK |
0548                 SOF_HDA_SD_CTL_DMA_START, 0);
0549 
0550     ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_HDA_BAR,
0551                         sd_offset, run,
0552                         !(run & dma_start),
0553                         HDA_DSP_REG_POLL_INTERVAL_US,
0554                         HDA_DSP_STREAM_RUN_TIMEOUT);
0555 
0556     if (ret < 0) {
0557         char *stream_name = hda_hstream_dbg_get_stream_info_str(hstream);
0558 
0559         dev_err(sdev->dev,
0560             "%s: on %s: timeout on STREAM_SD_OFFSET read1\n",
0561             __func__, stream_name ? stream_name : "unknown stream");
0562         kfree(stream_name);
0563         return ret;
0564     }
0565 
0566     snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
0567                 sd_offset + SOF_HDA_ADSP_REG_CL_SD_STS,
0568                 SOF_HDA_CL_DMA_SD_INT_MASK,
0569                 SOF_HDA_CL_DMA_SD_INT_MASK);
0570 
0571     hstream->frags = 0;
0572 
0573     ret = hda_dsp_stream_setup_bdl(sdev, dmab, hstream);
0574     if (ret < 0) {
0575         dev_err(sdev->dev, "error: set up of BDL failed\n");
0576         return ret;
0577     }
0578 
0579     /* program stream tag to set up stream descriptor for DMA */
0580     snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset,
0581                 SOF_HDA_CL_SD_CTL_STREAM_TAG_MASK,
0582                 hstream->stream_tag <<
0583                 SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT);
0584 
0585     /* program cyclic buffer length */
0586     snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
0587               sd_offset + SOF_HDA_ADSP_REG_CL_SD_CBL,
0588               hstream->bufsize);
0589 
0590     /*
0591      * Recommended hardware programming sequence for HDAudio DMA format
0592      * on earlier platforms - this is not needed on newer platforms
0593      *
0594      * 1. Put DMA into coupled mode by clearing PPCTL.PROCEN bit
0595      *    for corresponding stream index before the time of writing
0596      *    format to SDxFMT register.
0597      * 2. Write SDxFMT
0598      * 3. Set PPCTL.PROCEN bit for corresponding stream index to
0599      *    enable decoupled mode
0600      */
0601 
0602     if (chip->quirks & SOF_INTEL_PROCEN_FMT_QUIRK) {
0603         /* couple host and link DMA, disable DSP features */
0604         snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
0605                     mask, 0);
0606     }
0607 
0608     /* program stream format */
0609     snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
0610                 sd_offset +
0611                 SOF_HDA_ADSP_REG_CL_SD_FORMAT,
0612                 0xffff, hstream->format_val);
0613 
0614     if (chip->quirks & SOF_INTEL_PROCEN_FMT_QUIRK) {
0615         /* decouple host and link DMA, enable DSP features */
0616         snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
0617                     mask, mask);
0618     }
0619 
0620     /* program last valid index */
0621     snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
0622                 sd_offset + SOF_HDA_ADSP_REG_CL_SD_LVI,
0623                 0xffff, (hstream->frags - 1));
0624 
0625     /* program BDL address */
0626     snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
0627               sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPL,
0628               (u32)hstream->bdl.addr);
0629     snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
0630               sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPU,
0631               upper_32_bits(hstream->bdl.addr));
0632 
0633     /* enable position buffer, if needed */
0634     if (bus->use_posbuf && bus->posbuf.addr &&
0635         !(snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPLBASE)
0636           & SOF_HDA_ADSP_DPLBASE_ENABLE)) {
0637         snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPUBASE,
0638                   upper_32_bits(bus->posbuf.addr));
0639         snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPLBASE,
0640                   (u32)bus->posbuf.addr |
0641                   SOF_HDA_ADSP_DPLBASE_ENABLE);
0642     }
0643 
0644     /* set interrupt enable bits */
0645     snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset,
0646                 SOF_HDA_CL_DMA_SD_INT_MASK,
0647                 SOF_HDA_CL_DMA_SD_INT_MASK);
0648 
0649     /* read FIFO size */
0650     if (hstream->direction == SNDRV_PCM_STREAM_PLAYBACK) {
0651         hstream->fifo_size =
0652             snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR,
0653                      sd_offset +
0654                      SOF_HDA_ADSP_REG_CL_SD_FIFOSIZE);
0655         hstream->fifo_size &= 0xffff;
0656         hstream->fifo_size += 1;
0657     } else {
0658         hstream->fifo_size = 0;
0659     }
0660 
0661     return ret;
0662 }
0663 
0664 int hda_dsp_stream_hw_free(struct snd_sof_dev *sdev,
0665                struct snd_pcm_substream *substream)
0666 {
0667     struct hdac_stream *hstream = substream->runtime->private_data;
0668     struct hdac_ext_stream *hext_stream = container_of(hstream,
0669                              struct hdac_ext_stream,
0670                              hstream);
0671     struct hdac_bus *bus = sof_to_bus(sdev);
0672     u32 mask = 0x1 << hstream->index;
0673     int ret;
0674 
0675     ret = hda_dsp_stream_reset(sdev, hstream);
0676     if (ret < 0)
0677         return ret;
0678 
0679     spin_lock_irq(&bus->reg_lock);
0680     /* couple host and link DMA if link DMA channel is idle */
0681     if (!hext_stream->link_locked)
0682         snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR,
0683                     SOF_HDA_REG_PP_PPCTL, mask, 0);
0684     spin_unlock_irq(&bus->reg_lock);
0685 
0686     hda_dsp_stream_spib_config(sdev, hext_stream, HDA_DSP_SPIB_DISABLE, 0);
0687 
0688     hstream->substream = NULL;
0689 
0690     return 0;
0691 }
0692 
0693 bool hda_dsp_check_stream_irq(struct snd_sof_dev *sdev)
0694 {
0695     struct hdac_bus *bus = sof_to_bus(sdev);
0696     bool ret = false;
0697     u32 status;
0698 
0699     /* The function can be called at irq thread, so use spin_lock_irq */
0700     spin_lock_irq(&bus->reg_lock);
0701 
0702     status = snd_hdac_chip_readl(bus, INTSTS);
0703     dev_vdbg(bus->dev, "stream irq, INTSTS status: 0x%x\n", status);
0704 
0705     /* if Register inaccessible, ignore it.*/
0706     if (status != 0xffffffff)
0707         ret = true;
0708 
0709     spin_unlock_irq(&bus->reg_lock);
0710 
0711     return ret;
0712 }
0713 
0714 static void
0715 hda_dsp_compr_bytes_transferred(struct hdac_stream *hstream, int direction)
0716 {
0717     u64 buffer_size = hstream->bufsize;
0718     u64 prev_pos, pos, num_bytes;
0719 
0720     div64_u64_rem(hstream->curr_pos, buffer_size, &prev_pos);
0721     pos = hda_dsp_stream_get_position(hstream, direction, false);
0722 
0723     if (pos < prev_pos)
0724         num_bytes = (buffer_size - prev_pos) +  pos;
0725     else
0726         num_bytes = pos - prev_pos;
0727 
0728     hstream->curr_pos += num_bytes;
0729 }
0730 
0731 static bool hda_dsp_stream_check(struct hdac_bus *bus, u32 status)
0732 {
0733     struct sof_intel_hda_dev *sof_hda = bus_to_sof_hda(bus);
0734     struct hdac_stream *s;
0735     bool active = false;
0736     u32 sd_status;
0737 
0738     list_for_each_entry(s, &bus->stream_list, list) {
0739         if (status & BIT(s->index) && s->opened) {
0740             sd_status = snd_hdac_stream_readb(s, SD_STS);
0741 
0742             dev_vdbg(bus->dev, "stream %d status 0x%x\n",
0743                  s->index, sd_status);
0744 
0745             snd_hdac_stream_writeb(s, SD_STS, sd_status);
0746 
0747             active = true;
0748             if ((!s->substream && !s->cstream) ||
0749                 !s->running ||
0750                 (sd_status & SOF_HDA_CL_DMA_SD_INT_COMPLETE) == 0)
0751                 continue;
0752 
0753             /* Inform ALSA only in case not do that with IPC */
0754             if (s->substream && sof_hda->no_ipc_position) {
0755                 snd_sof_pcm_period_elapsed(s->substream);
0756             } else if (s->cstream) {
0757                 hda_dsp_compr_bytes_transferred(s, s->cstream->direction);
0758                 snd_compr_fragment_elapsed(s->cstream);
0759             }
0760         }
0761     }
0762 
0763     return active;
0764 }
0765 
0766 irqreturn_t hda_dsp_stream_threaded_handler(int irq, void *context)
0767 {
0768     struct snd_sof_dev *sdev = context;
0769     struct hdac_bus *bus = sof_to_bus(sdev);
0770 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
0771     u32 rirb_status;
0772 #endif
0773     bool active;
0774     u32 status;
0775     int i;
0776 
0777     /*
0778      * Loop 10 times to handle missed interrupts caused by
0779      * unsolicited responses from the codec
0780      */
0781     for (i = 0, active = true; i < 10 && active; i++) {
0782         spin_lock_irq(&bus->reg_lock);
0783 
0784         status = snd_hdac_chip_readl(bus, INTSTS);
0785 
0786         /* check streams */
0787         active = hda_dsp_stream_check(bus, status);
0788 
0789         /* check and clear RIRB interrupt */
0790 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
0791         if (status & AZX_INT_CTRL_EN) {
0792             rirb_status = snd_hdac_chip_readb(bus, RIRBSTS);
0793             if (rirb_status & RIRB_INT_MASK) {
0794                 /*
0795                  * Clearing the interrupt status here ensures
0796                  * that no interrupt gets masked after the RIRB
0797                  * wp is read in snd_hdac_bus_update_rirb.
0798                  */
0799                 snd_hdac_chip_writeb(bus, RIRBSTS,
0800                              RIRB_INT_MASK);
0801                 active = true;
0802                 if (rirb_status & RIRB_INT_RESPONSE)
0803                     snd_hdac_bus_update_rirb(bus);
0804             }
0805         }
0806 #endif
0807         spin_unlock_irq(&bus->reg_lock);
0808     }
0809 
0810     return IRQ_HANDLED;
0811 }
0812 
0813 int hda_dsp_stream_init(struct snd_sof_dev *sdev)
0814 {
0815     struct hdac_bus *bus = sof_to_bus(sdev);
0816     struct hdac_ext_stream *hext_stream;
0817     struct hdac_stream *hstream;
0818     struct pci_dev *pci = to_pci_dev(sdev->dev);
0819     struct sof_intel_hda_dev *sof_hda = bus_to_sof_hda(bus);
0820     int sd_offset;
0821     int i, num_playback, num_capture, num_total, ret;
0822     u32 gcap;
0823 
0824     gcap = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_GCAP);
0825     dev_dbg(sdev->dev, "hda global caps = 0x%x\n", gcap);
0826 
0827     /* get stream count from GCAP */
0828     num_capture = (gcap >> 8) & 0x0f;
0829     num_playback = (gcap >> 12) & 0x0f;
0830     num_total = num_playback + num_capture;
0831 
0832     dev_dbg(sdev->dev, "detected %d playback and %d capture streams\n",
0833         num_playback, num_capture);
0834 
0835     if (num_playback >= SOF_HDA_PLAYBACK_STREAMS) {
0836         dev_err(sdev->dev, "error: too many playback streams %d\n",
0837             num_playback);
0838         return -EINVAL;
0839     }
0840 
0841     if (num_capture >= SOF_HDA_CAPTURE_STREAMS) {
0842         dev_err(sdev->dev, "error: too many capture streams %d\n",
0843             num_playback);
0844         return -EINVAL;
0845     }
0846 
0847     /*
0848      * mem alloc for the position buffer
0849      * TODO: check position buffer update
0850      */
0851     ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev,
0852                   SOF_HDA_DPIB_ENTRY_SIZE * num_total,
0853                   &bus->posbuf);
0854     if (ret < 0) {
0855         dev_err(sdev->dev, "error: posbuffer dma alloc failed\n");
0856         return -ENOMEM;
0857     }
0858 
0859 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
0860     /* mem alloc for the CORB/RIRB ringbuffers */
0861     ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev,
0862                   PAGE_SIZE, &bus->rb);
0863     if (ret < 0) {
0864         dev_err(sdev->dev, "error: RB alloc failed\n");
0865         return -ENOMEM;
0866     }
0867 #endif
0868 
0869     /* create capture streams */
0870     for (i = 0; i < num_capture; i++) {
0871         struct sof_intel_hda_stream *hda_stream;
0872 
0873         hda_stream = devm_kzalloc(sdev->dev, sizeof(*hda_stream),
0874                       GFP_KERNEL);
0875         if (!hda_stream)
0876             return -ENOMEM;
0877 
0878         hda_stream->sdev = sdev;
0879 
0880         hext_stream = &hda_stream->hext_stream;
0881 
0882         hext_stream->pphc_addr = sdev->bar[HDA_DSP_PP_BAR] +
0883             SOF_HDA_PPHC_BASE + SOF_HDA_PPHC_INTERVAL * i;
0884 
0885         hext_stream->pplc_addr = sdev->bar[HDA_DSP_PP_BAR] +
0886             SOF_HDA_PPLC_BASE + SOF_HDA_PPLC_MULTI * num_total +
0887             SOF_HDA_PPLC_INTERVAL * i;
0888 
0889         /* do we support SPIB */
0890         if (sdev->bar[HDA_DSP_SPIB_BAR]) {
0891             hext_stream->spib_addr = sdev->bar[HDA_DSP_SPIB_BAR] +
0892                 SOF_HDA_SPIB_BASE + SOF_HDA_SPIB_INTERVAL * i +
0893                 SOF_HDA_SPIB_SPIB;
0894 
0895             hext_stream->fifo_addr = sdev->bar[HDA_DSP_SPIB_BAR] +
0896                 SOF_HDA_SPIB_BASE + SOF_HDA_SPIB_INTERVAL * i +
0897                 SOF_HDA_SPIB_MAXFIFO;
0898         }
0899 
0900         hstream = &hext_stream->hstream;
0901         hstream->bus = bus;
0902         hstream->sd_int_sta_mask = 1 << i;
0903         hstream->index = i;
0904         sd_offset = SOF_STREAM_SD_OFFSET(hstream);
0905         hstream->sd_addr = sdev->bar[HDA_DSP_HDA_BAR] + sd_offset;
0906         hstream->stream_tag = i + 1;
0907         hstream->opened = false;
0908         hstream->running = false;
0909         hstream->direction = SNDRV_PCM_STREAM_CAPTURE;
0910 
0911         /* memory alloc for stream BDL */
0912         ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev,
0913                       HDA_DSP_BDL_SIZE, &hstream->bdl);
0914         if (ret < 0) {
0915             dev_err(sdev->dev, "error: stream bdl dma alloc failed\n");
0916             return -ENOMEM;
0917         }
0918         hstream->posbuf = (__le32 *)(bus->posbuf.area +
0919             (hstream->index) * 8);
0920 
0921         list_add_tail(&hstream->list, &bus->stream_list);
0922     }
0923 
0924     /* create playback streams */
0925     for (i = num_capture; i < num_total; i++) {
0926         struct sof_intel_hda_stream *hda_stream;
0927 
0928         hda_stream = devm_kzalloc(sdev->dev, sizeof(*hda_stream),
0929                       GFP_KERNEL);
0930         if (!hda_stream)
0931             return -ENOMEM;
0932 
0933         hda_stream->sdev = sdev;
0934 
0935         hext_stream = &hda_stream->hext_stream;
0936 
0937         /* we always have DSP support */
0938         hext_stream->pphc_addr = sdev->bar[HDA_DSP_PP_BAR] +
0939             SOF_HDA_PPHC_BASE + SOF_HDA_PPHC_INTERVAL * i;
0940 
0941         hext_stream->pplc_addr = sdev->bar[HDA_DSP_PP_BAR] +
0942             SOF_HDA_PPLC_BASE + SOF_HDA_PPLC_MULTI * num_total +
0943             SOF_HDA_PPLC_INTERVAL * i;
0944 
0945         /* do we support SPIB */
0946         if (sdev->bar[HDA_DSP_SPIB_BAR]) {
0947             hext_stream->spib_addr = sdev->bar[HDA_DSP_SPIB_BAR] +
0948                 SOF_HDA_SPIB_BASE + SOF_HDA_SPIB_INTERVAL * i +
0949                 SOF_HDA_SPIB_SPIB;
0950 
0951             hext_stream->fifo_addr = sdev->bar[HDA_DSP_SPIB_BAR] +
0952                 SOF_HDA_SPIB_BASE + SOF_HDA_SPIB_INTERVAL * i +
0953                 SOF_HDA_SPIB_MAXFIFO;
0954         }
0955 
0956         hstream = &hext_stream->hstream;
0957         hstream->bus = bus;
0958         hstream->sd_int_sta_mask = 1 << i;
0959         hstream->index = i;
0960         sd_offset = SOF_STREAM_SD_OFFSET(hstream);
0961         hstream->sd_addr = sdev->bar[HDA_DSP_HDA_BAR] + sd_offset;
0962         hstream->stream_tag = i - num_capture + 1;
0963         hstream->opened = false;
0964         hstream->running = false;
0965         hstream->direction = SNDRV_PCM_STREAM_PLAYBACK;
0966 
0967         /* mem alloc for stream BDL */
0968         ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev,
0969                       HDA_DSP_BDL_SIZE, &hstream->bdl);
0970         if (ret < 0) {
0971             dev_err(sdev->dev, "error: stream bdl dma alloc failed\n");
0972             return -ENOMEM;
0973         }
0974 
0975         hstream->posbuf = (__le32 *)(bus->posbuf.area +
0976             (hstream->index) * 8);
0977 
0978         list_add_tail(&hstream->list, &bus->stream_list);
0979     }
0980 
0981     /* store total stream count (playback + capture) from GCAP */
0982     sof_hda->stream_max = num_total;
0983 
0984     return 0;
0985 }
0986 
0987 void hda_dsp_stream_free(struct snd_sof_dev *sdev)
0988 {
0989     struct hdac_bus *bus = sof_to_bus(sdev);
0990     struct hdac_stream *s, *_s;
0991     struct hdac_ext_stream *hext_stream;
0992     struct sof_intel_hda_stream *hda_stream;
0993 
0994     /* free position buffer */
0995     if (bus->posbuf.area)
0996         snd_dma_free_pages(&bus->posbuf);
0997 
0998 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
0999     /* free position buffer */
1000     if (bus->rb.area)
1001         snd_dma_free_pages(&bus->rb);
1002 #endif
1003 
1004     list_for_each_entry_safe(s, _s, &bus->stream_list, list) {
1005         /* TODO: decouple */
1006 
1007         /* free bdl buffer */
1008         if (s->bdl.area)
1009             snd_dma_free_pages(&s->bdl);
1010         list_del(&s->list);
1011         hext_stream = stream_to_hdac_ext_stream(s);
1012         hda_stream = container_of(hext_stream, struct sof_intel_hda_stream,
1013                       hext_stream);
1014         devm_kfree(sdev->dev, hda_stream);
1015     }
1016 }
1017 
1018 snd_pcm_uframes_t hda_dsp_stream_get_position(struct hdac_stream *hstream,
1019                           int direction, bool can_sleep)
1020 {
1021     struct hdac_ext_stream *hext_stream = stream_to_hdac_ext_stream(hstream);
1022     struct sof_intel_hda_stream *hda_stream = hstream_to_sof_hda_stream(hext_stream);
1023     struct snd_sof_dev *sdev = hda_stream->sdev;
1024     snd_pcm_uframes_t pos;
1025 
1026     switch (sof_hda_position_quirk) {
1027     case SOF_HDA_POSITION_QUIRK_USE_SKYLAKE_LEGACY:
1028         /*
1029          * This legacy code, inherited from the Skylake driver,
1030          * mixes DPIB registers and DPIB DDR updates and
1031          * does not seem to follow any known hardware recommendations.
1032          * It's not clear e.g. why there is a different flow
1033          * for capture and playback, the only information that matters is
1034          * what traffic class is used, and on all SOF-enabled platforms
1035          * only VC0 is supported so the work-around was likely not necessary
1036          * and quite possibly wrong.
1037          */
1038 
1039         /* DPIB/posbuf position mode:
1040          * For Playback, Use DPIB register from HDA space which
1041          * reflects the actual data transferred.
1042          * For Capture, Use the position buffer for pointer, as DPIB
1043          * is not accurate enough, its update may be completed
1044          * earlier than the data written to DDR.
1045          */
1046         if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
1047             pos = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR,
1048                            AZX_REG_VS_SDXDPIB_XBASE +
1049                            (AZX_REG_VS_SDXDPIB_XINTERVAL *
1050                         hstream->index));
1051         } else {
1052             /*
1053              * For capture stream, we need more workaround to fix the
1054              * position incorrect issue:
1055              *
1056              * 1. Wait at least 20us before reading position buffer after
1057              * the interrupt generated(IOC), to make sure position update
1058              * happens on frame boundary i.e. 20.833uSec for 48KHz.
1059              * 2. Perform a dummy Read to DPIB register to flush DMA
1060              * position value.
1061              * 3. Read the DMA Position from posbuf. Now the readback
1062              * value should be >= period boundary.
1063              */
1064             if (can_sleep)
1065                 usleep_range(20, 21);
1066 
1067             snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR,
1068                      AZX_REG_VS_SDXDPIB_XBASE +
1069                      (AZX_REG_VS_SDXDPIB_XINTERVAL *
1070                       hstream->index));
1071             pos = snd_hdac_stream_get_pos_posbuf(hstream);
1072         }
1073         break;
1074     case SOF_HDA_POSITION_QUIRK_USE_DPIB_REGISTERS:
1075         /*
1076          * In case VC1 traffic is disabled this is the recommended option
1077          */
1078         pos = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR,
1079                        AZX_REG_VS_SDXDPIB_XBASE +
1080                        (AZX_REG_VS_SDXDPIB_XINTERVAL *
1081                     hstream->index));
1082         break;
1083     case SOF_HDA_POSITION_QUIRK_USE_DPIB_DDR_UPDATE:
1084         /*
1085          * This is the recommended option when VC1 is enabled.
1086          * While this isn't needed for SOF platforms it's added for
1087          * consistency and debug.
1088          */
1089         pos = snd_hdac_stream_get_pos_posbuf(hstream);
1090         break;
1091     default:
1092         dev_err_once(sdev->dev, "hda_position_quirk value %d not supported\n",
1093                  sof_hda_position_quirk);
1094         pos = 0;
1095         break;
1096     }
1097 
1098     if (pos >= hstream->bufsize)
1099         pos = 0;
1100 
1101     return pos;
1102 }
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