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0001 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
0002 //
0003 // This file is provided under a dual BSD/GPLv2 license.  When using or
0004 // redistributing this file, you may do so under either license.
0005 //
0006 // Copyright(c) 2018 Intel Corporation. All rights reserved.
0007 //
0008 // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
0009 //      Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
0010 //      Rander Wang <rander.wang@intel.com>
0011 //          Keyon Jie <yang.jie@linux.intel.com>
0012 //
0013 
0014 /*
0015  * Hardware interface for HDA DSP code loader
0016  */
0017 
0018 #include <linux/firmware.h>
0019 #include <sound/hdaudio_ext.h>
0020 #include <sound/hda_register.h>
0021 #include <sound/sof.h>
0022 #include "ext_manifest.h"
0023 #include "../ops.h"
0024 #include "../sof-priv.h"
0025 #include "hda.h"
0026 
0027 static void hda_ssp_set_cbp_cfp(struct snd_sof_dev *sdev)
0028 {
0029     struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
0030     const struct sof_intel_dsp_desc *chip = hda->desc;
0031     int i;
0032 
0033     /* DSP is powered up, set all SSPs to clock consumer/codec provider mode */
0034     for (i = 0; i < chip->ssp_count; i++) {
0035         snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
0036                          chip->ssp_base_offset
0037                          + i * SSP_DEV_MEM_SIZE
0038                          + SSP_SSC1_OFFSET,
0039                          SSP_SET_CBP_CFP,
0040                          SSP_SET_CBP_CFP);
0041     }
0042 }
0043 
0044 struct hdac_ext_stream *hda_cl_stream_prepare(struct snd_sof_dev *sdev, unsigned int format,
0045                           unsigned int size, struct snd_dma_buffer *dmab,
0046                           int direction)
0047 {
0048     struct hdac_ext_stream *hext_stream;
0049     struct hdac_stream *hstream;
0050     struct pci_dev *pci = to_pci_dev(sdev->dev);
0051     int ret;
0052 
0053     hext_stream = hda_dsp_stream_get(sdev, direction, 0);
0054 
0055     if (!hext_stream) {
0056         dev_err(sdev->dev, "error: no stream available\n");
0057         return ERR_PTR(-ENODEV);
0058     }
0059     hstream = &hext_stream->hstream;
0060     hstream->substream = NULL;
0061 
0062     /* allocate DMA buffer */
0063     ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, &pci->dev, size, dmab);
0064     if (ret < 0) {
0065         dev_err(sdev->dev, "error: memory alloc failed: %d\n", ret);
0066         goto out_put;
0067     }
0068 
0069     hstream->period_bytes = 0;/* initialize period_bytes */
0070     hstream->format_val = format;
0071     hstream->bufsize = size;
0072 
0073     if (direction == SNDRV_PCM_STREAM_CAPTURE) {
0074         ret = hda_dsp_iccmax_stream_hw_params(sdev, hext_stream, dmab, NULL);
0075         if (ret < 0) {
0076             dev_err(sdev->dev, "error: iccmax stream prepare failed: %d\n", ret);
0077             goto out_free;
0078         }
0079     } else {
0080         ret = hda_dsp_stream_hw_params(sdev, hext_stream, dmab, NULL);
0081         if (ret < 0) {
0082             dev_err(sdev->dev, "error: hdac prepare failed: %d\n", ret);
0083             goto out_free;
0084         }
0085         hda_dsp_stream_spib_config(sdev, hext_stream, HDA_DSP_SPIB_ENABLE, size);
0086     }
0087 
0088     return hext_stream;
0089 
0090 out_free:
0091     snd_dma_free_pages(dmab);
0092 out_put:
0093     hda_dsp_stream_put(sdev, direction, hstream->stream_tag);
0094     return ERR_PTR(ret);
0095 }
0096 
0097 /*
0098  * first boot sequence has some extra steps.
0099  * power on all host managed cores and only unstall/run the boot core to boot the
0100  * DSP then turn off all non boot cores (if any) is powered on.
0101  */
0102 int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot)
0103 {
0104     struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
0105     const struct sof_intel_dsp_desc *chip = hda->desc;
0106     unsigned int status, target_status;
0107     u32 flags, ipc_hdr, j;
0108     unsigned long mask;
0109     char *dump_msg;
0110     int ret;
0111 
0112     /* step 1: power up corex */
0113     ret = hda_dsp_core_power_up(sdev, chip->host_managed_cores_mask);
0114     if (ret < 0) {
0115         if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
0116             dev_err(sdev->dev, "error: dsp core 0/1 power up failed\n");
0117         goto err;
0118     }
0119 
0120     hda_ssp_set_cbp_cfp(sdev);
0121 
0122     /* step 2: Send ROM_CONTROL command (stream_tag is ignored for IMR boot) */
0123     ipc_hdr = chip->ipc_req_mask | HDA_DSP_ROM_IPC_CONTROL;
0124     if (!imr_boot)
0125         ipc_hdr |= HDA_DSP_ROM_IPC_PURGE_FW | ((stream_tag - 1) << 9);
0126 
0127     snd_sof_dsp_write(sdev, HDA_DSP_BAR, chip->ipc_req, ipc_hdr);
0128 
0129     /* step 3: unset core 0 reset state & unstall/run core 0 */
0130     ret = hda_dsp_core_run(sdev, chip->init_core_mask);
0131     if (ret < 0) {
0132         if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
0133             dev_err(sdev->dev,
0134                 "error: dsp core start failed %d\n", ret);
0135         ret = -EIO;
0136         goto err;
0137     }
0138 
0139     /* step 4: wait for IPC DONE bit from ROM */
0140     ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
0141                         chip->ipc_ack, status,
0142                         ((status & chip->ipc_ack_mask)
0143                             == chip->ipc_ack_mask),
0144                         HDA_DSP_REG_POLL_INTERVAL_US,
0145                         HDA_DSP_INIT_TIMEOUT_US);
0146 
0147     if (ret < 0) {
0148         if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
0149             dev_err(sdev->dev,
0150                 "error: %s: timeout for HIPCIE done\n",
0151                 __func__);
0152         goto err;
0153     }
0154 
0155     /* set DONE bit to clear the reply IPC message */
0156     snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
0157                        chip->ipc_ack,
0158                        chip->ipc_ack_mask,
0159                        chip->ipc_ack_mask);
0160 
0161     /* step 5: power down cores that are no longer needed */
0162     ret = hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask &
0163                        ~(chip->init_core_mask));
0164     if (ret < 0) {
0165         if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
0166             dev_err(sdev->dev,
0167                 "error: dsp core x power down failed\n");
0168         goto err;
0169     }
0170 
0171     /* step 6: enable IPC interrupts */
0172     hda_dsp_ipc_int_enable(sdev);
0173 
0174     /*
0175      * step 7:
0176      * - Cold/Full boot: wait for ROM init to proceed to download the firmware
0177      * - IMR boot: wait for ROM firmware entered (firmware booted up from IMR)
0178      */
0179     if (imr_boot)
0180         target_status = HDA_DSP_ROM_FW_ENTERED;
0181     else
0182         target_status = HDA_DSP_ROM_INIT;
0183 
0184     ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
0185                     chip->rom_status_reg, status,
0186                     ((status & HDA_DSP_ROM_STS_MASK)
0187                         == target_status),
0188                     HDA_DSP_REG_POLL_INTERVAL_US,
0189                     chip->rom_init_timeout *
0190                     USEC_PER_MSEC);
0191     if (!ret) {
0192         /* set enabled cores mask and increment ref count for cores in init_core_mask */
0193         sdev->enabled_cores_mask |= chip->init_core_mask;
0194         mask = sdev->enabled_cores_mask;
0195         for_each_set_bit(j, &mask, SOF_MAX_DSP_NUM_CORES)
0196             sdev->dsp_core_ref_count[j]++;
0197         return 0;
0198     }
0199 
0200     if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
0201         dev_err(sdev->dev,
0202             "%s: timeout with rom_status_reg (%#x) read\n",
0203             __func__, chip->rom_status_reg);
0204 
0205 err:
0206     flags = SOF_DBG_DUMP_PCI | SOF_DBG_DUMP_MBOX | SOF_DBG_DUMP_OPTIONAL;
0207 
0208     /* after max boot attempts make sure that the dump is printed */
0209     if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
0210         flags &= ~SOF_DBG_DUMP_OPTIONAL;
0211 
0212     dump_msg = kasprintf(GFP_KERNEL, "Boot iteration failed: %d/%d",
0213                  hda->boot_iteration, HDA_FW_BOOT_ATTEMPTS);
0214     snd_sof_dsp_dbg_dump(sdev, dump_msg, flags);
0215     hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask);
0216 
0217     kfree(dump_msg);
0218     return ret;
0219 }
0220 
0221 static int cl_trigger(struct snd_sof_dev *sdev,
0222               struct hdac_ext_stream *hext_stream, int cmd)
0223 {
0224     struct hdac_stream *hstream = &hext_stream->hstream;
0225     int sd_offset = SOF_STREAM_SD_OFFSET(hstream);
0226 
0227     /* code loader is special case that reuses stream ops */
0228     switch (cmd) {
0229     case SNDRV_PCM_TRIGGER_START:
0230         snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
0231                     1 << hstream->index,
0232                     1 << hstream->index);
0233 
0234         snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
0235                     sd_offset,
0236                     SOF_HDA_SD_CTL_DMA_START |
0237                     SOF_HDA_CL_DMA_SD_INT_MASK,
0238                     SOF_HDA_SD_CTL_DMA_START |
0239                     SOF_HDA_CL_DMA_SD_INT_MASK);
0240 
0241         hstream->running = true;
0242         return 0;
0243     default:
0244         return hda_dsp_stream_trigger(sdev, hext_stream, cmd);
0245     }
0246 }
0247 
0248 int hda_cl_cleanup(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab,
0249            struct hdac_ext_stream *hext_stream)
0250 {
0251     struct hdac_stream *hstream = &hext_stream->hstream;
0252     int sd_offset = SOF_STREAM_SD_OFFSET(hstream);
0253     int ret = 0;
0254 
0255     if (hstream->direction == SNDRV_PCM_STREAM_PLAYBACK)
0256         ret = hda_dsp_stream_spib_config(sdev, hext_stream, HDA_DSP_SPIB_DISABLE, 0);
0257     else
0258         snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset,
0259                     SOF_HDA_SD_CTL_DMA_START, 0);
0260 
0261     hda_dsp_stream_put(sdev, hstream->direction, hstream->stream_tag);
0262     hstream->running = 0;
0263     hstream->substream = NULL;
0264 
0265     /* reset BDL address */
0266     snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
0267               sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPL, 0);
0268     snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
0269               sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPU, 0);
0270 
0271     snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, sd_offset, 0);
0272     snd_dma_free_pages(dmab);
0273     dmab->area = NULL;
0274     hstream->bufsize = 0;
0275     hstream->format_val = 0;
0276 
0277     return ret;
0278 }
0279 
0280 int hda_cl_copy_fw(struct snd_sof_dev *sdev, struct hdac_ext_stream *hext_stream)
0281 {
0282     struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
0283     const struct sof_intel_dsp_desc *chip = hda->desc;
0284     unsigned int reg;
0285     int ret, status;
0286 
0287     ret = cl_trigger(sdev, hext_stream, SNDRV_PCM_TRIGGER_START);
0288     if (ret < 0) {
0289         dev_err(sdev->dev, "error: DMA trigger start failed\n");
0290         return ret;
0291     }
0292 
0293     status = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
0294                     chip->rom_status_reg, reg,
0295                     ((reg & HDA_DSP_ROM_STS_MASK)
0296                         == HDA_DSP_ROM_FW_ENTERED),
0297                     HDA_DSP_REG_POLL_INTERVAL_US,
0298                     HDA_DSP_BASEFW_TIMEOUT_US);
0299 
0300     /*
0301      * even in case of errors we still need to stop the DMAs,
0302      * but we return the initial error should the DMA stop also fail
0303      */
0304 
0305     if (status < 0) {
0306         dev_err(sdev->dev,
0307             "%s: timeout with rom_status_reg (%#x) read\n",
0308             __func__, chip->rom_status_reg);
0309     }
0310 
0311     ret = cl_trigger(sdev, hext_stream, SNDRV_PCM_TRIGGER_STOP);
0312     if (ret < 0) {
0313         dev_err(sdev->dev, "error: DMA trigger stop failed\n");
0314         if (!status)
0315             status = ret;
0316     }
0317 
0318     return status;
0319 }
0320 
0321 int hda_dsp_cl_boot_firmware_iccmax(struct snd_sof_dev *sdev)
0322 {
0323     struct snd_sof_pdata *plat_data = sdev->pdata;
0324     struct hdac_ext_stream *iccmax_stream;
0325     struct hdac_bus *bus = sof_to_bus(sdev);
0326     struct firmware stripped_firmware;
0327     struct snd_dma_buffer dmab_bdl;
0328     int ret, ret1;
0329     u8 original_gb;
0330 
0331     /* save the original LTRP guardband value */
0332     original_gb = snd_hdac_chip_readb(bus, VS_LTRP) & HDA_VS_INTEL_LTRP_GB_MASK;
0333 
0334     if (plat_data->fw->size <= plat_data->fw_offset) {
0335         dev_err(sdev->dev, "error: firmware size must be greater than firmware offset\n");
0336         return -EINVAL;
0337     }
0338 
0339     stripped_firmware.size = plat_data->fw->size - plat_data->fw_offset;
0340 
0341     /* prepare capture stream for ICCMAX */
0342     iccmax_stream = hda_cl_stream_prepare(sdev, HDA_CL_STREAM_FORMAT, stripped_firmware.size,
0343                           &dmab_bdl, SNDRV_PCM_STREAM_CAPTURE);
0344     if (IS_ERR(iccmax_stream)) {
0345         dev_err(sdev->dev, "error: dma prepare for ICCMAX stream failed\n");
0346         return PTR_ERR(iccmax_stream);
0347     }
0348 
0349     ret = hda_dsp_cl_boot_firmware(sdev);
0350 
0351     /*
0352      * Perform iccmax stream cleanup. This should be done even if firmware loading fails.
0353      * If the cleanup also fails, we return the initial error
0354      */
0355     ret1 = hda_cl_cleanup(sdev, &dmab_bdl, iccmax_stream);
0356     if (ret1 < 0) {
0357         dev_err(sdev->dev, "error: ICCMAX stream cleanup failed\n");
0358 
0359         /* set return value to indicate cleanup failure */
0360         if (!ret)
0361             ret = ret1;
0362     }
0363 
0364     /* restore the original guardband value after FW boot */
0365     snd_hdac_chip_updateb(bus, VS_LTRP, HDA_VS_INTEL_LTRP_GB_MASK, original_gb);
0366 
0367     return ret;
0368 }
0369 
0370 static int hda_dsp_boot_imr(struct snd_sof_dev *sdev)
0371 {
0372     const struct sof_intel_dsp_desc *chip_info;
0373     int ret;
0374 
0375     chip_info = get_chip_info(sdev->pdata);
0376     if (chip_info->cl_init)
0377         ret = chip_info->cl_init(sdev, 0, true);
0378     else
0379         ret = -EINVAL;
0380 
0381     if (!ret)
0382         hda_sdw_process_wakeen(sdev);
0383 
0384     return ret;
0385 }
0386 
0387 int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev)
0388 {
0389     struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
0390     struct snd_sof_pdata *plat_data = sdev->pdata;
0391     const struct sof_dev_desc *desc = plat_data->desc;
0392     const struct sof_intel_dsp_desc *chip_info;
0393     struct hdac_ext_stream *hext_stream;
0394     struct firmware stripped_firmware;
0395     struct snd_dma_buffer dmab;
0396     int ret, ret1, i;
0397 
0398     if (hda->imrboot_supported && !sdev->first_boot && !hda->skip_imr_boot) {
0399         dev_dbg(sdev->dev, "IMR restore supported, booting from IMR directly\n");
0400         hda->boot_iteration = 0;
0401         ret = hda_dsp_boot_imr(sdev);
0402         if (!ret)
0403             return 0;
0404 
0405         dev_warn(sdev->dev, "IMR restore failed, trying to cold boot\n");
0406     }
0407 
0408     chip_info = desc->chip_info;
0409 
0410     if (plat_data->fw->size <= plat_data->fw_offset) {
0411         dev_err(sdev->dev, "error: firmware size must be greater than firmware offset\n");
0412         return -EINVAL;
0413     }
0414 
0415     stripped_firmware.data = plat_data->fw->data + plat_data->fw_offset;
0416     stripped_firmware.size = plat_data->fw->size - plat_data->fw_offset;
0417 
0418     /* init for booting wait */
0419     init_waitqueue_head(&sdev->boot_wait);
0420 
0421     /* prepare DMA for code loader stream */
0422     hext_stream = hda_cl_stream_prepare(sdev, HDA_CL_STREAM_FORMAT,
0423                         stripped_firmware.size,
0424                         &dmab, SNDRV_PCM_STREAM_PLAYBACK);
0425     if (IS_ERR(hext_stream)) {
0426         dev_err(sdev->dev, "error: dma prepare for fw loading failed\n");
0427         return PTR_ERR(hext_stream);
0428     }
0429 
0430     memcpy(dmab.area, stripped_firmware.data,
0431            stripped_firmware.size);
0432 
0433     /* try ROM init a few times before giving up */
0434     for (i = 0; i < HDA_FW_BOOT_ATTEMPTS; i++) {
0435         dev_dbg(sdev->dev,
0436             "Attempting iteration %d of Core En/ROM load...\n", i);
0437 
0438         hda->boot_iteration = i + 1;
0439         if (chip_info->cl_init)
0440             ret = chip_info->cl_init(sdev, hext_stream->hstream.stream_tag, false);
0441         else
0442             ret = -EINVAL;
0443 
0444         /* don't retry anymore if successful */
0445         if (!ret)
0446             break;
0447     }
0448 
0449     if (i == HDA_FW_BOOT_ATTEMPTS) {
0450         dev_err(sdev->dev, "error: dsp init failed after %d attempts with err: %d\n",
0451             i, ret);
0452         goto cleanup;
0453     }
0454 
0455     /*
0456      * When a SoundWire link is in clock stop state, a Slave
0457      * device may trigger in-band wakes for events such as jack
0458      * insertion or acoustic event detection. This event will lead
0459      * to a WAKEEN interrupt, handled by the PCI device and routed
0460      * to PME if the PCI device is in D3. The resume function in
0461      * audio PCI driver will be invoked by ACPI for PME event and
0462      * initialize the device and process WAKEEN interrupt.
0463      *
0464      * The WAKEEN interrupt should be processed ASAP to prevent an
0465      * interrupt flood, otherwise other interrupts, such IPC,
0466      * cannot work normally.  The WAKEEN is handled after the ROM
0467      * is initialized successfully, which ensures power rails are
0468      * enabled before accessing the SoundWire SHIM registers
0469      */
0470     if (!sdev->first_boot)
0471         hda_sdw_process_wakeen(sdev);
0472 
0473     /*
0474      * Set the boot_iteration to the last attempt, indicating that the
0475      * DSP ROM has been initialized and from this point there will be no
0476      * retry done to boot.
0477      *
0478      * Continue with code loading and firmware boot
0479      */
0480     hda->boot_iteration = HDA_FW_BOOT_ATTEMPTS;
0481     ret = hda_cl_copy_fw(sdev, hext_stream);
0482     if (!ret) {
0483         dev_dbg(sdev->dev, "Firmware download successful, booting...\n");
0484         hda->skip_imr_boot = false;
0485     } else {
0486         snd_sof_dsp_dbg_dump(sdev, "Firmware download failed",
0487                      SOF_DBG_DUMP_PCI | SOF_DBG_DUMP_MBOX);
0488         hda->skip_imr_boot = true;
0489     }
0490 
0491 cleanup:
0492     /*
0493      * Perform codeloader stream cleanup.
0494      * This should be done even if firmware loading fails.
0495      * If the cleanup also fails, we return the initial error
0496      */
0497     ret1 = hda_cl_cleanup(sdev, &dmab, hext_stream);
0498     if (ret1 < 0) {
0499         dev_err(sdev->dev, "error: Code loader DSP cleanup failed\n");
0500 
0501         /* set return value to indicate cleanup failure */
0502         if (!ret)
0503             ret = ret1;
0504     }
0505 
0506     /*
0507      * return primary core id if both fw copy
0508      * and stream clean up are successful
0509      */
0510     if (!ret)
0511         return chip_info->init_core_mask;
0512 
0513     /* disable DSP */
0514     snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR,
0515                 SOF_HDA_REG_PP_PPCTL,
0516                 SOF_HDA_PPCTL_GPROCEN, 0);
0517     return ret;
0518 }
0519 
0520 /* pre fw run operations */
0521 int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev)
0522 {
0523     /* disable clock gating and power gating */
0524     return hda_dsp_ctrl_clock_power_gating(sdev, false);
0525 }
0526 
0527 /* post fw run operations */
0528 int hda_dsp_post_fw_run(struct snd_sof_dev *sdev)
0529 {
0530     int ret;
0531 
0532     if (sdev->first_boot) {
0533         struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
0534 
0535         ret = hda_sdw_startup(sdev);
0536         if (ret < 0) {
0537             dev_err(sdev->dev,
0538                 "error: could not startup SoundWire links\n");
0539             return ret;
0540         }
0541 
0542         /* Check if IMR boot is usable */
0543         if (!sof_debug_check_flag(SOF_DBG_IGNORE_D3_PERSISTENT) &&
0544             (sdev->fw_ready.flags & SOF_IPC_INFO_D3_PERSISTENT ||
0545              sdev->pdata->ipc_type == SOF_INTEL_IPC4))
0546             hdev->imrboot_supported = true;
0547     }
0548 
0549     hda_sdw_int_enable(sdev, true);
0550 
0551     /* re-enable clock gating and power gating */
0552     return hda_dsp_ctrl_clock_power_gating(sdev, true);
0553 }
0554 
0555 int hda_dsp_ext_man_get_cavs_config_data(struct snd_sof_dev *sdev,
0556                      const struct sof_ext_man_elem_header *hdr)
0557 {
0558     const struct sof_ext_man_cavs_config_data *config_data =
0559         container_of(hdr, struct sof_ext_man_cavs_config_data, hdr);
0560     struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
0561     int i, elem_num;
0562 
0563     /* calculate total number of config data elements */
0564     elem_num = (hdr->size - sizeof(struct sof_ext_man_elem_header))
0565            / sizeof(struct sof_config_elem);
0566     if (elem_num <= 0) {
0567         dev_err(sdev->dev, "cavs config data is inconsistent: %d\n", elem_num);
0568         return -EINVAL;
0569     }
0570 
0571     for (i = 0; i < elem_num; i++)
0572         switch (config_data->elems[i].token) {
0573         case SOF_EXT_MAN_CAVS_CONFIG_EMPTY:
0574             /* skip empty token */
0575             break;
0576         case SOF_EXT_MAN_CAVS_CONFIG_CAVS_LPRO:
0577             hda->clk_config_lpro = config_data->elems[i].value;
0578             dev_dbg(sdev->dev, "FW clock config: %s\n",
0579                 hda->clk_config_lpro ? "LPRO" : "HPRO");
0580             break;
0581         case SOF_EXT_MAN_CAVS_CONFIG_OUTBOX_SIZE:
0582         case SOF_EXT_MAN_CAVS_CONFIG_INBOX_SIZE:
0583             /* These elements are defined but not being used yet. No warn is required */
0584             break;
0585         default:
0586             dev_info(sdev->dev, "unsupported token type: %d\n",
0587                  config_data->elems[i].token);
0588         }
0589 
0590     return 0;
0591 }
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