sof/intel/hda-ipc.h

0001 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
0002 /*
0003  * This file is provided under a dual BSD/GPLv2 license.  When using or
0004  * redistributing this file, you may do so under either license.
0005  *
0006  * Copyright(c) 2019 Intel Corporation. All rights reserved.
0007  *
0008  * Author: Keyon Jie <yang.jie@linux.intel.com>
0009  */
0010
0011 #ifndef __SOF_INTEL_HDA_IPC_H
0012 #define __SOF_INTEL_HDA_IPC_H
0013
0014 /*
0015  * Primary register, mapped to
0016  * - DIPCTDR (HIPCIDR) in sideband IPC (cAVS 1.8+)
0017  * - DIPCT in cAVS 1.5 IPC
0018  *
0019  * Secondary register, mapped to:
0020  * - DIPCTDD (HIPCIDD) in sideband IPC (cAVS 1.8+)
0021  * - DIPCTE in cAVS 1.5 IPC
0022  */
0023
0024 /* Common bits in primary register */
0025
0026 /* Reserved for doorbell */
0027 #define HDA_IPC_RSVD_31     BIT(31)
0028 /* Target, 0 - normal message, 1 - compact message(cAVS compatible) */
0029 #define HDA_IPC_MSG_COMPACT BIT(30)
0030 /* Direction, 0 - request, 1 - response */
0031 #define HDA_IPC_RSP     BIT(29)
0032
0033 #define HDA_IPC_TYPE_SHIFT  24
0034 #define HDA_IPC_TYPE_MASK   GENMASK(28, 24)
0035 #define HDA_IPC_TYPE(x)     ((x) << HDA_IPC_TYPE_SHIFT)
0036
0037 #define HDA_IPC_PM_GATE     HDA_IPC_TYPE(0x8U)
0038
0039 /* Command specific payload bits in secondary register */
0040
0041 /* Disable DMA tracing (0 - keep tracing, 1 - to disable DMA trace) */
0042 #define HDA_PM_NO_DMA_TRACE BIT(4)
0043 /* Prevent clock gating (0 - cg allowed, 1 - DSP clock always on) */
0044 #define HDA_PM_PCG      BIT(3)
0045 /* Prevent power gating (0 - deep power state transitions allowed) */
0046 #define HDA_PM_PPG      BIT(2)
0047 /* Indicates whether streaming is active */
0048 #define HDA_PM_PG_STREAMING BIT(1)
0049 #define HDA_PM_PG_RSVD      BIT(0)
0050
0051 irqreturn_t cnl_ipc_irq_thread(int irq, void *context);
0052 int cnl_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg);
0053 void cnl_ipc_dump(struct snd_sof_dev *sdev);
0054
0055 #endif