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0011 #ifndef __SOF_INTEL_ATOM_H
0012 #define __SOF_INTEL_ATOM_H
0013
0014
0015 #define IRAM_OFFSET 0x0C0000
0016 #define IRAM_SIZE (80 * 1024)
0017 #define DRAM_OFFSET 0x100000
0018 #define DRAM_SIZE (160 * 1024)
0019 #define SHIM_OFFSET 0x140000
0020 #define SHIM_SIZE_BYT 0x100
0021 #define SHIM_SIZE_CHT 0x118
0022 #define MBOX_OFFSET 0x144000
0023 #define MBOX_SIZE 0x1000
0024 #define EXCEPT_OFFSET 0x800
0025 #define EXCEPT_MAX_HDR_SIZE 0x400
0026
0027
0028 #define DMAC0_OFFSET 0x098000
0029 #define DMAC1_OFFSET 0x09c000
0030 #define DMAC2_OFFSET 0x094000
0031 #define DMAC_SIZE 0x420
0032 #define SSP0_OFFSET 0x0a0000
0033 #define SSP1_OFFSET 0x0a1000
0034 #define SSP2_OFFSET 0x0a2000
0035 #define SSP3_OFFSET 0x0a4000
0036 #define SSP4_OFFSET 0x0a5000
0037 #define SSP5_OFFSET 0x0a6000
0038 #define SSP_SIZE 0x100
0039
0040 #define STACK_DUMP_SIZE 32
0041
0042 #define PCI_BAR_SIZE 0x200000
0043
0044 #define PANIC_OFFSET(x) (((x) & GENMASK_ULL(47, 32)) >> 32)
0045
0046
0047
0048
0049
0050 #define MBOX_DUMP_SIZE 0x30
0051
0052
0053 #define DSP_BAR 0
0054 #define PCI_BAR 1
0055 #define IMR_BAR 2
0056
0057 irqreturn_t atom_irq_handler(int irq, void *context);
0058 irqreturn_t atom_irq_thread(int irq, void *context);
0059
0060 int atom_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg);
0061 int atom_get_mailbox_offset(struct snd_sof_dev *sdev);
0062 int atom_get_window_offset(struct snd_sof_dev *sdev, u32 id);
0063
0064 int atom_run(struct snd_sof_dev *sdev);
0065 int atom_reset(struct snd_sof_dev *sdev);
0066 void atom_dump(struct snd_sof_dev *sdev, u32 flags);
0067
0068 struct snd_soc_acpi_mach *atom_machine_select(struct snd_sof_dev *sdev);
0069 void atom_set_mach_params(struct snd_soc_acpi_mach *mach,
0070 struct snd_sof_dev *sdev);
0071
0072 extern struct snd_soc_dai_driver atom_dai[];
0073
0074 #endif