sof/amd/acp.h

0001 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
0002 /*
0003  * This file is provided under a dual BSD/GPLv2 license. When using or
0004  * redistributing this file, you may do so under either license.
0005  *
0006  * Copyright(c) 2021 Advanced Micro Devices, Inc. All rights reserved.
0007  *
0008  * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
0009  */
0010
0011 #ifndef __SOF_AMD_ACP_H
0012 #define __SOF_AMD_ACP_H
0013
0014 #include "../sof-priv.h"
0015
0016 #define ACP_MAX_STREAM  8
0017
0018 #define ACP_DSP_BAR 0
0019
0020 #define ACP_HW_SEM_RETRY_COUNT          10000
0021 #define ACP_REG_POLL_INTERVAL                   500
0022 #define ACP_REG_POLL_TIMEOUT_US                 2000
0023 #define ACP_DMA_COMPLETE_TIMEOUT_US     5000
0024
0025 #define ACP_PGFSM_CNTL_POWER_ON_MASK        0x01
0026 #define ACP_PGFSM_STATUS_MASK           0x03
0027 #define ACP_POWERED_ON              0x00
0028 #define ACP_ASSERT_RESET            0x01
0029 #define ACP_RELEASE_RESET           0x00
0030 #define ACP_SOFT_RESET_DONE_MASK        0x00010001
0031
0032 #define ACP_DSP_INTR_EN_MASK            0x00000001
0033 #define ACP_SRAM_PTE_OFFSET         0x02050000
0034 #define PAGE_SIZE_4K_ENABLE         0x2
0035 #define ACP_PAGE_SIZE               0x1000
0036 #define ACP_DMA_CH_RUN              0x02
0037 #define ACP_MAX_DESC_CNT            0x02
0038 #define DSP_FW_RUN_ENABLE           0x01
0039 #define ACP_SHA_RUN             0x01
0040 #define ACP_SHA_RESET               0x02
0041 #define ACP_DMA_CH_RST              0x01
0042 #define ACP_DMA_CH_GRACEFUL_RST_EN      0x10
0043 #define ACP_ATU_CACHE_INVALID           0x01
0044 #define ACP_MAX_DESC                128
0045 #define ACPBUS_REG_BASE_OFFSET          ACP_DMA_CNTL_0
0046
0047 #define ACP_DEFAULT_DRAM_LENGTH         0x00080000
0048 #define ACP_SCRATCH_MEMORY_ADDRESS      0x02050000
0049 #define ACP_SYSTEM_MEMORY_WINDOW        0x4000000
0050 #define ACP_IRAM_BASE_ADDRESS           0x000000
0051 #define ACP_DATA_RAM_BASE_ADDRESS       0x01000000
0052 #define ACP_DRAM_PAGE_COUNT         128
0053
0054 #define ACP_DSP_TO_HOST_IRQ         0x04
0055
0056 #define HOST_BRIDGE_CZN             0x1630
0057 #define ACP_SHA_STAT                0x8000
0058 #define ACP_PSP_TIMEOUT_COUNTER         5
0059 #define ACP_EXT_INTR_ERROR_STAT         0x20000000
0060 #define MP0_C2PMSG_114_REG          0x3810AC8
0061 #define MP0_C2PMSG_73_REG           0x3810A24
0062 #define MBOX_ACP_SHA_DMA_COMMAND        0x70000
0063 #define MBOX_DELAY              1000
0064 #define MBOX_READY_MASK             0x80000000
0065 #define MBOX_STATUS_MASK            0xFFFF
0066
0067 struct  acp_atu_grp_pte {
0068     u32 low;
0069     u32 high;
0070 };
0071
0072 union dma_tx_cnt {
0073     struct {
0074         unsigned int count : 19;
0075         unsigned int reserved : 12;
0076         unsigned ioc : 1;
0077     } bitfields, bits;
0078     unsigned int u32_all;
0079     signed int i32_all;
0080 };
0081
0082 struct dma_descriptor {
0083     unsigned int src_addr;
0084     unsigned int dest_addr;
0085     union dma_tx_cnt tx_cnt;
0086     unsigned int reserved;
0087 };
0088
0089 /* Scratch memory structure for communication b/w host and dsp */
0090 struct  scratch_ipc_conf {
0091     /* DSP mailbox */
0092     u8 sof_out_box[512];
0093     /* Host mailbox */
0094     u8 sof_in_box[512];
0095     /* Debug memory */
0096     u8 sof_debug_box[1024];
0097     /* Exception memory*/
0098     u8 sof_except_box[1024];
0099     /* Stream buffer */
0100     u8 sof_stream_box[1024];
0101     /* Trace buffer */
0102     u8 sof_trace_box[1024];
0103     /* Host msg flag */
0104     u32 sof_host_msg_write;
0105     /* Host ack flag*/
0106     u32 sof_host_ack_write;
0107     /* DSP msg flag */
0108     u32 sof_dsp_msg_write;
0109     /* Dsp ack flag */
0110     u32 sof_dsp_ack_write;
0111 };
0112
0113 struct  scratch_reg_conf {
0114     struct scratch_ipc_conf info;
0115     struct acp_atu_grp_pte grp1_pte[16];
0116     struct acp_atu_grp_pte grp2_pte[16];
0117     struct acp_atu_grp_pte grp3_pte[16];
0118     struct acp_atu_grp_pte grp4_pte[16];
0119     struct acp_atu_grp_pte grp5_pte[16];
0120     struct acp_atu_grp_pte grp6_pte[16];
0121     struct acp_atu_grp_pte grp7_pte[16];
0122     struct acp_atu_grp_pte grp8_pte[16];
0123     struct dma_descriptor dma_desc[64];
0124     unsigned int reg_offset[8];
0125     unsigned int buf_size[8];
0126     u8 acp_tx_fifo_buf[256];
0127     u8 acp_rx_fifo_buf[256];
0128     unsigned int    reserve[];
0129 };
0130
0131 struct acp_dsp_stream {
0132     struct list_head list;
0133     struct snd_sof_dev *sdev;
0134     struct snd_pcm_substream *substream;
0135     struct snd_dma_buffer *dmab;
0136     int num_pages;
0137     int stream_tag;
0138     int active;
0139     unsigned int reg_offset;
0140 };
0141
0142 /* Common device data struct for ACP devices */
0143 struct acp_dev_data {
0144     struct snd_sof_dev  *dev;
0145     unsigned int fw_bin_size;
0146     unsigned int fw_data_bin_size;
0147     u32 fw_bin_page_count;
0148     dma_addr_t sha_dma_addr;
0149     u8 *bin_buf;
0150     dma_addr_t dma_addr;
0151     u8 *data_buf;
0152     struct dma_descriptor dscr_info[ACP_MAX_DESC];
0153     struct acp_dsp_stream stream_buf[ACP_MAX_STREAM];
0154     struct acp_dsp_stream *dtrace_stream;
0155     struct pci_dev *smn_dev;
0156 };
0157
0158 void memcpy_to_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *src, size_t bytes);
0159 void memcpy_from_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *dst, size_t bytes);
0160
0161 int acp_dma_status(struct acp_dev_data *adata, unsigned char ch);
0162 int configure_and_run_dma(struct acp_dev_data *adata, unsigned int src_addr,
0163               unsigned int dest_addr, int dsp_data_size);
0164 int configure_and_run_sha_dma(struct acp_dev_data *adata, void *image_addr,
0165                   unsigned int start_addr, unsigned int dest_addr,
0166                   unsigned int image_length);
0167
0168 /* ACP device probe/remove */
0169 int amd_sof_acp_probe(struct snd_sof_dev *sdev);
0170 int amd_sof_acp_remove(struct snd_sof_dev *sdev);
0171
0172 /* DSP Loader callbacks */
0173 int acp_sof_dsp_run(struct snd_sof_dev *sdev);
0174 int acp_dsp_pre_fw_run(struct snd_sof_dev *sdev);
0175 int acp_get_bar_index(struct snd_sof_dev *sdev, u32 type);
0176
0177 /* Block IO callbacks */
0178 int acp_dsp_block_write(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_type,
0179             u32 offset, void *src, size_t size);
0180 int acp_dsp_block_read(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_type,
0181                u32 offset, void *dest, size_t size);
0182
0183 /* IPC callbacks */
0184 irqreturn_t acp_sof_ipc_irq_thread(int irq, void *context);
0185 int acp_sof_ipc_msg_data(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream,
0186              void *p, size_t sz);
0187 int acp_sof_ipc_send_msg(struct snd_sof_dev *sdev,
0188              struct snd_sof_ipc_msg *msg);
0189 int acp_sof_ipc_get_mailbox_offset(struct snd_sof_dev *sdev);
0190 int acp_sof_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id);
0191 void acp_mailbox_write(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes);
0192 void acp_mailbox_read(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes);
0193
0194 /* ACP - DSP  stream callbacks */
0195 int acp_dsp_stream_config(struct snd_sof_dev *sdev, struct acp_dsp_stream *stream);
0196 int acp_dsp_stream_init(struct snd_sof_dev *sdev);
0197 struct acp_dsp_stream *acp_dsp_stream_get(struct snd_sof_dev *sdev, int tag);
0198 int acp_dsp_stream_put(struct snd_sof_dev *sdev, struct acp_dsp_stream *acp_stream);
0199
0200 /*
0201  * DSP PCM Operations.
0202  */
0203 int acp_pcm_open(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream);
0204 int acp_pcm_close(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream);
0205 int acp_pcm_hw_params(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream,
0206               struct snd_pcm_hw_params *params,
0207               struct snd_sof_platform_stream_params *platform_params);
0208
0209 extern struct snd_sof_dsp_ops sof_renoir_ops;
0210
0211 /* Machine configuration */
0212 int snd_amd_acp_find_config(struct pci_dev *pci);
0213
0214 /* Trace */
0215 int acp_sof_trace_init(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab,
0216                struct sof_ipc_dma_trace_params_ext *dtrace_params);
0217 int acp_sof_trace_release(struct snd_sof_dev *sdev);
0218
0219 /* PM Callbacks */
0220 int amd_sof_acp_suspend(struct snd_sof_dev *sdev, u32 target_state);
0221 int amd_sof_acp_resume(struct snd_sof_dev *sdev);
0222
0223 struct sof_amd_acp_desc {
0224     unsigned int host_bridge_id;
0225 };
0226
0227 static inline const struct sof_amd_acp_desc *get_chip_info(struct snd_sof_pdata *pdata)
0228 {
0229     const struct sof_dev_desc *desc = pdata->desc;
0230
0231     return desc->chip_info;
0232 }
0233 #endif