sof/amd/acp-loader.c

0001 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
0002 //
0003 // This file is provided under a dual BSD/GPLv2 license. When using or
0004 // redistributing this file, you may do so under either license.
0005 //
0006 // Copyright(c) 2021 Advanced Micro Devices, Inc.
0007 //
0008 // Authors: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
0009
0010 /*
0011  * Hardware interface for ACP DSP Firmware binaries loader
0012  */
0013
0014 #include <linux/firmware.h>
0015 #include <linux/module.h>
0016 #include <linux/pci.h>
0017
0018 #include "../ops.h"
0019 #include "acp-dsp-offset.h"
0020 #include "acp.h"
0021
0022 #define FW_BIN      0
0023 #define FW_DATA_BIN 1
0024
0025 #define FW_BIN_PTE_OFFSET   0x00
0026 #define FW_DATA_BIN_PTE_OFFSET  0x08
0027
0028 #define ACP_DSP_RUN 0x00
0029
0030 int acp_dsp_block_read(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_type,
0031                u32 offset, void *dest, size_t size)
0032 {
0033     switch (blk_type) {
0034     case SOF_FW_BLK_TYPE_SRAM:
0035         offset = offset - ACP_SCRATCH_MEMORY_ADDRESS;
0036         memcpy_from_scratch(sdev, offset, dest, size);
0037         break;
0038     default:
0039         dev_err(sdev->dev, "bad blk type 0x%x\n", blk_type);
0040         return -EINVAL;
0041     }
0042
0043     return 0;
0044 }
0045 EXPORT_SYMBOL_NS(acp_dsp_block_read, SND_SOC_SOF_AMD_COMMON);
0046
0047 int acp_dsp_block_write(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_type,
0048             u32 offset, void *src, size_t size)
0049 {
0050     struct snd_sof_pdata *plat_data = sdev->pdata;
0051     struct pci_dev *pci = to_pci_dev(sdev->dev);
0052     struct acp_dev_data *adata;
0053     void *dest;
0054     u32 dma_size, page_count;
0055     unsigned int size_fw;
0056
0057     adata = sdev->pdata->hw_pdata;
0058
0059     switch (blk_type) {
0060     case SOF_FW_BLK_TYPE_IRAM:
0061         if (!adata->bin_buf) {
0062             size_fw = plat_data->fw->size;
0063             page_count = PAGE_ALIGN(size_fw) >> PAGE_SHIFT;
0064             dma_size = page_count * ACP_PAGE_SIZE;
0065             adata->bin_buf = dma_alloc_coherent(&pci->dev, dma_size,
0066                                 &adata->sha_dma_addr,
0067                                 GFP_ATOMIC);
0068             if (!adata->bin_buf)
0069                 return -ENOMEM;
0070         }
0071         adata->fw_bin_size = size + offset;
0072         dest = adata->bin_buf + offset;
0073         break;
0074     case SOF_FW_BLK_TYPE_DRAM:
0075         if (!adata->data_buf) {
0076             adata->data_buf = dma_alloc_coherent(&pci->dev,
0077                                  ACP_DEFAULT_DRAM_LENGTH,
0078                                  &adata->dma_addr,
0079                                  GFP_ATOMIC);
0080             if (!adata->data_buf)
0081                 return -ENOMEM;
0082         }
0083         dest = adata->data_buf + offset;
0084         adata->fw_data_bin_size = size + offset;
0085         break;
0086     case SOF_FW_BLK_TYPE_SRAM:
0087         offset = offset - ACP_SCRATCH_MEMORY_ADDRESS;
0088         memcpy_to_scratch(sdev, offset, src, size);
0089         return 0;
0090     default:
0091         dev_err(sdev->dev, "bad blk type 0x%x\n", blk_type);
0092         return -EINVAL;
0093     }
0094
0095     memcpy(dest, src, size);
0096     return 0;
0097 }
0098 EXPORT_SYMBOL_NS(acp_dsp_block_write, SND_SOC_SOF_AMD_COMMON);
0099
0100 int acp_get_bar_index(struct snd_sof_dev *sdev, u32 type)
0101 {
0102     return type;
0103 }
0104 EXPORT_SYMBOL_NS(acp_get_bar_index, SND_SOC_SOF_AMD_COMMON);
0105
0106 static void configure_pte_for_fw_loading(int type, int num_pages, struct acp_dev_data *adata)
0107 {
0108     struct snd_sof_dev *sdev;
0109     unsigned int low, high;
0110     dma_addr_t addr;
0111     u16 page_idx;
0112     u32 offset;
0113
0114     sdev = adata->dev;
0115
0116     switch (type) {
0117     case FW_BIN:
0118         offset = FW_BIN_PTE_OFFSET;
0119         addr = adata->sha_dma_addr;
0120         break;
0121     case FW_DATA_BIN:
0122         offset = adata->fw_bin_page_count * 8;
0123         addr = adata->dma_addr;
0124         break;
0125     default:
0126         dev_err(sdev->dev, "Invalid data type %x\n", type);
0127         return;
0128     }
0129
0130     /* Group Enable */
0131     snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACPAXI2AXI_ATU_BASE_ADDR_GRP_1,
0132               ACP_SRAM_PTE_OFFSET | BIT(31));
0133     snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1,
0134               PAGE_SIZE_4K_ENABLE);
0135
0136     for (page_idx = 0; page_idx < num_pages; page_idx++) {
0137         low = lower_32_bits(addr);
0138         high = upper_32_bits(addr);
0139         snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + offset, low);
0140         high |= BIT(31);
0141         snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + offset + 4, high);
0142         offset += 8;
0143         addr += PAGE_SIZE;
0144     }
0145
0146     /* Flush ATU Cache after PTE Update */
0147     snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACPAXI2AXI_ATU_CTRL, ACP_ATU_CACHE_INVALID);
0148 }
0149
0150 /* pre fw run operations */
0151 int acp_dsp_pre_fw_run(struct snd_sof_dev *sdev)
0152 {
0153     struct pci_dev *pci = to_pci_dev(sdev->dev);
0154     struct snd_sof_pdata *plat_data = sdev->pdata;
0155     struct acp_dev_data *adata;
0156     unsigned int src_addr, size_fw;
0157     u32 page_count, dma_size;
0158     int ret;
0159
0160     adata = sdev->pdata->hw_pdata;
0161     size_fw = adata->fw_bin_size;
0162
0163     page_count = PAGE_ALIGN(size_fw) >> PAGE_SHIFT;
0164     adata->fw_bin_page_count = page_count;
0165
0166     configure_pte_for_fw_loading(FW_BIN, page_count, adata);
0167     ret = configure_and_run_sha_dma(adata, adata->bin_buf, ACP_SYSTEM_MEMORY_WINDOW,
0168                     ACP_IRAM_BASE_ADDRESS, size_fw);
0169     if (ret < 0) {
0170         dev_err(sdev->dev, "SHA DMA transfer failed status: %d\n", ret);
0171         return ret;
0172     }
0173     configure_pte_for_fw_loading(FW_DATA_BIN, ACP_DRAM_PAGE_COUNT, adata);
0174
0175     src_addr = ACP_SYSTEM_MEMORY_WINDOW + page_count * ACP_PAGE_SIZE;
0176     ret = configure_and_run_dma(adata, src_addr, ACP_DATA_RAM_BASE_ADDRESS,
0177                     adata->fw_data_bin_size);
0178     if (ret < 0) {
0179         dev_err(sdev->dev, "acp dma configuration failed: %d\n", ret);
0180         return ret;
0181     }
0182
0183     ret = acp_dma_status(adata, 0);
0184     if (ret < 0)
0185         dev_err(sdev->dev, "acp dma transfer status: %d\n", ret);
0186
0187     /* Free memory once DMA is complete */
0188     dma_size =  (PAGE_ALIGN(plat_data->fw->size) >> PAGE_SHIFT) * ACP_PAGE_SIZE;
0189     dma_free_coherent(&pci->dev, dma_size, adata->bin_buf, adata->sha_dma_addr);
0190     dma_free_coherent(&pci->dev, ACP_DEFAULT_DRAM_LENGTH, adata->data_buf, adata->dma_addr);
0191     adata->bin_buf = NULL;
0192     adata->data_buf = NULL;
0193
0194     return ret;
0195 }
0196 EXPORT_SYMBOL_NS(acp_dsp_pre_fw_run, SND_SOC_SOF_AMD_COMMON);
0197
0198 int acp_sof_dsp_run(struct snd_sof_dev *sdev)
0199 {
0200     int val;
0201
0202     snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DSP0_RUNSTALL, ACP_DSP_RUN);
0203     val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_DSP0_RUNSTALL);
0204     dev_dbg(sdev->dev, "ACP_DSP0_RUNSTALL : 0x%0x\n", val);
0205
0206     return 0;
0207 }
0208 EXPORT_SYMBOL_NS(acp_sof_dsp_run, SND_SOC_SOF_AMD_COMMON);