sof/amd/acp-ipc.c

0001 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
0002 //
0003 // This file is provided under a dual BSD/GPLv2 license. When using or
0004 // redistributing this file, you may do so under either license.
0005 //
0006 // Copyright(c) 2021 Advanced Micro Devices, Inc.
0007 //
0008 // Authors: Balakishore Pati <Balakishore.pati@amd.com>
0009 //      Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
0010
0011 /* ACP-specific SOF IPC code */
0012
0013 #include <linux/module.h>
0014 #include "../ops.h"
0015 #include "acp.h"
0016 #include "acp-dsp-offset.h"
0017
0018 void acp_mailbox_write(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes)
0019 {
0020     memcpy_to_scratch(sdev, offset, message, bytes);
0021 }
0022 EXPORT_SYMBOL_NS(acp_mailbox_write, SND_SOC_SOF_AMD_COMMON);
0023
0024 void acp_mailbox_read(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes)
0025 {
0026     memcpy_from_scratch(sdev, offset, message, bytes);
0027 }
0028 EXPORT_SYMBOL_NS(acp_mailbox_read, SND_SOC_SOF_AMD_COMMON);
0029
0030 static void acpbus_trigger_host_to_dsp_swintr(struct acp_dev_data *adata)
0031 {
0032     struct snd_sof_dev *sdev = adata->dev;
0033     u32 swintr_trigger;
0034
0035     swintr_trigger = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SW_INTR_TRIG);
0036     swintr_trigger |= 0x01;
0037     snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SW_INTR_TRIG, swintr_trigger);
0038 }
0039
0040 static void acp_ipc_host_msg_set(struct snd_sof_dev *sdev)
0041 {
0042     unsigned int host_msg = offsetof(struct scratch_ipc_conf, sof_host_msg_write);
0043
0044     snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + host_msg, 1);
0045 }
0046
0047 static void acp_dsp_ipc_host_done(struct snd_sof_dev *sdev)
0048 {
0049     unsigned int dsp_msg = offsetof(struct scratch_ipc_conf, sof_dsp_msg_write);
0050
0051     snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + dsp_msg, 0);
0052 }
0053
0054 static void acp_dsp_ipc_dsp_done(struct snd_sof_dev *sdev)
0055 {
0056     unsigned int dsp_ack = offsetof(struct scratch_ipc_conf, sof_dsp_ack_write);
0057
0058     snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + dsp_ack, 0);
0059 }
0060
0061 int acp_sof_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
0062 {
0063     struct acp_dev_data *adata = sdev->pdata->hw_pdata;
0064     unsigned int offset = offsetof(struct scratch_ipc_conf, sof_in_box);
0065     unsigned int count = ACP_HW_SEM_RETRY_COUNT;
0066
0067     while (snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_AXI2DAGB_SEM_0)) {
0068         /* Wait until acquired HW Semaphore Lock or timeout*/
0069         count--;
0070         if (!count) {
0071             dev_err(sdev->dev, "%s: Failed to acquire HW lock\n", __func__);
0072             return -EINVAL;
0073         }
0074     }
0075
0076     acp_mailbox_write(sdev, offset, msg->msg_data, msg->msg_size);
0077     acp_ipc_host_msg_set(sdev);
0078
0079     /* Trigger host to dsp interrupt for the msg */
0080     acpbus_trigger_host_to_dsp_swintr(adata);
0081
0082     /* Unlock or Release HW Semaphore */
0083     snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_AXI2DAGB_SEM_0, 0x0);
0084
0085     return 0;
0086 }
0087 EXPORT_SYMBOL_NS(acp_sof_ipc_send_msg, SND_SOC_SOF_AMD_COMMON);
0088
0089 static void acp_dsp_ipc_get_reply(struct snd_sof_dev *sdev)
0090 {
0091     struct snd_sof_ipc_msg *msg = sdev->msg;
0092     struct sof_ipc_reply reply;
0093     struct sof_ipc_cmd_hdr *hdr;
0094     unsigned int offset = offsetof(struct scratch_ipc_conf, sof_in_box);
0095     int ret = 0;
0096
0097        /*
0098     * Sometimes, there is unexpected reply ipc arriving. The reply
0099     * ipc belongs to none of the ipcs sent from driver.
0100     * In this case, the driver must ignore the ipc.
0101     */
0102     if (!msg) {
0103         dev_warn(sdev->dev, "unexpected ipc interrupt raised!\n");
0104         return;
0105     }
0106     hdr = msg->msg_data;
0107     if (hdr->cmd == (SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_CTX_SAVE) ||
0108         hdr->cmd == (SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_GATE)) {
0109         /*
0110          * memory windows are powered off before sending IPC reply,
0111          * so we can't read the mailbox for CTX_SAVE and PM_GATE
0112          * replies.
0113          */
0114         reply.error = 0;
0115         reply.hdr.cmd = SOF_IPC_GLB_REPLY;
0116         reply.hdr.size = sizeof(reply);
0117         memcpy(msg->reply_data, &reply, sizeof(reply));
0118         goto out;
0119     }
0120     /* get IPC reply from DSP in the mailbox */
0121     acp_mailbox_read(sdev, offset, &reply, sizeof(reply));
0122     if (reply.error < 0) {
0123         memcpy(msg->reply_data, &reply, sizeof(reply));
0124         ret = reply.error;
0125     } else {
0126         /* reply correct size ? */
0127         if (reply.hdr.size != msg->reply_size &&
0128             !(reply.hdr.cmd & SOF_IPC_GLB_PROBE)) {
0129             dev_err(sdev->dev, "reply expected %zu got %u bytes\n",
0130                 msg->reply_size, reply.hdr.size);
0131             ret = -EINVAL;
0132         }
0133         /* read the message */
0134         if (msg->reply_size > 0)
0135             acp_mailbox_read(sdev, offset, msg->reply_data, msg->reply_size);
0136     }
0137 out:
0138     msg->reply_error = ret;
0139 }
0140
0141 irqreturn_t acp_sof_ipc_irq_thread(int irq, void *context)
0142 {
0143     struct snd_sof_dev *sdev = context;
0144     unsigned int dsp_msg_write = offsetof(struct scratch_ipc_conf, sof_dsp_msg_write);
0145     unsigned int dsp_ack_write = offsetof(struct scratch_ipc_conf, sof_dsp_ack_write);
0146     bool ipc_irq = false;
0147     int dsp_msg, dsp_ack;
0148
0149     dsp_msg = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + dsp_msg_write);
0150     if (dsp_msg) {
0151         snd_sof_ipc_msgs_rx(sdev);
0152         acp_dsp_ipc_host_done(sdev);
0153         ipc_irq = true;
0154     }
0155
0156     dsp_ack = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + dsp_ack_write);
0157     if (dsp_ack) {
0158         spin_lock_irq(&sdev->ipc_lock);
0159         /* handle immediate reply from DSP core */
0160         acp_dsp_ipc_get_reply(sdev);
0161         snd_sof_ipc_reply(sdev, 0);
0162         /* set the done bit */
0163         acp_dsp_ipc_dsp_done(sdev);
0164         spin_unlock_irq(&sdev->ipc_lock);
0165         ipc_irq = true;
0166     }
0167
0168     if (!ipc_irq)
0169         dev_dbg_ratelimited(sdev->dev, "nothing to do in IPC IRQ thread\n");
0170
0171     return IRQ_HANDLED;
0172 }
0173 EXPORT_SYMBOL_NS(acp_sof_ipc_irq_thread, SND_SOC_SOF_AMD_COMMON);
0174
0175 int acp_sof_ipc_msg_data(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream,
0176              void *p, size_t sz)
0177 {
0178     unsigned int offset = offsetof(struct scratch_ipc_conf, sof_out_box);
0179
0180     if (!substream || !sdev->stream_box.size)
0181         acp_mailbox_read(sdev, offset, p, sz);
0182
0183     return 0;
0184 }
0185 EXPORT_SYMBOL_NS(acp_sof_ipc_msg_data, SND_SOC_SOF_AMD_COMMON);
0186
0187 int acp_sof_ipc_get_mailbox_offset(struct snd_sof_dev *sdev)
0188 {
0189     return ACP_SCRATCH_MEMORY_ADDRESS;
0190 }
0191 EXPORT_SYMBOL_NS(acp_sof_ipc_get_mailbox_offset, SND_SOC_SOF_AMD_COMMON);
0192
0193 MODULE_DESCRIPTION("AMD ACP sof-ipc driver");