sof/amd/acp-dsp-offset.h

0001 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
0002 /*
0003  * This file is provided under a dual BSD/GPLv2 license. When using or
0004  * redistributing this file, you may do so under either license.
0005  *
0006  * Copyright(c) 2021 Advanced Micro Devices, Inc. All rights reserved.
0007  *
0008  * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
0009  */
0010
0011 #ifndef _ACP_DSP_IP_OFFSET_H
0012 #define _ACP_DSP_IP_OFFSET_H
0013
0014 /* Registers from ACP_DMA_0 block */
0015 #define ACP_DMA_CNTL_0              0x00
0016 #define ACP_DMA_DSCR_STRT_IDX_0         0x20
0017 #define ACP_DMA_DSCR_CNT_0          0x40
0018 #define ACP_DMA_PRIO_0              0x60
0019 #define ACP_DMA_CUR_DSCR_0          0x80
0020 #define ACP_DMA_ERR_STS_0           0xC0
0021 #define ACP_DMA_DESC_BASE_ADDR          0xE0
0022 #define ACP_DMA_DESC_MAX_NUM_DSCR       0xE4
0023 #define ACP_DMA_CH_STS              0xE8
0024 #define ACP_DMA_CH_GROUP            0xEC
0025 #define ACP_DMA_CH_RST_STS          0xF0
0026
0027 /* Registers from ACP_DSP_0 block */
0028 #define ACP_DSP0_RUNSTALL           0x414
0029
0030 /* Registers from ACP_AXI2AXIATU block */
0031 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1      0xC00
0032 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_1      0xC04
0033 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_2      0xC08
0034 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_2      0xC0C
0035 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_3      0xC10
0036 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_3      0xC14
0037 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_4      0xC18
0038 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_4      0xC1C
0039 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_5      0xC20
0040 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_5      0xC24
0041 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_6      0xC28
0042 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_6      0xC2C
0043 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_7      0xC30
0044 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_7      0xC34
0045 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_8      0xC38
0046 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_8      0xC3C
0047 #define ACPAXI2AXI_ATU_CTRL         0xC40
0048 #define ACP_SOFT_RESET              0x1000
0049 #define ACP_CONTROL             0x1004
0050
0051 #define ACP_I2S_PIN_CONFIG          0x1400
0052
0053 /* Registers from ACP_PGFSM block */
0054 #define ACP_PGFSM_CONTROL           0x141C
0055 #define ACP_PGFSM_STATUS            0x1420
0056 #define ACP_CLKMUX_SEL              0x1424
0057
0058 /* Registers from ACP_INTR block */
0059 #define ACP_EXTERNAL_INTR_ENB           0x1800
0060 #define ACP_EXTERNAL_INTR_CNTL          0x1804
0061 #define ACP_EXTERNAL_INTR_STAT          0x1808
0062 #define ACP_DSP_SW_INTR_CNTL            0x1814
0063 #define ACP_DSP_SW_INTR_STAT                    0x1818
0064 #define ACP_SW_INTR_TRIG                        0x181C
0065 #define ACP_ERROR_STATUS            0x18C4
0066 #define ACP_AXI2DAGB_SEM_0          0x1880
0067
0068 /* Registers from ACP_SHA block */
0069 #define ACP_SHA_DSP_FW_QUALIFIER        0x1C70
0070 #define ACP_SHA_DMA_CMD             0x1CB0
0071 #define ACP_SHA_MSG_LENGTH          0x1CB4
0072 #define ACP_SHA_DMA_STRT_ADDR           0x1CB8
0073 #define ACP_SHA_DMA_DESTINATION_ADDR        0x1CBC
0074 #define ACP_SHA_DMA_CMD_STS         0x1CC0
0075 #define ACP_SHA_DMA_ERR_STATUS          0x1CC4
0076 #define ACP_SHA_TRANSFER_BYTE_CNT       0x1CC8
0077 #define ACP_SHA_PSP_ACK                         0x1C74
0078
0079 #define ACP_SCRATCH_REG_0           0x10000
0080
0081 #endif