Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // Renesas RZ/G2L ASoC Serial Sound Interface (SSIF-2) Driver
0004 //
0005 // Copyright (C) 2021 Renesas Electronics Corp.
0006 // Copyright (C) 2019 Chris Brandt.
0007 //
0008 
0009 #include <linux/clk.h>
0010 #include <linux/dmaengine.h>
0011 #include <linux/io.h>
0012 #include <linux/module.h>
0013 #include <linux/of_device.h>
0014 #include <linux/pm_runtime.h>
0015 #include <linux/reset.h>
0016 #include <sound/soc.h>
0017 
0018 /* REGISTER OFFSET */
0019 #define SSICR           0x000
0020 #define SSISR           0x004
0021 #define SSIFCR          0x010
0022 #define SSIFSR          0x014
0023 #define SSIFTDR         0x018
0024 #define SSIFRDR         0x01c
0025 #define SSIOFR          0x020
0026 #define SSISCR          0x024
0027 
0028 /* SSI REGISTER BITS */
0029 #define SSICR_DWL(x)        (((x) & 0x7) << 19)
0030 #define SSICR_SWL(x)        (((x) & 0x7) << 16)
0031 
0032 #define SSICR_CKS       BIT(30)
0033 #define SSICR_TUIEN     BIT(29)
0034 #define SSICR_TOIEN     BIT(28)
0035 #define SSICR_RUIEN     BIT(27)
0036 #define SSICR_ROIEN     BIT(26)
0037 #define SSICR_MST       BIT(14)
0038 #define SSICR_BCKP      BIT(13)
0039 #define SSICR_LRCKP     BIT(12)
0040 #define SSICR_CKDV(x)       (((x) & 0xf) << 4)
0041 #define SSICR_TEN       BIT(1)
0042 #define SSICR_REN       BIT(0)
0043 
0044 #define SSISR_TUIRQ     BIT(29)
0045 #define SSISR_TOIRQ     BIT(28)
0046 #define SSISR_RUIRQ     BIT(27)
0047 #define SSISR_ROIRQ     BIT(26)
0048 #define SSISR_IIRQ      BIT(25)
0049 
0050 #define SSIFCR_AUCKE        BIT(31)
0051 #define SSIFCR_SSIRST       BIT(16)
0052 #define SSIFCR_TIE      BIT(3)
0053 #define SSIFCR_RIE      BIT(2)
0054 #define SSIFCR_TFRST        BIT(1)
0055 #define SSIFCR_RFRST        BIT(0)
0056 
0057 #define SSIFSR_TDC_MASK     0x3f
0058 #define SSIFSR_TDC_SHIFT    24
0059 #define SSIFSR_RDC_MASK     0x3f
0060 #define SSIFSR_RDC_SHIFT    8
0061 
0062 #define SSIFSR_TDE      BIT(16)
0063 #define SSIFSR_RDF      BIT(0)
0064 
0065 #define SSIOFR_LRCONT       BIT(8)
0066 
0067 #define SSISCR_TDES(x)      (((x) & 0x1f) << 8)
0068 #define SSISCR_RDFS(x)      (((x) & 0x1f) << 0)
0069 
0070 /* Pre allocated buffers sizes */
0071 #define PREALLOC_BUFFER     (SZ_32K)
0072 #define PREALLOC_BUFFER_MAX (SZ_32K)
0073 
0074 #define SSI_RATES       SNDRV_PCM_RATE_8000_48000 /* 8k-44.1kHz */
0075 #define SSI_FMTS        SNDRV_PCM_FMTBIT_S16_LE
0076 #define SSI_CHAN_MIN        2
0077 #define SSI_CHAN_MAX        2
0078 #define SSI_FIFO_DEPTH      32
0079 
0080 struct rz_ssi_priv;
0081 
0082 struct rz_ssi_stream {
0083     struct rz_ssi_priv *priv;
0084     struct snd_pcm_substream *substream;
0085     int fifo_sample_size;   /* sample capacity of SSI FIFO */
0086     int dma_buffer_pos; /* The address for the next DMA descriptor */
0087     int period_counter; /* for keeping track of periods transferred */
0088     int sample_width;
0089     int buffer_pos;     /* current frame position in the buffer */
0090     int running;        /* 0=stopped, 1=running */
0091 
0092     int uerr_num;
0093     int oerr_num;
0094 
0095     struct dma_chan *dma_ch;
0096 
0097     int (*transfer)(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm);
0098 };
0099 
0100 struct rz_ssi_priv {
0101     void __iomem *base;
0102     struct platform_device *pdev;
0103     struct reset_control *rstc;
0104     struct device *dev;
0105     struct clk *sfr_clk;
0106     struct clk *clk;
0107 
0108     phys_addr_t phys;
0109     int irq_int;
0110     int irq_tx;
0111     int irq_rx;
0112 
0113     spinlock_t lock;
0114 
0115     /*
0116      * The SSI supports full-duplex transmission and reception.
0117      * However, if an error occurs, channel reset (both transmission
0118      * and reception reset) is required.
0119      * So it is better to use as half-duplex (playing and recording
0120      * should be done on separate channels).
0121      */
0122     struct rz_ssi_stream playback;
0123     struct rz_ssi_stream capture;
0124 
0125     /* clock */
0126     unsigned long audio_mck;
0127     unsigned long audio_clk_1;
0128     unsigned long audio_clk_2;
0129 
0130     bool lrckp_fsync_fall;  /* LR clock polarity (SSICR.LRCKP) */
0131     bool bckp_rise; /* Bit clock polarity (SSICR.BCKP) */
0132     bool dma_rt;
0133 };
0134 
0135 static void rz_ssi_dma_complete(void *data);
0136 
0137 static void rz_ssi_reg_writel(struct rz_ssi_priv *priv, uint reg, u32 data)
0138 {
0139     writel(data, (priv->base + reg));
0140 }
0141 
0142 static u32 rz_ssi_reg_readl(struct rz_ssi_priv *priv, uint reg)
0143 {
0144     return readl(priv->base + reg);
0145 }
0146 
0147 static void rz_ssi_reg_mask_setl(struct rz_ssi_priv *priv, uint reg,
0148                  u32 bclr, u32 bset)
0149 {
0150     u32 val;
0151 
0152     val = readl(priv->base + reg);
0153     val = (val & ~bclr) | bset;
0154     writel(val, (priv->base + reg));
0155 }
0156 
0157 static inline struct snd_soc_dai *
0158 rz_ssi_get_dai(struct snd_pcm_substream *substream)
0159 {
0160     struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
0161 
0162     return asoc_rtd_to_cpu(rtd, 0);
0163 }
0164 
0165 static inline bool rz_ssi_stream_is_play(struct rz_ssi_priv *ssi,
0166                      struct snd_pcm_substream *substream)
0167 {
0168     return substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
0169 }
0170 
0171 static inline struct rz_ssi_stream *
0172 rz_ssi_stream_get(struct rz_ssi_priv *ssi, struct snd_pcm_substream *substream)
0173 {
0174     struct rz_ssi_stream *stream = &ssi->playback;
0175 
0176     if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
0177         stream = &ssi->capture;
0178 
0179     return stream;
0180 }
0181 
0182 static inline bool rz_ssi_is_dma_enabled(struct rz_ssi_priv *ssi)
0183 {
0184     return (ssi->playback.dma_ch && (ssi->dma_rt || ssi->capture.dma_ch));
0185 }
0186 
0187 static void rz_ssi_set_substream(struct rz_ssi_stream *strm,
0188                  struct snd_pcm_substream *substream)
0189 {
0190     struct rz_ssi_priv *ssi = strm->priv;
0191     unsigned long flags;
0192 
0193     spin_lock_irqsave(&ssi->lock, flags);
0194     strm->substream = substream;
0195     spin_unlock_irqrestore(&ssi->lock, flags);
0196 }
0197 
0198 static bool rz_ssi_stream_is_valid(struct rz_ssi_priv *ssi,
0199                    struct rz_ssi_stream *strm)
0200 {
0201     unsigned long flags;
0202     bool ret;
0203 
0204     spin_lock_irqsave(&ssi->lock, flags);
0205     ret = strm->substream && strm->substream->runtime;
0206     spin_unlock_irqrestore(&ssi->lock, flags);
0207 
0208     return ret;
0209 }
0210 
0211 static void rz_ssi_stream_init(struct rz_ssi_stream *strm,
0212                    struct snd_pcm_substream *substream)
0213 {
0214     struct snd_pcm_runtime *runtime = substream->runtime;
0215 
0216     rz_ssi_set_substream(strm, substream);
0217     strm->sample_width = samples_to_bytes(runtime, 1);
0218     strm->dma_buffer_pos = 0;
0219     strm->period_counter = 0;
0220     strm->buffer_pos = 0;
0221 
0222     strm->oerr_num = 0;
0223     strm->uerr_num = 0;
0224     strm->running = 0;
0225 
0226     /* fifo init */
0227     strm->fifo_sample_size = SSI_FIFO_DEPTH;
0228 }
0229 
0230 static void rz_ssi_stream_quit(struct rz_ssi_priv *ssi,
0231                    struct rz_ssi_stream *strm)
0232 {
0233     struct snd_soc_dai *dai = rz_ssi_get_dai(strm->substream);
0234 
0235     rz_ssi_set_substream(strm, NULL);
0236 
0237     if (strm->oerr_num > 0)
0238         dev_info(dai->dev, "overrun = %d\n", strm->oerr_num);
0239 
0240     if (strm->uerr_num > 0)
0241         dev_info(dai->dev, "underrun = %d\n", strm->uerr_num);
0242 }
0243 
0244 static int rz_ssi_clk_setup(struct rz_ssi_priv *ssi, unsigned int rate,
0245                 unsigned int channels)
0246 {
0247     static s8 ckdv[16] = { 1,  2,  4,  8, 16, 32, 64, 128,
0248                    6, 12, 24, 48, 96, -1, -1, -1 };
0249     unsigned int channel_bits = 32; /* System Word Length */
0250     unsigned long bclk_rate = rate * channels * channel_bits;
0251     unsigned int div;
0252     unsigned int i;
0253     u32 ssicr = 0;
0254     u32 clk_ckdv;
0255 
0256     /* Clear AUCKE so we can set MST */
0257     rz_ssi_reg_writel(ssi, SSIFCR, 0);
0258 
0259     /* Continue to output LRCK pin even when idle */
0260     rz_ssi_reg_writel(ssi, SSIOFR, SSIOFR_LRCONT);
0261     if (ssi->audio_clk_1 && ssi->audio_clk_2) {
0262         if (ssi->audio_clk_1 % bclk_rate)
0263             ssi->audio_mck = ssi->audio_clk_2;
0264         else
0265             ssi->audio_mck = ssi->audio_clk_1;
0266     }
0267 
0268     /* Clock setting */
0269     ssicr |= SSICR_MST;
0270     if (ssi->audio_mck == ssi->audio_clk_1)
0271         ssicr |= SSICR_CKS;
0272     if (ssi->bckp_rise)
0273         ssicr |= SSICR_BCKP;
0274     if (ssi->lrckp_fsync_fall)
0275         ssicr |= SSICR_LRCKP;
0276 
0277     /* Determine the clock divider */
0278     clk_ckdv = 0;
0279     div = ssi->audio_mck / bclk_rate;
0280     /* try to find an match */
0281     for (i = 0; i < ARRAY_SIZE(ckdv); i++) {
0282         if (ckdv[i] == div) {
0283             clk_ckdv = i;
0284             break;
0285         }
0286     }
0287 
0288     if (i == ARRAY_SIZE(ckdv)) {
0289         dev_err(ssi->dev, "Rate not divisible by audio clock source\n");
0290         return -EINVAL;
0291     }
0292 
0293     /*
0294      * DWL: Data Word Length = 16 bits
0295      * SWL: System Word Length = 32 bits
0296      */
0297     ssicr |= SSICR_CKDV(clk_ckdv);
0298     ssicr |= SSICR_DWL(1) | SSICR_SWL(3);
0299     rz_ssi_reg_writel(ssi, SSICR, ssicr);
0300     rz_ssi_reg_writel(ssi, SSIFCR,
0301               (SSIFCR_AUCKE | SSIFCR_TFRST | SSIFCR_RFRST));
0302 
0303     return 0;
0304 }
0305 
0306 static int rz_ssi_start(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm)
0307 {
0308     bool is_play = rz_ssi_stream_is_play(ssi, strm->substream);
0309     u32 ssicr, ssifcr;
0310 
0311     ssicr = rz_ssi_reg_readl(ssi, SSICR);
0312     ssifcr = rz_ssi_reg_readl(ssi, SSIFCR) & ~0xF;
0313 
0314     /* FIFO interrupt thresholds */
0315     if (rz_ssi_is_dma_enabled(ssi))
0316         rz_ssi_reg_writel(ssi, SSISCR, 0);
0317     else
0318         rz_ssi_reg_writel(ssi, SSISCR,
0319                   SSISCR_TDES(strm->fifo_sample_size / 2 - 1) |
0320                   SSISCR_RDFS(0));
0321 
0322     /* enable IRQ */
0323     if (is_play) {
0324         ssicr |= SSICR_TUIEN | SSICR_TOIEN;
0325         ssifcr |= SSIFCR_TIE | SSIFCR_RFRST;
0326     } else {
0327         ssicr |= SSICR_RUIEN | SSICR_ROIEN;
0328         ssifcr |= SSIFCR_RIE | SSIFCR_TFRST;
0329     }
0330 
0331     rz_ssi_reg_writel(ssi, SSICR, ssicr);
0332     rz_ssi_reg_writel(ssi, SSIFCR, ssifcr);
0333 
0334     /* Clear all error flags */
0335     rz_ssi_reg_mask_setl(ssi, SSISR,
0336                  (SSISR_TOIRQ | SSISR_TUIRQ | SSISR_ROIRQ |
0337                   SSISR_RUIRQ), 0);
0338 
0339     strm->running = 1;
0340     ssicr |= is_play ? SSICR_TEN : SSICR_REN;
0341     rz_ssi_reg_writel(ssi, SSICR, ssicr);
0342 
0343     return 0;
0344 }
0345 
0346 static int rz_ssi_stop(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm)
0347 {
0348     int timeout;
0349 
0350     strm->running = 0;
0351 
0352     /* Disable TX/RX */
0353     rz_ssi_reg_mask_setl(ssi, SSICR, SSICR_TEN | SSICR_REN, 0);
0354 
0355     /* Cancel all remaining DMA transactions */
0356     if (rz_ssi_is_dma_enabled(ssi))
0357         dmaengine_terminate_async(strm->dma_ch);
0358 
0359     /* Disable irqs */
0360     rz_ssi_reg_mask_setl(ssi, SSICR, SSICR_TUIEN | SSICR_TOIEN |
0361                  SSICR_RUIEN | SSICR_ROIEN, 0);
0362     rz_ssi_reg_mask_setl(ssi, SSIFCR, SSIFCR_TIE | SSIFCR_RIE, 0);
0363 
0364     /* Clear all error flags */
0365     rz_ssi_reg_mask_setl(ssi, SSISR,
0366                  (SSISR_TOIRQ | SSISR_TUIRQ | SSISR_ROIRQ |
0367                   SSISR_RUIRQ), 0);
0368 
0369     /* Wait for idle */
0370     timeout = 100;
0371     while (--timeout) {
0372         if (rz_ssi_reg_readl(ssi, SSISR) & SSISR_IIRQ)
0373             break;
0374         udelay(1);
0375     }
0376 
0377     if (!timeout)
0378         dev_info(ssi->dev, "timeout waiting for SSI idle\n");
0379 
0380     /* Hold FIFOs in reset */
0381     rz_ssi_reg_mask_setl(ssi, SSIFCR, 0,
0382                  SSIFCR_TFRST | SSIFCR_RFRST);
0383 
0384     return 0;
0385 }
0386 
0387 static void rz_ssi_pointer_update(struct rz_ssi_stream *strm, int frames)
0388 {
0389     struct snd_pcm_substream *substream = strm->substream;
0390     struct snd_pcm_runtime *runtime;
0391     int current_period;
0392 
0393     if (!strm->running || !substream || !substream->runtime)
0394         return;
0395 
0396     runtime = substream->runtime;
0397     strm->buffer_pos += frames;
0398     WARN_ON(strm->buffer_pos > runtime->buffer_size);
0399 
0400     /* ring buffer */
0401     if (strm->buffer_pos == runtime->buffer_size)
0402         strm->buffer_pos = 0;
0403 
0404     current_period = strm->buffer_pos / runtime->period_size;
0405     if (strm->period_counter != current_period) {
0406         snd_pcm_period_elapsed(strm->substream);
0407         strm->period_counter = current_period;
0408     }
0409 }
0410 
0411 static int rz_ssi_pio_recv(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm)
0412 {
0413     struct snd_pcm_substream *substream = strm->substream;
0414     struct snd_pcm_runtime *runtime;
0415     u16 *buf;
0416     int fifo_samples;
0417     int frames_left;
0418     int samples;
0419     int i;
0420 
0421     if (!rz_ssi_stream_is_valid(ssi, strm))
0422         return -EINVAL;
0423 
0424     runtime = substream->runtime;
0425 
0426     do {
0427         /* frames left in this period */
0428         frames_left = runtime->period_size -
0429                   (strm->buffer_pos % runtime->period_size);
0430         if (!frames_left)
0431             frames_left = runtime->period_size;
0432 
0433         /* Samples in RX FIFO */
0434         fifo_samples = (rz_ssi_reg_readl(ssi, SSIFSR) >>
0435                 SSIFSR_RDC_SHIFT) & SSIFSR_RDC_MASK;
0436 
0437         /* Only read full frames at a time */
0438         samples = 0;
0439         while (frames_left && (fifo_samples >= runtime->channels)) {
0440             samples += runtime->channels;
0441             fifo_samples -= runtime->channels;
0442             frames_left--;
0443         }
0444 
0445         /* not enough samples yet */
0446         if (!samples)
0447             break;
0448 
0449         /* calculate new buffer index */
0450         buf = (u16 *)runtime->dma_area;
0451         buf += strm->buffer_pos * runtime->channels;
0452 
0453         /* Note, only supports 16-bit samples */
0454         for (i = 0; i < samples; i++)
0455             *buf++ = (u16)(rz_ssi_reg_readl(ssi, SSIFRDR) >> 16);
0456 
0457         rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_RDF, 0);
0458         rz_ssi_pointer_update(strm, samples / runtime->channels);
0459     } while (!frames_left && fifo_samples >= runtime->channels);
0460 
0461     return 0;
0462 }
0463 
0464 static int rz_ssi_pio_send(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm)
0465 {
0466     struct snd_pcm_substream *substream = strm->substream;
0467     struct snd_pcm_runtime *runtime = substream->runtime;
0468     int sample_space;
0469     int samples = 0;
0470     int frames_left;
0471     int i;
0472     u32 ssifsr;
0473     u16 *buf;
0474 
0475     if (!rz_ssi_stream_is_valid(ssi, strm))
0476         return -EINVAL;
0477 
0478     /* frames left in this period */
0479     frames_left = runtime->period_size - (strm->buffer_pos %
0480                           runtime->period_size);
0481     if (frames_left == 0)
0482         frames_left = runtime->period_size;
0483 
0484     sample_space = strm->fifo_sample_size;
0485     ssifsr = rz_ssi_reg_readl(ssi, SSIFSR);
0486     sample_space -= (ssifsr >> SSIFSR_TDC_SHIFT) & SSIFSR_TDC_MASK;
0487 
0488     /* Only add full frames at a time */
0489     while (frames_left && (sample_space >= runtime->channels)) {
0490         samples += runtime->channels;
0491         sample_space -= runtime->channels;
0492         frames_left--;
0493     }
0494 
0495     /* no space to send anything right now */
0496     if (samples == 0)
0497         return 0;
0498 
0499     /* calculate new buffer index */
0500     buf = (u16 *)(runtime->dma_area);
0501     buf += strm->buffer_pos * runtime->channels;
0502 
0503     /* Note, only supports 16-bit samples */
0504     for (i = 0; i < samples; i++)
0505         rz_ssi_reg_writel(ssi, SSIFTDR, ((u32)(*buf++) << 16));
0506 
0507     rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_TDE, 0);
0508     rz_ssi_pointer_update(strm, samples / runtime->channels);
0509 
0510     return 0;
0511 }
0512 
0513 static irqreturn_t rz_ssi_interrupt(int irq, void *data)
0514 {
0515     struct rz_ssi_stream *strm = NULL;
0516     struct rz_ssi_priv *ssi = data;
0517     u32 ssisr = rz_ssi_reg_readl(ssi, SSISR);
0518 
0519     if (ssi->playback.substream)
0520         strm = &ssi->playback;
0521     else if (ssi->capture.substream)
0522         strm = &ssi->capture;
0523     else
0524         return IRQ_HANDLED; /* Left over TX/RX interrupt */
0525 
0526     if (irq == ssi->irq_int) { /* error or idle */
0527         if (ssisr & SSISR_TUIRQ)
0528             strm->uerr_num++;
0529         if (ssisr & SSISR_TOIRQ)
0530             strm->oerr_num++;
0531         if (ssisr & SSISR_RUIRQ)
0532             strm->uerr_num++;
0533         if (ssisr & SSISR_ROIRQ)
0534             strm->oerr_num++;
0535 
0536         if (ssisr & (SSISR_TUIRQ | SSISR_TOIRQ | SSISR_RUIRQ |
0537                  SSISR_ROIRQ)) {
0538             /* Error handling */
0539             /* You must reset (stop/restart) after each interrupt */
0540             rz_ssi_stop(ssi, strm);
0541 
0542             /* Clear all flags */
0543             rz_ssi_reg_mask_setl(ssi, SSISR, SSISR_TOIRQ |
0544                          SSISR_TUIRQ | SSISR_ROIRQ |
0545                          SSISR_RUIRQ, 0);
0546 
0547             /* Add/remove more data */
0548             strm->transfer(ssi, strm);
0549 
0550             /* Resume */
0551             rz_ssi_start(ssi, strm);
0552         }
0553     }
0554 
0555     if (!strm->running)
0556         return IRQ_HANDLED;
0557 
0558     /* tx data empty */
0559     if (irq == ssi->irq_tx)
0560         strm->transfer(ssi, &ssi->playback);
0561 
0562     /* rx data full */
0563     if (irq == ssi->irq_rx) {
0564         strm->transfer(ssi, &ssi->capture);
0565         rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_RDF, 0);
0566     }
0567 
0568     return IRQ_HANDLED;
0569 }
0570 
0571 static int rz_ssi_dma_slave_config(struct rz_ssi_priv *ssi,
0572                    struct dma_chan *dma_ch, bool is_play)
0573 {
0574     struct dma_slave_config cfg;
0575 
0576     memset(&cfg, 0, sizeof(cfg));
0577 
0578     cfg.direction = is_play ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
0579     cfg.dst_addr = ssi->phys + SSIFTDR;
0580     cfg.src_addr = ssi->phys + SSIFRDR;
0581     cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
0582     cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
0583 
0584     return dmaengine_slave_config(dma_ch, &cfg);
0585 }
0586 
0587 static int rz_ssi_dma_transfer(struct rz_ssi_priv *ssi,
0588                    struct rz_ssi_stream *strm)
0589 {
0590     struct snd_pcm_substream *substream = strm->substream;
0591     struct dma_async_tx_descriptor *desc;
0592     struct snd_pcm_runtime *runtime;
0593     enum dma_transfer_direction dir;
0594     u32 dma_paddr, dma_size;
0595     int amount;
0596 
0597     if (!rz_ssi_stream_is_valid(ssi, strm))
0598         return -EINVAL;
0599 
0600     runtime = substream->runtime;
0601     if (runtime->status->state == SNDRV_PCM_STATE_DRAINING)
0602         /*
0603          * Stream is ending, so do not queue up any more DMA
0604          * transfers otherwise we play partial sound clips
0605          * because we can't shut off the DMA quick enough.
0606          */
0607         return 0;
0608 
0609     dir = rz_ssi_stream_is_play(ssi, substream) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
0610 
0611     /* Always transfer 1 period */
0612     amount = runtime->period_size;
0613 
0614     /* DMA physical address and size */
0615     dma_paddr = runtime->dma_addr + frames_to_bytes(runtime,
0616                             strm->dma_buffer_pos);
0617     dma_size = frames_to_bytes(runtime, amount);
0618     desc = dmaengine_prep_slave_single(strm->dma_ch, dma_paddr, dma_size,
0619                        dir,
0620                        DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
0621     if (!desc) {
0622         dev_err(ssi->dev, "dmaengine_prep_slave_single() fail\n");
0623         return -ENOMEM;
0624     }
0625 
0626     desc->callback = rz_ssi_dma_complete;
0627     desc->callback_param = strm;
0628 
0629     if (dmaengine_submit(desc) < 0) {
0630         dev_err(ssi->dev, "dmaengine_submit() fail\n");
0631         return -EIO;
0632     }
0633 
0634     /* Update DMA pointer */
0635     strm->dma_buffer_pos += amount;
0636     if (strm->dma_buffer_pos >= runtime->buffer_size)
0637         strm->dma_buffer_pos = 0;
0638 
0639     /* Start DMA */
0640     dma_async_issue_pending(strm->dma_ch);
0641 
0642     return 0;
0643 }
0644 
0645 static void rz_ssi_dma_complete(void *data)
0646 {
0647     struct rz_ssi_stream *strm = (struct rz_ssi_stream *)data;
0648 
0649     if (!strm->running || !strm->substream || !strm->substream->runtime)
0650         return;
0651 
0652     /* Note that next DMA transaction has probably already started */
0653     rz_ssi_pointer_update(strm, strm->substream->runtime->period_size);
0654 
0655     /* Queue up another DMA transaction */
0656     rz_ssi_dma_transfer(strm->priv, strm);
0657 }
0658 
0659 static void rz_ssi_release_dma_channels(struct rz_ssi_priv *ssi)
0660 {
0661     if (ssi->playback.dma_ch) {
0662         dma_release_channel(ssi->playback.dma_ch);
0663         ssi->playback.dma_ch = NULL;
0664         if (ssi->dma_rt)
0665             ssi->dma_rt = false;
0666     }
0667 
0668     if (ssi->capture.dma_ch) {
0669         dma_release_channel(ssi->capture.dma_ch);
0670         ssi->capture.dma_ch = NULL;
0671     }
0672 }
0673 
0674 static int rz_ssi_dma_request(struct rz_ssi_priv *ssi, struct device *dev)
0675 {
0676     ssi->playback.dma_ch = dma_request_chan(dev, "tx");
0677     if (IS_ERR(ssi->playback.dma_ch))
0678         ssi->playback.dma_ch = NULL;
0679 
0680     ssi->capture.dma_ch = dma_request_chan(dev, "rx");
0681     if (IS_ERR(ssi->capture.dma_ch))
0682         ssi->capture.dma_ch = NULL;
0683 
0684     if (!ssi->playback.dma_ch && !ssi->capture.dma_ch) {
0685         ssi->playback.dma_ch = dma_request_chan(dev, "rt");
0686         if (IS_ERR(ssi->playback.dma_ch)) {
0687             ssi->playback.dma_ch = NULL;
0688             goto no_dma;
0689         }
0690 
0691         ssi->dma_rt = true;
0692     }
0693 
0694     if (!rz_ssi_is_dma_enabled(ssi))
0695         goto no_dma;
0696 
0697     if (ssi->playback.dma_ch &&
0698         (rz_ssi_dma_slave_config(ssi, ssi->playback.dma_ch, true) < 0))
0699         goto no_dma;
0700 
0701     if (ssi->capture.dma_ch &&
0702         (rz_ssi_dma_slave_config(ssi, ssi->capture.dma_ch, false) < 0))
0703         goto no_dma;
0704 
0705     return 0;
0706 
0707 no_dma:
0708     rz_ssi_release_dma_channels(ssi);
0709 
0710     return -ENODEV;
0711 }
0712 
0713 static int rz_ssi_dai_trigger(struct snd_pcm_substream *substream, int cmd,
0714                   struct snd_soc_dai *dai)
0715 {
0716     struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai);
0717     struct rz_ssi_stream *strm = rz_ssi_stream_get(ssi, substream);
0718     int ret = 0, i, num_transfer = 1;
0719 
0720     switch (cmd) {
0721     case SNDRV_PCM_TRIGGER_START:
0722         /* Soft Reset */
0723         rz_ssi_reg_mask_setl(ssi, SSIFCR, 0, SSIFCR_SSIRST);
0724         rz_ssi_reg_mask_setl(ssi, SSIFCR, SSIFCR_SSIRST, 0);
0725         udelay(5);
0726 
0727         rz_ssi_stream_init(strm, substream);
0728 
0729         if (ssi->dma_rt) {
0730             bool is_playback;
0731 
0732             is_playback = rz_ssi_stream_is_play(ssi, substream);
0733             ret = rz_ssi_dma_slave_config(ssi, ssi->playback.dma_ch,
0734                               is_playback);
0735             /* Fallback to pio */
0736             if (ret < 0) {
0737                 ssi->playback.transfer = rz_ssi_pio_send;
0738                 ssi->capture.transfer = rz_ssi_pio_recv;
0739                 rz_ssi_release_dma_channels(ssi);
0740             }
0741         }
0742 
0743         /* For DMA, queue up multiple DMA descriptors */
0744         if (rz_ssi_is_dma_enabled(ssi))
0745             num_transfer = 4;
0746 
0747         for (i = 0; i < num_transfer; i++) {
0748             ret = strm->transfer(ssi, strm);
0749             if (ret)
0750                 goto done;
0751         }
0752 
0753         ret = rz_ssi_start(ssi, strm);
0754         break;
0755     case SNDRV_PCM_TRIGGER_STOP:
0756         rz_ssi_stop(ssi, strm);
0757         rz_ssi_stream_quit(ssi, strm);
0758         break;
0759     }
0760 
0761 done:
0762     return ret;
0763 }
0764 
0765 static int rz_ssi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
0766 {
0767     struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai);
0768 
0769     switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
0770     case SND_SOC_DAIFMT_BP_FP:
0771         break;
0772     default:
0773         dev_err(ssi->dev, "Codec should be clk and frame consumer\n");
0774         return -EINVAL;
0775     }
0776 
0777     /*
0778      * set clock polarity
0779      *
0780      * "normal" BCLK = Signal is available at rising edge of BCLK
0781      * "normal" FSYNC = (I2S) Left ch starts with falling FSYNC edge
0782      */
0783     switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
0784     case SND_SOC_DAIFMT_NB_NF:
0785         ssi->bckp_rise = false;
0786         ssi->lrckp_fsync_fall = false;
0787         break;
0788     case SND_SOC_DAIFMT_NB_IF:
0789         ssi->bckp_rise = false;
0790         ssi->lrckp_fsync_fall = true;
0791         break;
0792     case SND_SOC_DAIFMT_IB_NF:
0793         ssi->bckp_rise = true;
0794         ssi->lrckp_fsync_fall = false;
0795         break;
0796     case SND_SOC_DAIFMT_IB_IF:
0797         ssi->bckp_rise = true;
0798         ssi->lrckp_fsync_fall = true;
0799         break;
0800     default:
0801         return -EINVAL;
0802     }
0803 
0804     /* only i2s support */
0805     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0806     case SND_SOC_DAIFMT_I2S:
0807         break;
0808     default:
0809         dev_err(ssi->dev, "Only I2S mode is supported.\n");
0810         return -EINVAL;
0811     }
0812 
0813     return 0;
0814 }
0815 
0816 static int rz_ssi_dai_hw_params(struct snd_pcm_substream *substream,
0817                 struct snd_pcm_hw_params *params,
0818                 struct snd_soc_dai *dai)
0819 {
0820     struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai);
0821     unsigned int sample_bits = hw_param_interval(params,
0822                     SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
0823     unsigned int channels = params_channels(params);
0824 
0825     if (sample_bits != 16) {
0826         dev_err(ssi->dev, "Unsupported sample width: %d\n",
0827             sample_bits);
0828         return -EINVAL;
0829     }
0830 
0831     if (channels != 2) {
0832         dev_err(ssi->dev, "Number of channels not matched: %d\n",
0833             channels);
0834         return -EINVAL;
0835     }
0836 
0837     return rz_ssi_clk_setup(ssi, params_rate(params),
0838                 params_channels(params));
0839 }
0840 
0841 static const struct snd_soc_dai_ops rz_ssi_dai_ops = {
0842     .trigger    = rz_ssi_dai_trigger,
0843     .set_fmt    = rz_ssi_dai_set_fmt,
0844     .hw_params  = rz_ssi_dai_hw_params,
0845 };
0846 
0847 static const struct snd_pcm_hardware rz_ssi_pcm_hardware = {
0848     .info           = SNDRV_PCM_INFO_INTERLEAVED    |
0849                   SNDRV_PCM_INFO_MMAP       |
0850                   SNDRV_PCM_INFO_MMAP_VALID,
0851     .buffer_bytes_max   = PREALLOC_BUFFER,
0852     .period_bytes_min   = 32,
0853     .period_bytes_max   = 8192,
0854     .channels_min       = SSI_CHAN_MIN,
0855     .channels_max       = SSI_CHAN_MAX,
0856     .periods_min        = 1,
0857     .periods_max        = 32,
0858     .fifo_size      = 32 * 2,
0859 };
0860 
0861 static int rz_ssi_pcm_open(struct snd_soc_component *component,
0862                struct snd_pcm_substream *substream)
0863 {
0864     snd_soc_set_runtime_hwparams(substream, &rz_ssi_pcm_hardware);
0865 
0866     return snd_pcm_hw_constraint_integer(substream->runtime,
0867                         SNDRV_PCM_HW_PARAM_PERIODS);
0868 }
0869 
0870 static snd_pcm_uframes_t rz_ssi_pcm_pointer(struct snd_soc_component *component,
0871                         struct snd_pcm_substream *substream)
0872 {
0873     struct snd_soc_dai *dai = rz_ssi_get_dai(substream);
0874     struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai);
0875     struct rz_ssi_stream *strm = rz_ssi_stream_get(ssi, substream);
0876 
0877     return strm->buffer_pos;
0878 }
0879 
0880 static int rz_ssi_pcm_new(struct snd_soc_component *component,
0881               struct snd_soc_pcm_runtime *rtd)
0882 {
0883     snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV,
0884                        rtd->card->snd_card->dev,
0885                        PREALLOC_BUFFER, PREALLOC_BUFFER_MAX);
0886     return 0;
0887 }
0888 
0889 static struct snd_soc_dai_driver rz_ssi_soc_dai[] = {
0890     {
0891         .name           = "rz-ssi-dai",
0892         .playback = {
0893             .rates      = SSI_RATES,
0894             .formats    = SSI_FMTS,
0895             .channels_min   = SSI_CHAN_MIN,
0896             .channels_max   = SSI_CHAN_MAX,
0897         },
0898         .capture = {
0899             .rates      = SSI_RATES,
0900             .formats    = SSI_FMTS,
0901             .channels_min   = SSI_CHAN_MIN,
0902             .channels_max   = SSI_CHAN_MAX,
0903         },
0904         .ops = &rz_ssi_dai_ops,
0905     },
0906 };
0907 
0908 static const struct snd_soc_component_driver rz_ssi_soc_component = {
0909     .name           = "rz-ssi",
0910     .open           = rz_ssi_pcm_open,
0911     .pointer        = rz_ssi_pcm_pointer,
0912     .pcm_construct      = rz_ssi_pcm_new,
0913     .legacy_dai_naming  = 1,
0914 };
0915 
0916 static int rz_ssi_probe(struct platform_device *pdev)
0917 {
0918     struct rz_ssi_priv *ssi;
0919     struct clk *audio_clk;
0920     struct resource *res;
0921     int ret;
0922 
0923     ssi = devm_kzalloc(&pdev->dev, sizeof(*ssi), GFP_KERNEL);
0924     if (!ssi)
0925         return -ENOMEM;
0926 
0927     ssi->pdev = pdev;
0928     ssi->dev = &pdev->dev;
0929     ssi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
0930     if (IS_ERR(ssi->base))
0931         return PTR_ERR(ssi->base);
0932 
0933     ssi->phys = res->start;
0934     ssi->clk = devm_clk_get(&pdev->dev, "ssi");
0935     if (IS_ERR(ssi->clk))
0936         return PTR_ERR(ssi->clk);
0937 
0938     ssi->sfr_clk = devm_clk_get(&pdev->dev, "ssi_sfr");
0939     if (IS_ERR(ssi->sfr_clk))
0940         return PTR_ERR(ssi->sfr_clk);
0941 
0942     audio_clk = devm_clk_get(&pdev->dev, "audio_clk1");
0943     if (IS_ERR(audio_clk))
0944         return dev_err_probe(&pdev->dev, PTR_ERR(audio_clk),
0945                      "no audio clk1");
0946 
0947     ssi->audio_clk_1 = clk_get_rate(audio_clk);
0948     audio_clk = devm_clk_get(&pdev->dev, "audio_clk2");
0949     if (IS_ERR(audio_clk))
0950         return dev_err_probe(&pdev->dev, PTR_ERR(audio_clk),
0951                      "no audio clk2");
0952 
0953     ssi->audio_clk_2 = clk_get_rate(audio_clk);
0954     if (!(ssi->audio_clk_1 || ssi->audio_clk_2))
0955         return dev_err_probe(&pdev->dev, -EINVAL,
0956                      "no audio clk1 or audio clk2");
0957 
0958     ssi->audio_mck = ssi->audio_clk_1 ? ssi->audio_clk_1 : ssi->audio_clk_2;
0959 
0960     /* Detect DMA support */
0961     ret = rz_ssi_dma_request(ssi, &pdev->dev);
0962     if (ret < 0) {
0963         dev_warn(&pdev->dev, "DMA not available, using PIO\n");
0964         ssi->playback.transfer = rz_ssi_pio_send;
0965         ssi->capture.transfer = rz_ssi_pio_recv;
0966     } else {
0967         dev_info(&pdev->dev, "DMA enabled");
0968         ssi->playback.transfer = rz_ssi_dma_transfer;
0969         ssi->capture.transfer = rz_ssi_dma_transfer;
0970     }
0971 
0972     ssi->playback.priv = ssi;
0973     ssi->capture.priv = ssi;
0974 
0975     spin_lock_init(&ssi->lock);
0976     dev_set_drvdata(&pdev->dev, ssi);
0977 
0978     /* Error Interrupt */
0979     ssi->irq_int = platform_get_irq_byname(pdev, "int_req");
0980     if (ssi->irq_int < 0) {
0981         rz_ssi_release_dma_channels(ssi);
0982         return ssi->irq_int;
0983     }
0984 
0985     ret = devm_request_irq(&pdev->dev, ssi->irq_int, &rz_ssi_interrupt,
0986                    0, dev_name(&pdev->dev), ssi);
0987     if (ret < 0) {
0988         rz_ssi_release_dma_channels(ssi);
0989         return dev_err_probe(&pdev->dev, ret,
0990                      "irq request error (int_req)\n");
0991     }
0992 
0993     if (!rz_ssi_is_dma_enabled(ssi)) {
0994         /* Tx and Rx interrupts (pio only) */
0995         ssi->irq_tx = platform_get_irq_byname(pdev, "dma_tx");
0996         if (ssi->irq_tx < 0)
0997             return ssi->irq_tx;
0998 
0999         ret = devm_request_irq(&pdev->dev, ssi->irq_tx,
1000                        &rz_ssi_interrupt, 0,
1001                        dev_name(&pdev->dev), ssi);
1002         if (ret < 0)
1003             return dev_err_probe(&pdev->dev, ret,
1004                          "irq request error (dma_tx)\n");
1005 
1006         ssi->irq_rx = platform_get_irq_byname(pdev, "dma_rx");
1007         if (ssi->irq_rx < 0)
1008             return ssi->irq_rx;
1009 
1010         ret = devm_request_irq(&pdev->dev, ssi->irq_rx,
1011                        &rz_ssi_interrupt, 0,
1012                        dev_name(&pdev->dev), ssi);
1013         if (ret < 0)
1014             return dev_err_probe(&pdev->dev, ret,
1015                          "irq request error (dma_rx)\n");
1016     }
1017 
1018     ssi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
1019     if (IS_ERR(ssi->rstc)) {
1020         ret = PTR_ERR(ssi->rstc);
1021         goto err_reset;
1022     }
1023 
1024     reset_control_deassert(ssi->rstc);
1025     pm_runtime_enable(&pdev->dev);
1026     ret = pm_runtime_resume_and_get(&pdev->dev);
1027     if (ret < 0) {
1028         dev_err(&pdev->dev, "pm_runtime_resume_and_get failed\n");
1029         goto err_pm;
1030     }
1031 
1032     ret = devm_snd_soc_register_component(&pdev->dev, &rz_ssi_soc_component,
1033                           rz_ssi_soc_dai,
1034                           ARRAY_SIZE(rz_ssi_soc_dai));
1035     if (ret < 0) {
1036         dev_err(&pdev->dev, "failed to register snd component\n");
1037         goto err_snd_soc;
1038     }
1039 
1040     return 0;
1041 
1042 err_snd_soc:
1043     pm_runtime_put(ssi->dev);
1044 err_pm:
1045     pm_runtime_disable(ssi->dev);
1046     reset_control_assert(ssi->rstc);
1047 err_reset:
1048     rz_ssi_release_dma_channels(ssi);
1049 
1050     return ret;
1051 }
1052 
1053 static int rz_ssi_remove(struct platform_device *pdev)
1054 {
1055     struct rz_ssi_priv *ssi = dev_get_drvdata(&pdev->dev);
1056 
1057     rz_ssi_release_dma_channels(ssi);
1058 
1059     pm_runtime_put(ssi->dev);
1060     pm_runtime_disable(ssi->dev);
1061     reset_control_assert(ssi->rstc);
1062 
1063     return 0;
1064 }
1065 
1066 static const struct of_device_id rz_ssi_of_match[] = {
1067     { .compatible = "renesas,rz-ssi", },
1068     {/* Sentinel */},
1069 };
1070 MODULE_DEVICE_TABLE(of, rz_ssi_of_match);
1071 
1072 static struct platform_driver rz_ssi_driver = {
1073     .driver = {
1074         .name   = "rz-ssi-pcm-audio",
1075         .of_match_table = rz_ssi_of_match,
1076     },
1077     .probe      = rz_ssi_probe,
1078     .remove     = rz_ssi_remove,
1079 };
1080 
1081 module_platform_driver(rz_ssi_driver);
1082 
1083 MODULE_LICENSE("GPL v2");
1084 MODULE_DESCRIPTION("Renesas RZ/G2L ASoC Serial Sound Interface Driver");
1085 MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!