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0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // Renesas R-Car Gen1 SRU/SSI support
0004 //
0005 // Copyright (C) 2013 Renesas Solutions Corp.
0006 // Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
0007 
0008 /*
0009  * #define DEBUG
0010  *
0011  * you can also add below in
0012  * ${LINUX}/drivers/base/regmap/regmap.c
0013  * for regmap debug
0014  *
0015  * #define LOG_DEVICE "xxxx.rcar_sound"
0016  */
0017 
0018 #include "rsnd.h"
0019 
0020 struct rsnd_gen {
0021     struct rsnd_gen_ops *ops;
0022 
0023     /* RSND_BASE_MAX base */
0024     void __iomem *base[RSND_BASE_MAX];
0025     phys_addr_t res[RSND_BASE_MAX];
0026     struct regmap *regmap[RSND_BASE_MAX];
0027 
0028     /* RSND_REG_MAX base */
0029     struct regmap_field *regs[REG_MAX];
0030     const char *reg_name[REG_MAX];
0031 };
0032 
0033 #define rsnd_priv_to_gen(p) ((struct rsnd_gen *)(p)->gen)
0034 #define rsnd_reg_name(gen, id)  ((gen)->reg_name[id])
0035 
0036 struct rsnd_regmap_field_conf {
0037     int idx;
0038     unsigned int reg_offset;
0039     unsigned int id_offset;
0040     const char *reg_name;
0041 };
0042 
0043 #define RSND_REG_SET(id, offset, _id_offset, n) \
0044 {                       \
0045     .idx = id,              \
0046     .reg_offset = offset,           \
0047     .id_offset = _id_offset,        \
0048     .reg_name = n,              \
0049 }
0050 /* single address mapping */
0051 #define RSND_GEN_S_REG(id, offset)  \
0052     RSND_REG_SET(id, offset, 0, #id)
0053 
0054 /* multi address mapping */
0055 #define RSND_GEN_M_REG(id, offset, _id_offset)  \
0056     RSND_REG_SET(id, offset, _id_offset, #id)
0057 
0058 /*
0059  *      basic function
0060  */
0061 static int rsnd_is_accessible_reg(struct rsnd_priv *priv,
0062                   struct rsnd_gen *gen, enum rsnd_reg reg)
0063 {
0064     if (!gen->regs[reg]) {
0065         struct device *dev = rsnd_priv_to_dev(priv);
0066 
0067         dev_err(dev, "unsupported register access %x\n", reg);
0068         return 0;
0069     }
0070 
0071     return 1;
0072 }
0073 
0074 static int rsnd_mod_id_cmd(struct rsnd_mod *mod)
0075 {
0076     if (mod->ops->id_cmd)
0077         return mod->ops->id_cmd(mod);
0078 
0079     return rsnd_mod_id(mod);
0080 }
0081 
0082 u32 rsnd_mod_read(struct rsnd_mod *mod, enum rsnd_reg reg)
0083 {
0084     struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
0085     struct device *dev = rsnd_priv_to_dev(priv);
0086     struct rsnd_gen *gen = rsnd_priv_to_gen(priv);
0087     u32 val;
0088 
0089     if (!rsnd_is_accessible_reg(priv, gen, reg))
0090         return 0;
0091 
0092     regmap_fields_read(gen->regs[reg], rsnd_mod_id_cmd(mod), &val);
0093 
0094     dev_dbg(dev, "r %s - %-18s (%4d) : %08x\n",
0095         rsnd_mod_name(mod),
0096         rsnd_reg_name(gen, reg), reg, val);
0097 
0098     return val;
0099 }
0100 
0101 void rsnd_mod_write(struct rsnd_mod *mod,
0102             enum rsnd_reg reg, u32 data)
0103 {
0104     struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
0105     struct device *dev = rsnd_priv_to_dev(priv);
0106     struct rsnd_gen *gen = rsnd_priv_to_gen(priv);
0107 
0108     if (!rsnd_is_accessible_reg(priv, gen, reg))
0109         return;
0110 
0111     regmap_fields_force_write(gen->regs[reg], rsnd_mod_id_cmd(mod), data);
0112 
0113     dev_dbg(dev, "w %s - %-18s (%4d) : %08x\n",
0114         rsnd_mod_name(mod),
0115         rsnd_reg_name(gen, reg), reg, data);
0116 }
0117 
0118 void rsnd_mod_bset(struct rsnd_mod *mod,
0119            enum rsnd_reg reg, u32 mask, u32 data)
0120 {
0121     struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
0122     struct device *dev = rsnd_priv_to_dev(priv);
0123     struct rsnd_gen *gen = rsnd_priv_to_gen(priv);
0124 
0125     if (!rsnd_is_accessible_reg(priv, gen, reg))
0126         return;
0127 
0128     regmap_fields_force_update_bits(gen->regs[reg],
0129                     rsnd_mod_id_cmd(mod), mask, data);
0130 
0131     dev_dbg(dev, "b %s - %-18s (%4d) : %08x/%08x\n",
0132         rsnd_mod_name(mod),
0133         rsnd_reg_name(gen, reg), reg, data, mask);
0134 
0135 }
0136 
0137 phys_addr_t rsnd_gen_get_phy_addr(struct rsnd_priv *priv, int reg_id)
0138 {
0139     struct rsnd_gen *gen = rsnd_priv_to_gen(priv);
0140 
0141     return  gen->res[reg_id];
0142 }
0143 
0144 #ifdef CONFIG_DEBUG_FS
0145 void __iomem *rsnd_gen_get_base_addr(struct rsnd_priv *priv, int reg_id)
0146 {
0147     struct rsnd_gen *gen = rsnd_priv_to_gen(priv);
0148 
0149     return  gen->base[reg_id];
0150 }
0151 #endif
0152 
0153 #define rsnd_gen_regmap_init(priv, id_size, reg_id, name, conf)     \
0154     _rsnd_gen_regmap_init(priv, id_size, reg_id, name, conf, ARRAY_SIZE(conf))
0155 static int _rsnd_gen_regmap_init(struct rsnd_priv *priv,
0156                  int id_size,
0157                  int reg_id,
0158                  const char *name,
0159                  const struct rsnd_regmap_field_conf *conf,
0160                  int conf_size)
0161 {
0162     struct platform_device *pdev = rsnd_priv_to_pdev(priv);
0163     struct rsnd_gen *gen = rsnd_priv_to_gen(priv);
0164     struct device *dev = rsnd_priv_to_dev(priv);
0165     struct resource *res;
0166     struct regmap_config regc;
0167     struct regmap_field *regs;
0168     struct regmap *regmap;
0169     struct reg_field regf;
0170     void __iomem *base;
0171     int i;
0172 
0173     memset(&regc, 0, sizeof(regc));
0174     regc.reg_bits = 32;
0175     regc.val_bits = 32;
0176     regc.reg_stride = 4;
0177     regc.name = name;
0178 
0179     res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
0180     if (!res)
0181         res = platform_get_resource(pdev, IORESOURCE_MEM, reg_id);
0182     if (!res)
0183         return -ENODEV;
0184 
0185     base = devm_ioremap_resource(dev, res);
0186     if (IS_ERR(base))
0187         return PTR_ERR(base);
0188 
0189     regmap = devm_regmap_init_mmio(dev, base, &regc);
0190     if (IS_ERR(regmap))
0191         return PTR_ERR(regmap);
0192 
0193     /* RSND_BASE_MAX base */
0194     gen->base[reg_id] = base;
0195     gen->regmap[reg_id] = regmap;
0196     gen->res[reg_id] = res->start;
0197 
0198     for (i = 0; i < conf_size; i++) {
0199 
0200         regf.reg    = conf[i].reg_offset;
0201         regf.id_offset  = conf[i].id_offset;
0202         regf.lsb    = 0;
0203         regf.msb    = 31;
0204         regf.id_size    = id_size;
0205 
0206         regs = devm_regmap_field_alloc(dev, regmap, regf);
0207         if (IS_ERR(regs))
0208             return PTR_ERR(regs);
0209 
0210         /* RSND_REG_MAX base */
0211         gen->regs[conf[i].idx] = regs;
0212         gen->reg_name[conf[i].idx] = conf[i].reg_name;
0213     }
0214 
0215     return 0;
0216 }
0217 
0218 /*
0219  *      Gen2
0220  */
0221 static int rsnd_gen2_probe(struct rsnd_priv *priv)
0222 {
0223     static const struct rsnd_regmap_field_conf conf_ssiu[] = {
0224         RSND_GEN_S_REG(SSI_MODE0,   0x800),
0225         RSND_GEN_S_REG(SSI_MODE1,   0x804),
0226         RSND_GEN_S_REG(SSI_MODE2,   0x808),
0227         RSND_GEN_S_REG(SSI_CONTROL, 0x810),
0228         RSND_GEN_S_REG(SSI_SYS_STATUS0, 0x840),
0229         RSND_GEN_S_REG(SSI_SYS_STATUS1, 0x844),
0230         RSND_GEN_S_REG(SSI_SYS_STATUS2, 0x848),
0231         RSND_GEN_S_REG(SSI_SYS_STATUS3, 0x84c),
0232         RSND_GEN_S_REG(SSI_SYS_STATUS4, 0x880),
0233         RSND_GEN_S_REG(SSI_SYS_STATUS5, 0x884),
0234         RSND_GEN_S_REG(SSI_SYS_STATUS6, 0x888),
0235         RSND_GEN_S_REG(SSI_SYS_STATUS7, 0x88c),
0236         RSND_GEN_S_REG(SSI_SYS_INT_ENABLE0, 0x850),
0237         RSND_GEN_S_REG(SSI_SYS_INT_ENABLE1, 0x854),
0238         RSND_GEN_S_REG(SSI_SYS_INT_ENABLE2, 0x858),
0239         RSND_GEN_S_REG(SSI_SYS_INT_ENABLE3, 0x85c),
0240         RSND_GEN_S_REG(SSI_SYS_INT_ENABLE4, 0x890),
0241         RSND_GEN_S_REG(SSI_SYS_INT_ENABLE5, 0x894),
0242         RSND_GEN_S_REG(SSI_SYS_INT_ENABLE6, 0x898),
0243         RSND_GEN_S_REG(SSI_SYS_INT_ENABLE7, 0x89c),
0244         RSND_GEN_S_REG(HDMI0_SEL,   0x9e0),
0245         RSND_GEN_S_REG(HDMI1_SEL,   0x9e4),
0246 
0247         /* FIXME: it needs SSI_MODE2/3 in the future */
0248         RSND_GEN_M_REG(SSI_BUSIF0_MODE,     0x0,    0x80),
0249         RSND_GEN_M_REG(SSI_BUSIF0_ADINR,    0x4,    0x80),
0250         RSND_GEN_M_REG(SSI_BUSIF0_DALIGN,   0x8,    0x80),
0251         RSND_GEN_M_REG(SSI_BUSIF1_MODE,     0x20,   0x80),
0252         RSND_GEN_M_REG(SSI_BUSIF1_ADINR,    0x24,   0x80),
0253         RSND_GEN_M_REG(SSI_BUSIF1_DALIGN,   0x28,   0x80),
0254         RSND_GEN_M_REG(SSI_BUSIF2_MODE,     0x40,   0x80),
0255         RSND_GEN_M_REG(SSI_BUSIF2_ADINR,    0x44,   0x80),
0256         RSND_GEN_M_REG(SSI_BUSIF2_DALIGN,   0x48,   0x80),
0257         RSND_GEN_M_REG(SSI_BUSIF3_MODE,     0x60,   0x80),
0258         RSND_GEN_M_REG(SSI_BUSIF3_ADINR,    0x64,   0x80),
0259         RSND_GEN_M_REG(SSI_BUSIF3_DALIGN,   0x68,   0x80),
0260         RSND_GEN_M_REG(SSI_BUSIF4_MODE,     0x500,  0x80),
0261         RSND_GEN_M_REG(SSI_BUSIF4_ADINR,    0x504,  0x80),
0262         RSND_GEN_M_REG(SSI_BUSIF4_DALIGN,   0x508,  0x80),
0263         RSND_GEN_M_REG(SSI_BUSIF5_MODE,     0x520,  0x80),
0264         RSND_GEN_M_REG(SSI_BUSIF5_ADINR,    0x524,  0x80),
0265         RSND_GEN_M_REG(SSI_BUSIF5_DALIGN,   0x528,  0x80),
0266         RSND_GEN_M_REG(SSI_BUSIF6_MODE,     0x540,  0x80),
0267         RSND_GEN_M_REG(SSI_BUSIF6_ADINR,    0x544,  0x80),
0268         RSND_GEN_M_REG(SSI_BUSIF6_DALIGN,   0x548,  0x80),
0269         RSND_GEN_M_REG(SSI_BUSIF7_MODE,     0x560,  0x80),
0270         RSND_GEN_M_REG(SSI_BUSIF7_ADINR,    0x564,  0x80),
0271         RSND_GEN_M_REG(SSI_BUSIF7_DALIGN,   0x568,  0x80),
0272         RSND_GEN_M_REG(SSI_MODE,        0xc,    0x80),
0273         RSND_GEN_M_REG(SSI_CTRL,        0x10,   0x80),
0274         RSND_GEN_M_REG(SSI_INT_ENABLE,      0x18,   0x80),
0275         RSND_GEN_S_REG(SSI9_BUSIF0_MODE,    0x48c),
0276         RSND_GEN_S_REG(SSI9_BUSIF0_ADINR,   0x484),
0277         RSND_GEN_S_REG(SSI9_BUSIF0_DALIGN,  0x488),
0278         RSND_GEN_S_REG(SSI9_BUSIF1_MODE,    0x4a0),
0279         RSND_GEN_S_REG(SSI9_BUSIF1_ADINR,   0x4a4),
0280         RSND_GEN_S_REG(SSI9_BUSIF1_DALIGN,  0x4a8),
0281         RSND_GEN_S_REG(SSI9_BUSIF2_MODE,    0x4c0),
0282         RSND_GEN_S_REG(SSI9_BUSIF2_ADINR,   0x4c4),
0283         RSND_GEN_S_REG(SSI9_BUSIF2_DALIGN,  0x4c8),
0284         RSND_GEN_S_REG(SSI9_BUSIF3_MODE,    0x4e0),
0285         RSND_GEN_S_REG(SSI9_BUSIF3_ADINR,   0x4e4),
0286         RSND_GEN_S_REG(SSI9_BUSIF3_DALIGN,  0x4e8),
0287         RSND_GEN_S_REG(SSI9_BUSIF4_MODE,    0xd80),
0288         RSND_GEN_S_REG(SSI9_BUSIF4_ADINR,   0xd84),
0289         RSND_GEN_S_REG(SSI9_BUSIF4_DALIGN,  0xd88),
0290         RSND_GEN_S_REG(SSI9_BUSIF5_MODE,    0xda0),
0291         RSND_GEN_S_REG(SSI9_BUSIF5_ADINR,   0xda4),
0292         RSND_GEN_S_REG(SSI9_BUSIF5_DALIGN,  0xda8),
0293         RSND_GEN_S_REG(SSI9_BUSIF6_MODE,    0xdc0),
0294         RSND_GEN_S_REG(SSI9_BUSIF6_ADINR,   0xdc4),
0295         RSND_GEN_S_REG(SSI9_BUSIF6_DALIGN,  0xdc8),
0296         RSND_GEN_S_REG(SSI9_BUSIF7_MODE,    0xde0),
0297         RSND_GEN_S_REG(SSI9_BUSIF7_ADINR,   0xde4),
0298         RSND_GEN_S_REG(SSI9_BUSIF7_DALIGN,  0xde8),
0299     };
0300 
0301     static const struct rsnd_regmap_field_conf conf_scu[] = {
0302         RSND_GEN_M_REG(SRC_I_BUSIF_MODE,0x0,    0x20),
0303         RSND_GEN_M_REG(SRC_O_BUSIF_MODE,0x4,    0x20),
0304         RSND_GEN_M_REG(SRC_BUSIF_DALIGN,0x8,    0x20),
0305         RSND_GEN_M_REG(SRC_ROUTE_MODE0, 0xc,    0x20),
0306         RSND_GEN_M_REG(SRC_CTRL,    0x10,   0x20),
0307         RSND_GEN_M_REG(SRC_INT_ENABLE0, 0x18,   0x20),
0308         RSND_GEN_M_REG(CMD_BUSIF_MODE,  0x184,  0x20),
0309         RSND_GEN_M_REG(CMD_BUSIF_DALIGN,0x188,  0x20),
0310         RSND_GEN_M_REG(CMD_ROUTE_SLCT,  0x18c,  0x20),
0311         RSND_GEN_M_REG(CMD_CTRL,    0x190,  0x20),
0312         RSND_GEN_S_REG(SCU_SYS_STATUS0, 0x1c8),
0313         RSND_GEN_S_REG(SCU_SYS_INT_EN0, 0x1cc),
0314         RSND_GEN_S_REG(SCU_SYS_STATUS1, 0x1d0),
0315         RSND_GEN_S_REG(SCU_SYS_INT_EN1, 0x1d4),
0316         RSND_GEN_M_REG(SRC_SWRSR,   0x200,  0x40),
0317         RSND_GEN_M_REG(SRC_SRCIR,   0x204,  0x40),
0318         RSND_GEN_M_REG(SRC_ADINR,   0x214,  0x40),
0319         RSND_GEN_M_REG(SRC_IFSCR,   0x21c,  0x40),
0320         RSND_GEN_M_REG(SRC_IFSVR,   0x220,  0x40),
0321         RSND_GEN_M_REG(SRC_SRCCR,   0x224,  0x40),
0322         RSND_GEN_M_REG(SRC_BSDSR,   0x22c,  0x40),
0323         RSND_GEN_M_REG(SRC_BSISR,   0x238,  0x40),
0324         RSND_GEN_M_REG(CTU_SWRSR,   0x500,  0x100),
0325         RSND_GEN_M_REG(CTU_CTUIR,   0x504,  0x100),
0326         RSND_GEN_M_REG(CTU_ADINR,   0x508,  0x100),
0327         RSND_GEN_M_REG(CTU_CPMDR,   0x510,  0x100),
0328         RSND_GEN_M_REG(CTU_SCMDR,   0x514,  0x100),
0329         RSND_GEN_M_REG(CTU_SV00R,   0x518,  0x100),
0330         RSND_GEN_M_REG(CTU_SV01R,   0x51c,  0x100),
0331         RSND_GEN_M_REG(CTU_SV02R,   0x520,  0x100),
0332         RSND_GEN_M_REG(CTU_SV03R,   0x524,  0x100),
0333         RSND_GEN_M_REG(CTU_SV04R,   0x528,  0x100),
0334         RSND_GEN_M_REG(CTU_SV05R,   0x52c,  0x100),
0335         RSND_GEN_M_REG(CTU_SV06R,   0x530,  0x100),
0336         RSND_GEN_M_REG(CTU_SV07R,   0x534,  0x100),
0337         RSND_GEN_M_REG(CTU_SV10R,   0x538,  0x100),
0338         RSND_GEN_M_REG(CTU_SV11R,   0x53c,  0x100),
0339         RSND_GEN_M_REG(CTU_SV12R,   0x540,  0x100),
0340         RSND_GEN_M_REG(CTU_SV13R,   0x544,  0x100),
0341         RSND_GEN_M_REG(CTU_SV14R,   0x548,  0x100),
0342         RSND_GEN_M_REG(CTU_SV15R,   0x54c,  0x100),
0343         RSND_GEN_M_REG(CTU_SV16R,   0x550,  0x100),
0344         RSND_GEN_M_REG(CTU_SV17R,   0x554,  0x100),
0345         RSND_GEN_M_REG(CTU_SV20R,   0x558,  0x100),
0346         RSND_GEN_M_REG(CTU_SV21R,   0x55c,  0x100),
0347         RSND_GEN_M_REG(CTU_SV22R,   0x560,  0x100),
0348         RSND_GEN_M_REG(CTU_SV23R,   0x564,  0x100),
0349         RSND_GEN_M_REG(CTU_SV24R,   0x568,  0x100),
0350         RSND_GEN_M_REG(CTU_SV25R,   0x56c,  0x100),
0351         RSND_GEN_M_REG(CTU_SV26R,   0x570,  0x100),
0352         RSND_GEN_M_REG(CTU_SV27R,   0x574,  0x100),
0353         RSND_GEN_M_REG(CTU_SV30R,   0x578,  0x100),
0354         RSND_GEN_M_REG(CTU_SV31R,   0x57c,  0x100),
0355         RSND_GEN_M_REG(CTU_SV32R,   0x580,  0x100),
0356         RSND_GEN_M_REG(CTU_SV33R,   0x584,  0x100),
0357         RSND_GEN_M_REG(CTU_SV34R,   0x588,  0x100),
0358         RSND_GEN_M_REG(CTU_SV35R,   0x58c,  0x100),
0359         RSND_GEN_M_REG(CTU_SV36R,   0x590,  0x100),
0360         RSND_GEN_M_REG(CTU_SV37R,   0x594,  0x100),
0361         RSND_GEN_M_REG(MIX_SWRSR,   0xd00,  0x40),
0362         RSND_GEN_M_REG(MIX_MIXIR,   0xd04,  0x40),
0363         RSND_GEN_M_REG(MIX_ADINR,   0xd08,  0x40),
0364         RSND_GEN_M_REG(MIX_MIXMR,   0xd10,  0x40),
0365         RSND_GEN_M_REG(MIX_MVPDR,   0xd14,  0x40),
0366         RSND_GEN_M_REG(MIX_MDBAR,   0xd18,  0x40),
0367         RSND_GEN_M_REG(MIX_MDBBR,   0xd1c,  0x40),
0368         RSND_GEN_M_REG(MIX_MDBCR,   0xd20,  0x40),
0369         RSND_GEN_M_REG(MIX_MDBDR,   0xd24,  0x40),
0370         RSND_GEN_M_REG(MIX_MDBER,   0xd28,  0x40),
0371         RSND_GEN_M_REG(DVC_SWRSR,   0xe00,  0x100),
0372         RSND_GEN_M_REG(DVC_DVUIR,   0xe04,  0x100),
0373         RSND_GEN_M_REG(DVC_ADINR,   0xe08,  0x100),
0374         RSND_GEN_M_REG(DVC_DVUCR,   0xe10,  0x100),
0375         RSND_GEN_M_REG(DVC_ZCMCR,   0xe14,  0x100),
0376         RSND_GEN_M_REG(DVC_VRCTR,   0xe18,  0x100),
0377         RSND_GEN_M_REG(DVC_VRPDR,   0xe1c,  0x100),
0378         RSND_GEN_M_REG(DVC_VRDBR,   0xe20,  0x100),
0379         RSND_GEN_M_REG(DVC_VOL0R,   0xe28,  0x100),
0380         RSND_GEN_M_REG(DVC_VOL1R,   0xe2c,  0x100),
0381         RSND_GEN_M_REG(DVC_VOL2R,   0xe30,  0x100),
0382         RSND_GEN_M_REG(DVC_VOL3R,   0xe34,  0x100),
0383         RSND_GEN_M_REG(DVC_VOL4R,   0xe38,  0x100),
0384         RSND_GEN_M_REG(DVC_VOL5R,   0xe3c,  0x100),
0385         RSND_GEN_M_REG(DVC_VOL6R,   0xe40,  0x100),
0386         RSND_GEN_M_REG(DVC_VOL7R,   0xe44,  0x100),
0387         RSND_GEN_M_REG(DVC_DVUER,   0xe48,  0x100),
0388     };
0389     static const struct rsnd_regmap_field_conf conf_adg[] = {
0390         RSND_GEN_S_REG(BRRA,        0x00),
0391         RSND_GEN_S_REG(BRRB,        0x04),
0392         RSND_GEN_S_REG(BRGCKR,      0x08),
0393         RSND_GEN_S_REG(AUDIO_CLK_SEL0,  0x0c),
0394         RSND_GEN_S_REG(AUDIO_CLK_SEL1,  0x10),
0395         RSND_GEN_S_REG(AUDIO_CLK_SEL2,  0x14),
0396         RSND_GEN_S_REG(DIV_EN,      0x30),
0397         RSND_GEN_S_REG(SRCIN_TIMSEL0,   0x34),
0398         RSND_GEN_S_REG(SRCIN_TIMSEL1,   0x38),
0399         RSND_GEN_S_REG(SRCIN_TIMSEL2,   0x3c),
0400         RSND_GEN_S_REG(SRCIN_TIMSEL3,   0x40),
0401         RSND_GEN_S_REG(SRCIN_TIMSEL4,   0x44),
0402         RSND_GEN_S_REG(SRCOUT_TIMSEL0,  0x48),
0403         RSND_GEN_S_REG(SRCOUT_TIMSEL1,  0x4c),
0404         RSND_GEN_S_REG(SRCOUT_TIMSEL2,  0x50),
0405         RSND_GEN_S_REG(SRCOUT_TIMSEL3,  0x54),
0406         RSND_GEN_S_REG(SRCOUT_TIMSEL4,  0x58),
0407         RSND_GEN_S_REG(CMDOUT_TIMSEL,   0x5c),
0408     };
0409     static const struct rsnd_regmap_field_conf conf_ssi[] = {
0410         RSND_GEN_M_REG(SSICR,       0x00,   0x40),
0411         RSND_GEN_M_REG(SSISR,       0x04,   0x40),
0412         RSND_GEN_M_REG(SSITDR,      0x08,   0x40),
0413         RSND_GEN_M_REG(SSIRDR,      0x0c,   0x40),
0414         RSND_GEN_M_REG(SSIWSR,      0x20,   0x40),
0415     };
0416     int ret_ssiu;
0417     int ret_scu;
0418     int ret_adg;
0419     int ret_ssi;
0420 
0421     ret_ssiu = rsnd_gen_regmap_init(priv, 10, RSND_GEN2_SSIU, "ssiu", conf_ssiu);
0422     ret_scu  = rsnd_gen_regmap_init(priv, 10, RSND_GEN2_SCU,  "scu",  conf_scu);
0423     ret_adg  = rsnd_gen_regmap_init(priv, 10, RSND_GEN2_ADG,  "adg",  conf_adg);
0424     ret_ssi  = rsnd_gen_regmap_init(priv, 10, RSND_GEN2_SSI,  "ssi",  conf_ssi);
0425     if (ret_ssiu < 0 ||
0426         ret_scu  < 0 ||
0427         ret_adg  < 0 ||
0428         ret_ssi  < 0)
0429         return ret_ssiu | ret_scu | ret_adg | ret_ssi;
0430 
0431     return 0;
0432 }
0433 
0434 /*
0435  *      Gen1
0436  */
0437 
0438 static int rsnd_gen1_probe(struct rsnd_priv *priv)
0439 {
0440     static const struct rsnd_regmap_field_conf conf_adg[] = {
0441         RSND_GEN_S_REG(BRRA,        0x00),
0442         RSND_GEN_S_REG(BRRB,        0x04),
0443         RSND_GEN_S_REG(BRGCKR,      0x08),
0444         RSND_GEN_S_REG(AUDIO_CLK_SEL0,  0x0c),
0445         RSND_GEN_S_REG(AUDIO_CLK_SEL1,  0x10),
0446     };
0447     static const struct rsnd_regmap_field_conf conf_ssi[] = {
0448         RSND_GEN_M_REG(SSICR,       0x00,   0x40),
0449         RSND_GEN_M_REG(SSISR,       0x04,   0x40),
0450         RSND_GEN_M_REG(SSITDR,      0x08,   0x40),
0451         RSND_GEN_M_REG(SSIRDR,      0x0c,   0x40),
0452         RSND_GEN_M_REG(SSIWSR,      0x20,   0x40),
0453     };
0454     int ret_adg;
0455     int ret_ssi;
0456 
0457     ret_adg  = rsnd_gen_regmap_init(priv, 9, RSND_GEN1_ADG, "adg", conf_adg);
0458     ret_ssi  = rsnd_gen_regmap_init(priv, 9, RSND_GEN1_SSI, "ssi", conf_ssi);
0459     if (ret_adg  < 0 ||
0460         ret_ssi  < 0)
0461         return ret_adg | ret_ssi;
0462 
0463     return 0;
0464 }
0465 
0466 /*
0467  *      Gen
0468  */
0469 int rsnd_gen_probe(struct rsnd_priv *priv)
0470 {
0471     struct device *dev = rsnd_priv_to_dev(priv);
0472     struct rsnd_gen *gen;
0473     int ret;
0474 
0475     gen = devm_kzalloc(dev, sizeof(*gen), GFP_KERNEL);
0476     if (!gen)
0477         return -ENOMEM;
0478 
0479     priv->gen = gen;
0480 
0481     ret = -ENODEV;
0482     if (rsnd_is_gen1(priv))
0483         ret = rsnd_gen1_probe(priv);
0484     else if (rsnd_is_gen2(priv) ||
0485          rsnd_is_gen3(priv))
0486         ret = rsnd_gen2_probe(priv);
0487 
0488     if (ret < 0)
0489         dev_err(dev, "unknown generation R-Car sound device\n");
0490 
0491     return ret;
0492 }
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