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0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // Helper routines for R-Car sound ADG.
0004 //
0005 //  Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
0006 #include <linux/clk-provider.h>
0007 #include <linux/clkdev.h>
0008 #include "rsnd.h"
0009 
0010 #define CLKA    0
0011 #define CLKB    1
0012 #define CLKC    2
0013 #define CLKI    3
0014 #define CLKMAX  4
0015 
0016 #define CLKOUT  0
0017 #define CLKOUT1 1
0018 #define CLKOUT2 2
0019 #define CLKOUT3 3
0020 #define CLKOUTMAX 4
0021 
0022 #define BRRx_MASK(x) (0x3FF & x)
0023 
0024 static struct rsnd_mod_ops adg_ops = {
0025     .name = "adg",
0026 };
0027 
0028 struct rsnd_adg {
0029     struct clk *clk[CLKMAX];
0030     struct clk *clkout[CLKOUTMAX];
0031     struct clk *null_clk;
0032     struct clk_onecell_data onecell;
0033     struct rsnd_mod mod;
0034     int clk_rate[CLKMAX];
0035     u32 flags;
0036     u32 ckr;
0037     u32 rbga;
0038     u32 rbgb;
0039 
0040     int rbga_rate_for_441khz; /* RBGA */
0041     int rbgb_rate_for_48khz;  /* RBGB */
0042 };
0043 
0044 #define LRCLK_ASYNC (1 << 0)
0045 #define AUDIO_OUT_48    (1 << 1)
0046 
0047 #define for_each_rsnd_clk(pos, adg, i)      \
0048     for (i = 0;             \
0049          (i < CLKMAX) &&            \
0050          ((pos) = adg->clk[i]);     \
0051          i++)
0052 #define for_each_rsnd_clkout(pos, adg, i)   \
0053     for (i = 0;             \
0054          (i < CLKOUTMAX) &&         \
0055          ((pos) = adg->clkout[i]);  \
0056          i++)
0057 #define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)
0058 
0059 static const char * const clk_name[] = {
0060     [CLKA]  = "clk_a",
0061     [CLKB]  = "clk_b",
0062     [CLKC]  = "clk_c",
0063     [CLKI]  = "clk_i",
0064 };
0065 
0066 static u32 rsnd_adg_calculate_rbgx(unsigned long div)
0067 {
0068     int i;
0069 
0070     if (!div)
0071         return 0;
0072 
0073     for (i = 3; i >= 0; i--) {
0074         int ratio = 2 << (i * 2);
0075         if (0 == (div % ratio))
0076             return (u32)((i << 8) | ((div / ratio) - 1));
0077     }
0078 
0079     return ~0;
0080 }
0081 
0082 static u32 rsnd_adg_ssi_ws_timing_gen2(struct rsnd_dai_stream *io)
0083 {
0084     struct rsnd_mod *ssi_mod = rsnd_io_to_mod_ssi(io);
0085     int id = rsnd_mod_id(ssi_mod);
0086     int ws = id;
0087 
0088     if (rsnd_ssi_is_pin_sharing(io)) {
0089         switch (id) {
0090         case 1:
0091         case 2:
0092         case 9:
0093             ws = 0;
0094             break;
0095         case 4:
0096             ws = 3;
0097             break;
0098         case 8:
0099             ws = 7;
0100             break;
0101         }
0102     }
0103 
0104     return (0x6 + ws) << 8;
0105 }
0106 
0107 static void __rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv,
0108                        struct rsnd_dai_stream *io,
0109                        unsigned int target_rate,
0110                        unsigned int *target_val,
0111                        unsigned int *target_en)
0112 {
0113     struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
0114     struct device *dev = rsnd_priv_to_dev(priv);
0115     int sel;
0116     unsigned int val, en;
0117     unsigned int min, diff;
0118     unsigned int sel_rate[] = {
0119         adg->clk_rate[CLKA],    /* 0000: CLKA */
0120         adg->clk_rate[CLKB],    /* 0001: CLKB */
0121         adg->clk_rate[CLKC],    /* 0010: CLKC */
0122         adg->rbga_rate_for_441khz,  /* 0011: RBGA */
0123         adg->rbgb_rate_for_48khz,   /* 0100: RBGB */
0124     };
0125 
0126     min = ~0;
0127     val = 0;
0128     en = 0;
0129     for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) {
0130         int idx = 0;
0131         int step = 2;
0132         int div;
0133 
0134         if (!sel_rate[sel])
0135             continue;
0136 
0137         for (div = 2; div <= 98304; div += step) {
0138             diff = abs(target_rate - sel_rate[sel] / div);
0139             if (min > diff) {
0140                 val = (sel << 8) | idx;
0141                 min = diff;
0142                 en = 1 << (sel + 1); /* fixme */
0143             }
0144 
0145             /*
0146              * step of 0_0000 / 0_0001 / 0_1101
0147              * are out of order
0148              */
0149             if ((idx > 2) && (idx % 2))
0150                 step *= 2;
0151             if (idx == 0x1c) {
0152                 div += step;
0153                 step *= 2;
0154             }
0155             idx++;
0156         }
0157     }
0158 
0159     if (min == ~0) {
0160         dev_err(dev, "no Input clock\n");
0161         return;
0162     }
0163 
0164     *target_val = val;
0165     if (target_en)
0166         *target_en = en;
0167 }
0168 
0169 static void rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv,
0170                        struct rsnd_dai_stream *io,
0171                        unsigned int in_rate,
0172                        unsigned int out_rate,
0173                        u32 *in, u32 *out, u32 *en)
0174 {
0175     struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io);
0176     unsigned int target_rate;
0177     u32 *target_val;
0178     u32 _in;
0179     u32 _out;
0180     u32 _en;
0181 
0182     /* default = SSI WS */
0183     _in =
0184     _out = rsnd_adg_ssi_ws_timing_gen2(io);
0185 
0186     target_rate = 0;
0187     target_val = NULL;
0188     _en = 0;
0189     if (runtime->rate != in_rate) {
0190         target_rate = out_rate;
0191         target_val  = &_out;
0192     } else if (runtime->rate != out_rate) {
0193         target_rate = in_rate;
0194         target_val  = &_in;
0195     }
0196 
0197     if (target_rate)
0198         __rsnd_adg_get_timesel_ratio(priv, io,
0199                          target_rate,
0200                          target_val, &_en);
0201 
0202     if (in)
0203         *in = _in;
0204     if (out)
0205         *out = _out;
0206     if (en)
0207         *en = _en;
0208 }
0209 
0210 int rsnd_adg_set_cmd_timsel_gen2(struct rsnd_mod *cmd_mod,
0211                  struct rsnd_dai_stream *io)
0212 {
0213     struct rsnd_priv *priv = rsnd_mod_to_priv(cmd_mod);
0214     struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
0215     struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
0216     int id = rsnd_mod_id(cmd_mod);
0217     int shift = (id % 2) ? 16 : 0;
0218     u32 mask, val;
0219 
0220     rsnd_adg_get_timesel_ratio(priv, io,
0221                    rsnd_src_get_in_rate(priv, io),
0222                    rsnd_src_get_out_rate(priv, io),
0223                    NULL, &val, NULL);
0224 
0225     val  = val  << shift;
0226     mask = 0x0f1f   << shift;
0227 
0228     rsnd_mod_bset(adg_mod, CMDOUT_TIMSEL, mask, val);
0229 
0230     return 0;
0231 }
0232 
0233 int rsnd_adg_set_src_timesel_gen2(struct rsnd_mod *src_mod,
0234                   struct rsnd_dai_stream *io,
0235                   unsigned int in_rate,
0236                   unsigned int out_rate)
0237 {
0238     struct rsnd_priv *priv = rsnd_mod_to_priv(src_mod);
0239     struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
0240     struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
0241     u32 in, out;
0242     u32 mask, en;
0243     int id = rsnd_mod_id(src_mod);
0244     int shift = (id % 2) ? 16 : 0;
0245 
0246     rsnd_mod_confirm_src(src_mod);
0247 
0248     rsnd_adg_get_timesel_ratio(priv, io,
0249                    in_rate, out_rate,
0250                    &in, &out, &en);
0251 
0252     in   = in   << shift;
0253     out  = out  << shift;
0254     mask = 0x0f1f   << shift;
0255 
0256     rsnd_mod_bset(adg_mod, SRCIN_TIMSEL(id / 2),  mask, in);
0257     rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL(id / 2), mask, out);
0258 
0259     if (en)
0260         rsnd_mod_bset(adg_mod, DIV_EN, en, en);
0261 
0262     return 0;
0263 }
0264 
0265 static void rsnd_adg_set_ssi_clk(struct rsnd_mod *ssi_mod, u32 val)
0266 {
0267     struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
0268     struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
0269     struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
0270     struct device *dev = rsnd_priv_to_dev(priv);
0271     int id = rsnd_mod_id(ssi_mod);
0272     int shift = (id % 4) * 8;
0273     u32 mask = 0xFF << shift;
0274 
0275     rsnd_mod_confirm_ssi(ssi_mod);
0276 
0277     val = val << shift;
0278 
0279     /*
0280      * SSI 8 is not connected to ADG.
0281      * it works with SSI 7
0282      */
0283     if (id == 8)
0284         return;
0285 
0286     rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL(id / 4), mask, val);
0287 
0288     dev_dbg(dev, "AUDIO_CLK_SEL is 0x%x\n", val);
0289 }
0290 
0291 int rsnd_adg_clk_query(struct rsnd_priv *priv, unsigned int rate)
0292 {
0293     struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
0294     int i;
0295     int sel_table[] = {
0296         [CLKA] = 0x1,
0297         [CLKB] = 0x2,
0298         [CLKC] = 0x3,
0299         [CLKI] = 0x0,
0300     };
0301 
0302     /*
0303      * find suitable clock from
0304      * AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI.
0305      */
0306     for (i = 0; i < CLKMAX; i++)
0307         if (rate == adg->clk_rate[i])
0308             return sel_table[i];
0309 
0310     /*
0311      * find divided clock from BRGA/BRGB
0312      */
0313     if (rate == adg->rbga_rate_for_441khz)
0314         return 0x10;
0315 
0316     if (rate == adg->rbgb_rate_for_48khz)
0317         return 0x20;
0318 
0319     return -EIO;
0320 }
0321 
0322 int rsnd_adg_ssi_clk_stop(struct rsnd_mod *ssi_mod)
0323 {
0324     rsnd_adg_set_ssi_clk(ssi_mod, 0);
0325 
0326     return 0;
0327 }
0328 
0329 int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *ssi_mod, unsigned int rate)
0330 {
0331     struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
0332     struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
0333     struct device *dev = rsnd_priv_to_dev(priv);
0334     struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
0335     int data;
0336     u32 ckr = 0;
0337 
0338     data = rsnd_adg_clk_query(priv, rate);
0339     if (data < 0)
0340         return data;
0341 
0342     rsnd_adg_set_ssi_clk(ssi_mod, data);
0343 
0344     if (rsnd_flags_has(adg, LRCLK_ASYNC)) {
0345         if (rsnd_flags_has(adg, AUDIO_OUT_48))
0346             ckr = 0x80000000;
0347     } else {
0348         if (0 == (rate % 8000))
0349             ckr = 0x80000000;
0350     }
0351 
0352     rsnd_mod_bset(adg_mod, BRGCKR, 0x80770000, adg->ckr | ckr);
0353     rsnd_mod_write(adg_mod, BRRA,  adg->rbga);
0354     rsnd_mod_write(adg_mod, BRRB,  adg->rbgb);
0355 
0356     dev_dbg(dev, "CLKOUT is based on BRG%c (= %dHz)\n",
0357         (ckr) ? 'B' : 'A',
0358         (ckr) ? adg->rbgb_rate_for_48khz :
0359             adg->rbga_rate_for_441khz);
0360 
0361     return 0;
0362 }
0363 
0364 void rsnd_adg_clk_control(struct rsnd_priv *priv, int enable)
0365 {
0366     struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
0367     struct clk *clk;
0368     int i;
0369 
0370     for_each_rsnd_clk(clk, adg, i) {
0371         if (enable) {
0372             clk_prepare_enable(clk);
0373 
0374             /*
0375              * We shouldn't use clk_get_rate() under
0376              * atomic context. Let's keep it when
0377              * rsnd_adg_clk_enable() was called
0378              */
0379             adg->clk_rate[i] = clk_get_rate(clk);
0380         } else {
0381             clk_disable_unprepare(clk);
0382         }
0383     }
0384 }
0385 
0386 static struct clk *rsnd_adg_create_null_clk(struct rsnd_priv *priv,
0387                         const char * const name,
0388                         const char *parent)
0389 {
0390     struct device *dev = rsnd_priv_to_dev(priv);
0391     struct clk *clk;
0392 
0393     clk = clk_register_fixed_rate(dev, name, parent, 0, 0);
0394     if (IS_ERR_OR_NULL(clk)) {
0395         dev_err(dev, "create null clk error\n");
0396         return ERR_CAST(clk);
0397     }
0398 
0399     return clk;
0400 }
0401 
0402 static struct clk *rsnd_adg_null_clk_get(struct rsnd_priv *priv)
0403 {
0404     struct rsnd_adg *adg = priv->adg;
0405 
0406     if (!adg->null_clk) {
0407         static const char * const name = "rsnd_adg_null";
0408 
0409         adg->null_clk = rsnd_adg_create_null_clk(priv, name, NULL);
0410     }
0411 
0412     return adg->null_clk;
0413 }
0414 
0415 static void rsnd_adg_null_clk_clean(struct rsnd_priv *priv)
0416 {
0417     struct rsnd_adg *adg = priv->adg;
0418 
0419     if (adg->null_clk)
0420         clk_unregister_fixed_rate(adg->null_clk);
0421 }
0422 
0423 static int rsnd_adg_get_clkin(struct rsnd_priv *priv)
0424 {
0425     struct rsnd_adg *adg = priv->adg;
0426     struct device *dev = rsnd_priv_to_dev(priv);
0427     struct clk *clk;
0428     int i;
0429 
0430     for (i = 0; i < CLKMAX; i++) {
0431         clk = devm_clk_get(dev, clk_name[i]);
0432 
0433         if (IS_ERR_OR_NULL(clk))
0434             clk = rsnd_adg_null_clk_get(priv);
0435         if (IS_ERR_OR_NULL(clk))
0436             goto err;
0437 
0438         adg->clk[i] = clk;
0439     }
0440 
0441     return 0;
0442 
0443 err:
0444     dev_err(dev, "adg clock IN get failed\n");
0445 
0446     rsnd_adg_null_clk_clean(priv);
0447 
0448     return -EIO;
0449 }
0450 
0451 static void rsnd_adg_unregister_clkout(struct rsnd_priv *priv)
0452 {
0453     struct rsnd_adg *adg = priv->adg;
0454     struct clk *clk;
0455     int i;
0456 
0457     for_each_rsnd_clkout(clk, adg, i)
0458         clk_unregister_fixed_rate(clk);
0459 }
0460 
0461 static int rsnd_adg_get_clkout(struct rsnd_priv *priv)
0462 {
0463     struct rsnd_adg *adg = priv->adg;
0464     struct clk *clk;
0465     struct device *dev = rsnd_priv_to_dev(priv);
0466     struct device_node *np = dev->of_node;
0467     struct property *prop;
0468     u32 ckr, rbgx, rbga, rbgb;
0469     u32 rate, div;
0470 #define REQ_SIZE 2
0471     u32 req_rate[REQ_SIZE] = {};
0472     uint32_t count = 0;
0473     unsigned long req_48kHz_rate, req_441kHz_rate;
0474     int i, req_size;
0475     const char *parent_clk_name = NULL;
0476     static const char * const clkout_name[] = {
0477         [CLKOUT]  = "audio_clkout",
0478         [CLKOUT1] = "audio_clkout1",
0479         [CLKOUT2] = "audio_clkout2",
0480         [CLKOUT3] = "audio_clkout3",
0481     };
0482     int brg_table[] = {
0483         [CLKA] = 0x0,
0484         [CLKB] = 0x1,
0485         [CLKC] = 0x4,
0486         [CLKI] = 0x2,
0487     };
0488 
0489     ckr = 0;
0490     rbga = 2; /* default 1/6 */
0491     rbgb = 2; /* default 1/6 */
0492 
0493     /*
0494      * ADG supports BRRA/BRRB output only
0495      * this means all clkout0/1/2/3 will be same rate
0496      */
0497     prop = of_find_property(np, "clock-frequency", NULL);
0498     if (!prop)
0499         goto rsnd_adg_get_clkout_end;
0500 
0501     req_size = prop->length / sizeof(u32);
0502     if (req_size > REQ_SIZE) {
0503         dev_err(dev, "too many clock-frequency\n");
0504         return -EINVAL;
0505     }
0506 
0507     of_property_read_u32_array(np, "clock-frequency", req_rate, req_size);
0508     req_48kHz_rate = 0;
0509     req_441kHz_rate = 0;
0510     for (i = 0; i < req_size; i++) {
0511         if (0 == (req_rate[i] % 44100))
0512             req_441kHz_rate = req_rate[i];
0513         if (0 == (req_rate[i] % 48000))
0514             req_48kHz_rate = req_rate[i];
0515     }
0516 
0517     if (req_rate[0] % 48000 == 0)
0518         rsnd_flags_set(adg, AUDIO_OUT_48);
0519 
0520     if (of_get_property(np, "clkout-lr-asynchronous", NULL))
0521         rsnd_flags_set(adg, LRCLK_ASYNC);
0522 
0523     /*
0524      * This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC
0525      * have 44.1kHz or 48kHz base clocks for now.
0526      *
0527      * SSI itself can divide parent clock by 1/1 - 1/16
0528      * see
0529      *  rsnd_adg_ssi_clk_try_start()
0530      *  rsnd_ssi_master_clk_start()
0531      */
0532     adg->rbga_rate_for_441khz   = 0;
0533     adg->rbgb_rate_for_48khz    = 0;
0534     for_each_rsnd_clk(clk, adg, i) {
0535         rate = clk_get_rate(clk);
0536 
0537         if (0 == rate) /* not used */
0538             continue;
0539 
0540         /* RBGA */
0541         if (!adg->rbga_rate_for_441khz && (0 == rate % 44100)) {
0542             div = 6;
0543             if (req_441kHz_rate)
0544                 div = rate / req_441kHz_rate;
0545             rbgx = rsnd_adg_calculate_rbgx(div);
0546             if (BRRx_MASK(rbgx) == rbgx) {
0547                 rbga = rbgx;
0548                 adg->rbga_rate_for_441khz = rate / div;
0549                 ckr |= brg_table[i] << 20;
0550                 if (req_441kHz_rate &&
0551                     !rsnd_flags_has(adg, AUDIO_OUT_48))
0552                     parent_clk_name = __clk_get_name(clk);
0553             }
0554         }
0555 
0556         /* RBGB */
0557         if (!adg->rbgb_rate_for_48khz && (0 == rate % 48000)) {
0558             div = 6;
0559             if (req_48kHz_rate)
0560                 div = rate / req_48kHz_rate;
0561             rbgx = rsnd_adg_calculate_rbgx(div);
0562             if (BRRx_MASK(rbgx) == rbgx) {
0563                 rbgb = rbgx;
0564                 adg->rbgb_rate_for_48khz = rate / div;
0565                 ckr |= brg_table[i] << 16;
0566                 if (req_48kHz_rate &&
0567                     rsnd_flags_has(adg, AUDIO_OUT_48))
0568                     parent_clk_name = __clk_get_name(clk);
0569             }
0570         }
0571     }
0572 
0573     /*
0574      * ADG supports BRRA/BRRB output only.
0575      * this means all clkout0/1/2/3 will be * same rate
0576      */
0577 
0578     of_property_read_u32(np, "#clock-cells", &count);
0579     /*
0580      * for clkout
0581      */
0582     if (!count) {
0583         clk = clk_register_fixed_rate(dev, clkout_name[CLKOUT],
0584                           parent_clk_name, 0, req_rate[0]);
0585         if (IS_ERR_OR_NULL(clk))
0586             goto err;
0587 
0588         adg->clkout[CLKOUT] = clk;
0589         of_clk_add_provider(np, of_clk_src_simple_get, clk);
0590     }
0591     /*
0592      * for clkout0/1/2/3
0593      */
0594     else {
0595         for (i = 0; i < CLKOUTMAX; i++) {
0596             clk = clk_register_fixed_rate(dev, clkout_name[i],
0597                               parent_clk_name, 0,
0598                               req_rate[0]);
0599             if (IS_ERR_OR_NULL(clk))
0600                 goto err;
0601 
0602             adg->clkout[i] = clk;
0603         }
0604         adg->onecell.clks   = adg->clkout;
0605         adg->onecell.clk_num    = CLKOUTMAX;
0606         of_clk_add_provider(np, of_clk_src_onecell_get,
0607                     &adg->onecell);
0608     }
0609 
0610 rsnd_adg_get_clkout_end:
0611     adg->ckr = ckr;
0612     adg->rbga = rbga;
0613     adg->rbgb = rbgb;
0614 
0615     return 0;
0616 
0617 err:
0618     dev_err(dev, "adg clock OUT get failed\n");
0619 
0620     rsnd_adg_unregister_clkout(priv);
0621 
0622     return -EIO;
0623 }
0624 
0625 #if defined(DEBUG) || defined(CONFIG_DEBUG_FS)
0626 __printf(3, 4)
0627 static void dbg_msg(struct device *dev, struct seq_file *m,
0628                    const char *fmt, ...)
0629 {
0630     char msg[128];
0631     va_list args;
0632 
0633     va_start(args, fmt);
0634     vsnprintf(msg, sizeof(msg), fmt, args);
0635     va_end(args);
0636 
0637     if (m)
0638         seq_puts(m, msg);
0639     else
0640         dev_dbg(dev, "%s", msg);
0641 }
0642 
0643 void rsnd_adg_clk_dbg_info(struct rsnd_priv *priv, struct seq_file *m)
0644 {
0645     struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
0646     struct device *dev = rsnd_priv_to_dev(priv);
0647     struct clk *clk;
0648     int i;
0649 
0650     for_each_rsnd_clk(clk, adg, i)
0651         dbg_msg(dev, m, "%s    : %pa : %ld\n",
0652             clk_name[i], clk, clk_get_rate(clk));
0653 
0654     dbg_msg(dev, m, "BRGCKR = 0x%08x, BRRA/BRRB = 0x%x/0x%x\n",
0655         adg->ckr, adg->rbga, adg->rbgb);
0656     dbg_msg(dev, m, "BRGA (for 44100 base) = %d\n", adg->rbga_rate_for_441khz);
0657     dbg_msg(dev, m, "BRGB (for 48000 base) = %d\n", adg->rbgb_rate_for_48khz);
0658 
0659     /*
0660      * Actual CLKOUT will be exchanged in rsnd_adg_ssi_clk_try_start()
0661      * by BRGCKR::BRGCKR_31
0662      */
0663     for_each_rsnd_clkout(clk, adg, i)
0664         dbg_msg(dev, m, "clkout %d : %pa : %ld\n", i,
0665             clk, clk_get_rate(clk));
0666 }
0667 #else
0668 #define rsnd_adg_clk_dbg_info(priv, m)
0669 #endif
0670 
0671 int rsnd_adg_probe(struct rsnd_priv *priv)
0672 {
0673     struct rsnd_adg *adg;
0674     struct device *dev = rsnd_priv_to_dev(priv);
0675     int ret;
0676 
0677     adg = devm_kzalloc(dev, sizeof(*adg), GFP_KERNEL);
0678     if (!adg)
0679         return -ENOMEM;
0680 
0681     ret = rsnd_mod_init(priv, &adg->mod, &adg_ops,
0682               NULL, 0, 0);
0683     if (ret)
0684         return ret;
0685 
0686     priv->adg = adg;
0687 
0688     ret = rsnd_adg_get_clkin(priv);
0689     if (ret)
0690         return ret;
0691 
0692     ret = rsnd_adg_get_clkout(priv);
0693     if (ret)
0694         return ret;
0695 
0696     rsnd_adg_clk_enable(priv);
0697     rsnd_adg_clk_dbg_info(priv, NULL);
0698 
0699     return 0;
0700 }
0701 
0702 void rsnd_adg_remove(struct rsnd_priv *priv)
0703 {
0704     struct device *dev = rsnd_priv_to_dev(priv);
0705     struct device_node *np = dev->of_node;
0706 
0707     rsnd_adg_unregister_clkout(priv);
0708 
0709     of_clk_del_provider(np);
0710 
0711     rsnd_adg_clk_disable(priv);
0712 
0713     /* It should be called after rsnd_adg_clk_disable() */
0714     rsnd_adg_null_clk_clean(priv);
0715 }
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