soc/samsung/regs-i2s-v2.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright 2007 Simtec Electronics <linux@simtec.co.uk>
0004  *  http://armlinux.simtec.co.uk/
0005  *
0006  * S3C2412 IIS register definition
0007  */
0008
0009 #ifndef __ASM_ARCH_REGS_S3C2412_IIS_H
0010 #define __ASM_ARCH_REGS_S3C2412_IIS_H
0011
0012 #define S3C2412_IISCON          (0x00)
0013 #define S3C2412_IISMOD          (0x04)
0014 #define S3C2412_IISFIC          (0x08)
0015 #define S3C2412_IISPSR          (0x0C)
0016 #define S3C2412_IISTXD          (0x10)
0017 #define S3C2412_IISRXD          (0x14)
0018
0019 #define S5PC1XX_IISFICS     0x18
0020 #define S5PC1XX_IISTXDS     0x1C
0021
0022 #define S5PC1XX_IISCON_SW_RST       (1 << 31)
0023 #define S5PC1XX_IISCON_FRXOFSTATUS  (1 << 26)
0024 #define S5PC1XX_IISCON_FRXORINTEN   (1 << 25)
0025 #define S5PC1XX_IISCON_FTXSURSTAT   (1 << 24)
0026 #define S5PC1XX_IISCON_FTXSURINTEN  (1 << 23)
0027 #define S5PC1XX_IISCON_TXSDMAPAUSE  (1 << 20)
0028 #define S5PC1XX_IISCON_TXSDMACTIVE  (1 << 18)
0029
0030 #define S3C64XX_IISCON_FTXURSTATUS  (1 << 17)
0031 #define S3C64XX_IISCON_FTXURINTEN   (1 << 16)
0032 #define S3C64XX_IISCON_TXFIFO2_EMPTY    (1 << 15)
0033 #define S3C64XX_IISCON_TXFIFO1_EMPTY    (1 << 14)
0034 #define S3C64XX_IISCON_TXFIFO2_FULL (1 << 13)
0035 #define S3C64XX_IISCON_TXFIFO1_FULL (1 << 12)
0036
0037 #define S3C2412_IISCON_LRINDEX      (1 << 11)
0038 #define S3C2412_IISCON_TXFIFO_EMPTY (1 << 10)
0039 #define S3C2412_IISCON_RXFIFO_EMPTY (1 << 9)
0040 #define S3C2412_IISCON_TXFIFO_FULL  (1 << 8)
0041 #define S3C2412_IISCON_RXFIFO_FULL  (1 << 7)
0042 #define S3C2412_IISCON_TXDMA_PAUSE  (1 << 6)
0043 #define S3C2412_IISCON_RXDMA_PAUSE  (1 << 5)
0044 #define S3C2412_IISCON_TXCH_PAUSE   (1 << 4)
0045 #define S3C2412_IISCON_RXCH_PAUSE   (1 << 3)
0046 #define S3C2412_IISCON_TXDMA_ACTIVE (1 << 2)
0047 #define S3C2412_IISCON_RXDMA_ACTIVE (1 << 1)
0048 #define S3C2412_IISCON_IIS_ACTIVE   (1 << 0)
0049
0050 #define S5PC1XX_IISMOD_OPCLK_CDCLK_OUT  (0 << 30)
0051 #define S5PC1XX_IISMOD_OPCLK_CDCLK_IN   (1 << 30)
0052 #define S5PC1XX_IISMOD_OPCLK_BCLK_OUT   (2 << 30)
0053 #define S5PC1XX_IISMOD_OPCLK_PCLK   (3 << 30)
0054 #define S5PC1XX_IISMOD_OPCLK_MASK   (3 << 30)
0055 #define S5PC1XX_IISMOD_TXS_IDMA     (1 << 28) /* Sec_TXFIFO use I-DMA */
0056 #define S5PC1XX_IISMOD_BLCS_MASK    0x3
0057 #define S5PC1XX_IISMOD_BLCS_SHIFT   26
0058 #define S5PC1XX_IISMOD_BLCP_MASK    0x3
0059 #define S5PC1XX_IISMOD_BLCP_SHIFT   24
0060
0061 #define S3C64XX_IISMOD_C2DD_HHALF   (1 << 21) /* Discard Higher-half */
0062 #define S3C64XX_IISMOD_C2DD_LHALF   (1 << 20) /* Discard Lower-half */
0063 #define S3C64XX_IISMOD_C1DD_HHALF   (1 << 19)
0064 #define S3C64XX_IISMOD_C1DD_LHALF   (1 << 18)
0065 #define S3C64XX_IISMOD_DC2_EN       (1 << 17)
0066 #define S3C64XX_IISMOD_DC1_EN       (1 << 16)
0067 #define S3C64XX_IISMOD_BLC_16BIT    (0 << 13)
0068 #define S3C64XX_IISMOD_BLC_8BIT     (1 << 13)
0069 #define S3C64XX_IISMOD_BLC_24BIT    (2 << 13)
0070 #define S3C64XX_IISMOD_BLC_MASK     (3 << 13)
0071
0072 #define S3C2412_IISMOD_IMS_SYSMUX   (1 << 10)
0073 #define S3C2412_IISMOD_SLAVE        (1 << 11)
0074 #define S3C2412_IISMOD_MODE_TXONLY  (0 << 8)
0075 #define S3C2412_IISMOD_MODE_RXONLY  (1 << 8)
0076 #define S3C2412_IISMOD_MODE_TXRX    (2 << 8)
0077 #define S3C2412_IISMOD_MODE_MASK    (3 << 8)
0078 #define S3C2412_IISMOD_LR_LLOW      (0 << 7)
0079 #define S3C2412_IISMOD_LR_RLOW      (1 << 7)
0080 #define S3C2412_IISMOD_SDF_IIS      (0 << 5)
0081 #define S3C2412_IISMOD_SDF_MSB      (1 << 5)
0082 #define S3C2412_IISMOD_SDF_LSB      (2 << 5)
0083 #define S3C2412_IISMOD_SDF_MASK     (3 << 5)
0084 #define S3C2412_IISMOD_RCLK_256FS   (0 << 3)
0085 #define S3C2412_IISMOD_RCLK_512FS   (1 << 3)
0086 #define S3C2412_IISMOD_RCLK_384FS   (2 << 3)
0087 #define S3C2412_IISMOD_RCLK_768FS   (3 << 3)
0088 #define S3C2412_IISMOD_RCLK_MASK    (3 << 3)
0089 #define S3C2412_IISMOD_BCLK_32FS    (0 << 1)
0090 #define S3C2412_IISMOD_BCLK_48FS    (1 << 1)
0091 #define S3C2412_IISMOD_BCLK_16FS    (2 << 1)
0092 #define S3C2412_IISMOD_BCLK_24FS    (3 << 1)
0093 #define S3C2412_IISMOD_BCLK_MASK    (3 << 1)
0094 #define S3C2412_IISMOD_8BIT     (1 << 0)
0095
0096 #define S3C64XX_IISMOD_CDCLKCON     (1 << 12)
0097
0098 #define S3C2412_IISPSR_PSREN        (1 << 15)
0099
0100 #define S3C64XX_IISFIC_TX2COUNT(x)  (((x) >>  24) & 0xf)
0101 #define S3C64XX_IISFIC_TX1COUNT(x)  (((x) >>  16) & 0xf)
0102
0103 #define S3C2412_IISFIC_TXFLUSH      (1 << 15)
0104 #define S3C2412_IISFIC_RXFLUSH      (1 << 7)
0105 #define S3C2412_IISFIC_TXCOUNT(x)   (((x) >>  8) & 0xf)
0106 #define S3C2412_IISFIC_RXCOUNT(x)   (((x) >>  0) & 0xf)
0107
0108 #define S5PC1XX_IISFICS_TXFLUSH     (1 << 15)
0109 #define S5PC1XX_IISFICS_TXCOUNT(x)  (((x) >>  8) & 0x7f)
0110
0111 #endif /* __ASM_ARCH_REGS_S3C2412_IIS_H */