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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 // ALSA SoC Audio Layer - Rockchip I2S/TDM Controller driver
0003 
0004 // Copyright (c) 2018 Rockchip Electronics Co. Ltd.
0005 // Author: Sugar Zhang <sugar.zhang@rock-chips.com>
0006 // Author: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
0007 
0008 #include <linux/clk.h>
0009 #include <linux/clk-provider.h>
0010 #include <linux/delay.h>
0011 #include <linux/mfd/syscon.h>
0012 #include <linux/module.h>
0013 #include <linux/of_address.h>
0014 #include <linux/of_device.h>
0015 #include <linux/of_gpio.h>
0016 #include <linux/pm_runtime.h>
0017 #include <linux/regmap.h>
0018 #include <linux/reset.h>
0019 #include <linux/spinlock.h>
0020 #include <sound/dmaengine_pcm.h>
0021 #include <sound/pcm_params.h>
0022 
0023 #include "rockchip_i2s_tdm.h"
0024 
0025 #define DRV_NAME "rockchip-i2s-tdm"
0026 
0027 #define DEFAULT_MCLK_FS             256
0028 #define CH_GRP_MAX              4  /* The max channel 8 / 2 */
0029 #define MULTIPLEX_CH_MAX            10
0030 #define CLK_PPM_MIN             -1000
0031 #define CLK_PPM_MAX             1000
0032 
0033 #define TRCM_TXRX 0
0034 #define TRCM_TX 1
0035 #define TRCM_RX 2
0036 
0037 struct txrx_config {
0038     u32 addr;
0039     u32 reg;
0040     u32 txonly;
0041     u32 rxonly;
0042 };
0043 
0044 struct rk_i2s_soc_data {
0045     u32 softrst_offset;
0046     u32 grf_reg_offset;
0047     u32 grf_shift;
0048     int config_count;
0049     const struct txrx_config *configs;
0050     int (*init)(struct device *dev, u32 addr);
0051 };
0052 
0053 struct rk_i2s_tdm_dev {
0054     struct device *dev;
0055     struct clk *hclk;
0056     struct clk *mclk_tx;
0057     struct clk *mclk_rx;
0058     /* The mclk_tx_src is parent of mclk_tx */
0059     struct clk *mclk_tx_src;
0060     /* The mclk_rx_src is parent of mclk_rx */
0061     struct clk *mclk_rx_src;
0062     /*
0063      * The mclk_root0 and mclk_root1 are root parent and supplies for
0064      * the different FS.
0065      *
0066      * e.g:
0067      * mclk_root0 is VPLL0, used for FS=48000Hz
0068      * mclk_root1 is VPLL1, used for FS=44100Hz
0069      */
0070     struct clk *mclk_root0;
0071     struct clk *mclk_root1;
0072     struct regmap *regmap;
0073     struct regmap *grf;
0074     struct snd_dmaengine_dai_dma_data capture_dma_data;
0075     struct snd_dmaengine_dai_dma_data playback_dma_data;
0076     struct reset_control *tx_reset;
0077     struct reset_control *rx_reset;
0078     struct rk_i2s_soc_data *soc_data;
0079     bool is_master_mode;
0080     bool io_multiplex;
0081     bool mclk_calibrate;
0082     bool tdm_mode;
0083     unsigned int mclk_rx_freq;
0084     unsigned int mclk_tx_freq;
0085     unsigned int mclk_root0_freq;
0086     unsigned int mclk_root1_freq;
0087     unsigned int mclk_root0_initial_freq;
0088     unsigned int mclk_root1_initial_freq;
0089     unsigned int frame_width;
0090     unsigned int clk_trcm;
0091     unsigned int i2s_sdis[CH_GRP_MAX];
0092     unsigned int i2s_sdos[CH_GRP_MAX];
0093     int clk_ppm;
0094     int refcount;
0095     spinlock_t lock; /* xfer lock */
0096     bool has_playback;
0097     bool has_capture;
0098     struct snd_soc_dai_driver *dai;
0099 };
0100 
0101 static int to_ch_num(unsigned int val)
0102 {
0103     switch (val) {
0104     case I2S_CHN_4:
0105         return 4;
0106     case I2S_CHN_6:
0107         return 6;
0108     case I2S_CHN_8:
0109         return 8;
0110     default:
0111         return 2;
0112     }
0113 }
0114 
0115 static void i2s_tdm_disable_unprepare_mclk(struct rk_i2s_tdm_dev *i2s_tdm)
0116 {
0117     clk_disable_unprepare(i2s_tdm->mclk_tx);
0118     clk_disable_unprepare(i2s_tdm->mclk_rx);
0119     if (i2s_tdm->mclk_calibrate) {
0120         clk_disable_unprepare(i2s_tdm->mclk_tx_src);
0121         clk_disable_unprepare(i2s_tdm->mclk_rx_src);
0122         clk_disable_unprepare(i2s_tdm->mclk_root0);
0123         clk_disable_unprepare(i2s_tdm->mclk_root1);
0124     }
0125 }
0126 
0127 /**
0128  * i2s_tdm_prepare_enable_mclk - prepare to enable all mclks, disable them on
0129  *               failure.
0130  * @i2s_tdm: rk_i2s_tdm_dev struct
0131  *
0132  * This function attempts to enable all mclk clocks, but cleans up after
0133  * itself on failure. Guarantees to balance its calls.
0134  *
0135  * Returns success (0) or negative errno.
0136  */
0137 static int i2s_tdm_prepare_enable_mclk(struct rk_i2s_tdm_dev *i2s_tdm)
0138 {
0139     int ret = 0;
0140 
0141     ret = clk_prepare_enable(i2s_tdm->mclk_tx);
0142     if (ret)
0143         goto err_mclk_tx;
0144     ret = clk_prepare_enable(i2s_tdm->mclk_rx);
0145     if (ret)
0146         goto err_mclk_rx;
0147     if (i2s_tdm->mclk_calibrate) {
0148         ret = clk_prepare_enable(i2s_tdm->mclk_tx_src);
0149         if (ret)
0150             goto err_mclk_rx;
0151         ret = clk_prepare_enable(i2s_tdm->mclk_rx_src);
0152         if (ret)
0153             goto err_mclk_rx_src;
0154         ret = clk_prepare_enable(i2s_tdm->mclk_root0);
0155         if (ret)
0156             goto err_mclk_root0;
0157         ret = clk_prepare_enable(i2s_tdm->mclk_root1);
0158         if (ret)
0159             goto err_mclk_root1;
0160     }
0161 
0162     return 0;
0163 
0164 err_mclk_root1:
0165     clk_disable_unprepare(i2s_tdm->mclk_root0);
0166 err_mclk_root0:
0167     clk_disable_unprepare(i2s_tdm->mclk_rx_src);
0168 err_mclk_rx_src:
0169     clk_disable_unprepare(i2s_tdm->mclk_tx_src);
0170 err_mclk_rx:
0171     clk_disable_unprepare(i2s_tdm->mclk_tx);
0172 err_mclk_tx:
0173     return ret;
0174 }
0175 
0176 static int __maybe_unused i2s_tdm_runtime_suspend(struct device *dev)
0177 {
0178     struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
0179 
0180     regcache_cache_only(i2s_tdm->regmap, true);
0181     i2s_tdm_disable_unprepare_mclk(i2s_tdm);
0182 
0183     clk_disable_unprepare(i2s_tdm->hclk);
0184 
0185     return 0;
0186 }
0187 
0188 static int __maybe_unused i2s_tdm_runtime_resume(struct device *dev)
0189 {
0190     struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
0191     int ret;
0192 
0193     ret = clk_prepare_enable(i2s_tdm->hclk);
0194     if (ret)
0195         goto err_hclk;
0196 
0197     ret = i2s_tdm_prepare_enable_mclk(i2s_tdm);
0198     if (ret)
0199         goto err_mclk;
0200 
0201     regcache_cache_only(i2s_tdm->regmap, false);
0202     regcache_mark_dirty(i2s_tdm->regmap);
0203 
0204     ret = regcache_sync(i2s_tdm->regmap);
0205     if (ret)
0206         goto err_regcache;
0207 
0208     return 0;
0209 
0210 err_regcache:
0211     i2s_tdm_disable_unprepare_mclk(i2s_tdm);
0212 err_mclk:
0213     clk_disable_unprepare(i2s_tdm->hclk);
0214 err_hclk:
0215     return ret;
0216 }
0217 
0218 static inline struct rk_i2s_tdm_dev *to_info(struct snd_soc_dai *dai)
0219 {
0220     return snd_soc_dai_get_drvdata(dai);
0221 }
0222 
0223 /*
0224  * Makes sure that both tx and rx are reset at the same time to sync lrck
0225  * when clk_trcm > 0.
0226  */
0227 static void rockchip_snd_xfer_sync_reset(struct rk_i2s_tdm_dev *i2s_tdm)
0228 {
0229     /* This is technically race-y.
0230      *
0231      * In an ideal world, we could atomically assert both resets at the
0232      * same time, through an atomic bulk reset API. This API however does
0233      * not exist, so what the downstream vendor code used to do was
0234      * implement half a reset controller here and require the CRU to be
0235      * passed to the driver as a device tree node. Violating abstractions
0236      * like that is bad, especially when it influences something like the
0237      * bindings which are supposed to describe the hardware, not whatever
0238      * workarounds the driver needs, so it was dropped.
0239      *
0240      * In practice, asserting the resets one by one appears to work just
0241      * fine for playback. During duplex (playback + capture) operation,
0242      * this might become an issue, but that should be solved by the
0243      * implementation of the aforementioned API, not by shoving a reset
0244      * controller into an audio driver.
0245      */
0246 
0247     reset_control_assert(i2s_tdm->tx_reset);
0248     reset_control_assert(i2s_tdm->rx_reset);
0249     udelay(10);
0250     reset_control_deassert(i2s_tdm->tx_reset);
0251     reset_control_deassert(i2s_tdm->rx_reset);
0252     udelay(10);
0253 }
0254 
0255 static void rockchip_snd_reset(struct reset_control *rc)
0256 {
0257     reset_control_assert(rc);
0258     udelay(10);
0259     reset_control_deassert(rc);
0260     udelay(10);
0261 }
0262 
0263 static void rockchip_snd_xfer_clear(struct rk_i2s_tdm_dev *i2s_tdm,
0264                     unsigned int clr)
0265 {
0266     unsigned int xfer_mask = 0;
0267     unsigned int xfer_val = 0;
0268     unsigned int val;
0269     int retry = 10;
0270     bool tx = clr & I2S_CLR_TXC;
0271     bool rx = clr & I2S_CLR_RXC;
0272 
0273     if (!(rx || tx))
0274         return;
0275 
0276     if (tx) {
0277         xfer_mask = I2S_XFER_TXS_START;
0278         xfer_val = I2S_XFER_TXS_STOP;
0279     }
0280     if (rx) {
0281         xfer_mask |= I2S_XFER_RXS_START;
0282         xfer_val |= I2S_XFER_RXS_STOP;
0283     }
0284 
0285     regmap_update_bits(i2s_tdm->regmap, I2S_XFER, xfer_mask, xfer_val);
0286     udelay(150);
0287     regmap_update_bits(i2s_tdm->regmap, I2S_CLR, clr, clr);
0288 
0289     regmap_read(i2s_tdm->regmap, I2S_CLR, &val);
0290     /* Wait on the clear operation to finish */
0291     while (val) {
0292         udelay(15);
0293         regmap_read(i2s_tdm->regmap, I2S_CLR, &val);
0294         retry--;
0295         if (!retry) {
0296             dev_warn(i2s_tdm->dev, "clear failed, reset %s%s\n",
0297                  tx ? "tx" : "", rx ? "rx" : "");
0298             if (rx && tx)
0299                 rockchip_snd_xfer_sync_reset(i2s_tdm);
0300             else if (tx)
0301                 rockchip_snd_reset(i2s_tdm->tx_reset);
0302             else if (rx)
0303                 rockchip_snd_reset(i2s_tdm->rx_reset);
0304             break;
0305         }
0306     }
0307 }
0308 
0309 static inline void rockchip_enable_tde(struct regmap *regmap)
0310 {
0311     regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_TDE_ENABLE,
0312                I2S_DMACR_TDE_ENABLE);
0313 }
0314 
0315 static inline void rockchip_disable_tde(struct regmap *regmap)
0316 {
0317     regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_TDE_ENABLE,
0318                I2S_DMACR_TDE_DISABLE);
0319 }
0320 
0321 static inline void rockchip_enable_rde(struct regmap *regmap)
0322 {
0323     regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_RDE_ENABLE,
0324                I2S_DMACR_RDE_ENABLE);
0325 }
0326 
0327 static inline void rockchip_disable_rde(struct regmap *regmap)
0328 {
0329     regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_RDE_ENABLE,
0330                I2S_DMACR_RDE_DISABLE);
0331 }
0332 
0333 /* only used when clk_trcm > 0 */
0334 static void rockchip_snd_txrxctrl(struct snd_pcm_substream *substream,
0335                   struct snd_soc_dai *dai, int on)
0336 {
0337     struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
0338     unsigned long flags;
0339 
0340     spin_lock_irqsave(&i2s_tdm->lock, flags);
0341     if (on) {
0342         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
0343             rockchip_enable_tde(i2s_tdm->regmap);
0344         else
0345             rockchip_enable_rde(i2s_tdm->regmap);
0346 
0347         if (++i2s_tdm->refcount == 1) {
0348             rockchip_snd_xfer_sync_reset(i2s_tdm);
0349             regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
0350                        I2S_XFER_TXS_START |
0351                        I2S_XFER_RXS_START,
0352                        I2S_XFER_TXS_START |
0353                        I2S_XFER_RXS_START);
0354         }
0355     } else {
0356         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
0357             rockchip_disable_tde(i2s_tdm->regmap);
0358         else
0359             rockchip_disable_rde(i2s_tdm->regmap);
0360 
0361         if (--i2s_tdm->refcount == 0) {
0362             rockchip_snd_xfer_clear(i2s_tdm,
0363                         I2S_CLR_TXC | I2S_CLR_RXC);
0364         }
0365     }
0366     spin_unlock_irqrestore(&i2s_tdm->lock, flags);
0367 }
0368 
0369 static void rockchip_snd_txctrl(struct rk_i2s_tdm_dev *i2s_tdm, int on)
0370 {
0371     if (on) {
0372         rockchip_enable_tde(i2s_tdm->regmap);
0373 
0374         regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
0375                    I2S_XFER_TXS_START,
0376                    I2S_XFER_TXS_START);
0377     } else {
0378         rockchip_disable_tde(i2s_tdm->regmap);
0379 
0380         rockchip_snd_xfer_clear(i2s_tdm, I2S_CLR_TXC);
0381     }
0382 }
0383 
0384 static void rockchip_snd_rxctrl(struct rk_i2s_tdm_dev *i2s_tdm, int on)
0385 {
0386     if (on) {
0387         rockchip_enable_rde(i2s_tdm->regmap);
0388 
0389         regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
0390                    I2S_XFER_RXS_START,
0391                    I2S_XFER_RXS_START);
0392     } else {
0393         rockchip_disable_rde(i2s_tdm->regmap);
0394 
0395         rockchip_snd_xfer_clear(i2s_tdm, I2S_CLR_RXC);
0396     }
0397 }
0398 
0399 static int rockchip_i2s_tdm_set_fmt(struct snd_soc_dai *cpu_dai,
0400                     unsigned int fmt)
0401 {
0402     struct rk_i2s_tdm_dev *i2s_tdm = to_info(cpu_dai);
0403     unsigned int mask, val, tdm_val, txcr_val, rxcr_val;
0404     int ret;
0405     bool is_tdm = i2s_tdm->tdm_mode;
0406 
0407     ret = pm_runtime_resume_and_get(cpu_dai->dev);
0408     if (ret < 0 && ret != -EACCES)
0409         return ret;
0410 
0411     mask = I2S_CKR_MSS_MASK;
0412     switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
0413     case SND_SOC_DAIFMT_BP_FP:
0414         val = I2S_CKR_MSS_MASTER;
0415         i2s_tdm->is_master_mode = true;
0416         break;
0417     case SND_SOC_DAIFMT_BC_FC:
0418         val = I2S_CKR_MSS_SLAVE;
0419         i2s_tdm->is_master_mode = false;
0420         break;
0421     default:
0422         ret = -EINVAL;
0423         goto err_pm_put;
0424     }
0425 
0426     regmap_update_bits(i2s_tdm->regmap, I2S_CKR, mask, val);
0427 
0428     mask = I2S_CKR_CKP_MASK | I2S_CKR_TLP_MASK | I2S_CKR_RLP_MASK;
0429     switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
0430     case SND_SOC_DAIFMT_NB_NF:
0431         val = I2S_CKR_CKP_NORMAL |
0432               I2S_CKR_TLP_NORMAL |
0433               I2S_CKR_RLP_NORMAL;
0434         break;
0435     case SND_SOC_DAIFMT_NB_IF:
0436         val = I2S_CKR_CKP_NORMAL |
0437               I2S_CKR_TLP_INVERTED |
0438               I2S_CKR_RLP_INVERTED;
0439         break;
0440     case SND_SOC_DAIFMT_IB_NF:
0441         val = I2S_CKR_CKP_INVERTED |
0442               I2S_CKR_TLP_NORMAL |
0443               I2S_CKR_RLP_NORMAL;
0444         break;
0445     case SND_SOC_DAIFMT_IB_IF:
0446         val = I2S_CKR_CKP_INVERTED |
0447               I2S_CKR_TLP_INVERTED |
0448               I2S_CKR_RLP_INVERTED;
0449         break;
0450     default:
0451         ret = -EINVAL;
0452         goto err_pm_put;
0453     }
0454 
0455     regmap_update_bits(i2s_tdm->regmap, I2S_CKR, mask, val);
0456 
0457     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0458     case SND_SOC_DAIFMT_RIGHT_J:
0459         txcr_val = I2S_TXCR_IBM_RSJM;
0460         rxcr_val = I2S_RXCR_IBM_RSJM;
0461         break;
0462     case SND_SOC_DAIFMT_LEFT_J:
0463         txcr_val = I2S_TXCR_IBM_LSJM;
0464         rxcr_val = I2S_RXCR_IBM_LSJM;
0465         break;
0466     case SND_SOC_DAIFMT_I2S:
0467         txcr_val = I2S_TXCR_IBM_NORMAL;
0468         rxcr_val = I2S_RXCR_IBM_NORMAL;
0469         break;
0470     case SND_SOC_DAIFMT_DSP_A: /* PCM delay 1 mode */
0471         txcr_val = I2S_TXCR_TFS_PCM | I2S_TXCR_PBM_MODE(1);
0472         rxcr_val = I2S_RXCR_TFS_PCM | I2S_RXCR_PBM_MODE(1);
0473         break;
0474     case SND_SOC_DAIFMT_DSP_B: /* PCM no delay mode */
0475         txcr_val = I2S_TXCR_TFS_PCM;
0476         rxcr_val = I2S_RXCR_TFS_PCM;
0477         break;
0478     default:
0479         ret = -EINVAL;
0480         goto err_pm_put;
0481     }
0482 
0483     mask = I2S_TXCR_IBM_MASK | I2S_TXCR_TFS_MASK | I2S_TXCR_PBM_MASK;
0484     regmap_update_bits(i2s_tdm->regmap, I2S_TXCR, mask, txcr_val);
0485 
0486     mask = I2S_RXCR_IBM_MASK | I2S_RXCR_TFS_MASK | I2S_RXCR_PBM_MASK;
0487     regmap_update_bits(i2s_tdm->regmap, I2S_RXCR, mask, rxcr_val);
0488 
0489     if (is_tdm) {
0490         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0491         case SND_SOC_DAIFMT_RIGHT_J:
0492             val = I2S_TXCR_TFS_TDM_I2S;
0493             tdm_val = TDM_SHIFT_CTRL(2);
0494             break;
0495         case SND_SOC_DAIFMT_LEFT_J:
0496             val = I2S_TXCR_TFS_TDM_I2S;
0497             tdm_val = TDM_SHIFT_CTRL(1);
0498             break;
0499         case SND_SOC_DAIFMT_I2S:
0500             val = I2S_TXCR_TFS_TDM_I2S;
0501             tdm_val = TDM_SHIFT_CTRL(0);
0502             break;
0503         case SND_SOC_DAIFMT_DSP_A:
0504             val = I2S_TXCR_TFS_TDM_PCM;
0505             tdm_val = TDM_SHIFT_CTRL(0);
0506             break;
0507         case SND_SOC_DAIFMT_DSP_B:
0508             val = I2S_TXCR_TFS_TDM_PCM;
0509             tdm_val = TDM_SHIFT_CTRL(2);
0510             break;
0511         default:
0512             ret = -EINVAL;
0513             goto err_pm_put;
0514         }
0515 
0516         tdm_val |= TDM_FSYNC_WIDTH_SEL1(1);
0517         tdm_val |= TDM_FSYNC_WIDTH_HALF_FRAME;
0518 
0519         mask = I2S_TXCR_TFS_MASK;
0520         regmap_update_bits(i2s_tdm->regmap, I2S_TXCR, mask, val);
0521         regmap_update_bits(i2s_tdm->regmap, I2S_RXCR, mask, val);
0522 
0523         mask = TDM_FSYNC_WIDTH_SEL1_MSK | TDM_FSYNC_WIDTH_SEL0_MSK |
0524                TDM_SHIFT_CTRL_MSK;
0525         regmap_update_bits(i2s_tdm->regmap, I2S_TDM_TXCR,
0526                    mask, tdm_val);
0527         regmap_update_bits(i2s_tdm->regmap, I2S_TDM_RXCR,
0528                    mask, tdm_val);
0529     }
0530 
0531 err_pm_put:
0532     pm_runtime_put(cpu_dai->dev);
0533 
0534     return ret;
0535 }
0536 
0537 static void rockchip_i2s_tdm_xfer_pause(struct snd_pcm_substream *substream,
0538                     struct rk_i2s_tdm_dev *i2s_tdm)
0539 {
0540     int stream;
0541 
0542     stream = SNDRV_PCM_STREAM_LAST - substream->stream;
0543     if (stream == SNDRV_PCM_STREAM_PLAYBACK)
0544         rockchip_disable_tde(i2s_tdm->regmap);
0545     else
0546         rockchip_disable_rde(i2s_tdm->regmap);
0547 
0548     rockchip_snd_xfer_clear(i2s_tdm, I2S_CLR_TXC | I2S_CLR_RXC);
0549 }
0550 
0551 static void rockchip_i2s_tdm_xfer_resume(struct snd_pcm_substream *substream,
0552                      struct rk_i2s_tdm_dev *i2s_tdm)
0553 {
0554     int stream;
0555 
0556     stream = SNDRV_PCM_STREAM_LAST - substream->stream;
0557     if (stream == SNDRV_PCM_STREAM_PLAYBACK)
0558         rockchip_enable_tde(i2s_tdm->regmap);
0559     else
0560         rockchip_enable_rde(i2s_tdm->regmap);
0561 
0562     regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
0563                I2S_XFER_TXS_START |
0564                I2S_XFER_RXS_START,
0565                I2S_XFER_TXS_START |
0566                I2S_XFER_RXS_START);
0567 }
0568 
0569 static int rockchip_i2s_tdm_clk_set_rate(struct rk_i2s_tdm_dev *i2s_tdm,
0570                      struct clk *clk, unsigned long rate,
0571                      int ppm)
0572 {
0573     unsigned long rate_target;
0574     int delta, ret;
0575 
0576     if (ppm == i2s_tdm->clk_ppm)
0577         return 0;
0578 
0579     if (ppm < 0)
0580         delta = -1;
0581     else
0582         delta = 1;
0583 
0584     delta *= (int)div64_u64((u64)rate * (u64)abs(ppm) + 500000,
0585                 1000000);
0586 
0587     rate_target = rate + delta;
0588 
0589     if (!rate_target)
0590         return -EINVAL;
0591 
0592     ret = clk_set_rate(clk, rate_target);
0593     if (ret)
0594         return ret;
0595 
0596     i2s_tdm->clk_ppm = ppm;
0597 
0598     return 0;
0599 }
0600 
0601 static int rockchip_i2s_tdm_calibrate_mclk(struct rk_i2s_tdm_dev *i2s_tdm,
0602                        struct snd_pcm_substream *substream,
0603                        unsigned int lrck_freq)
0604 {
0605     struct clk *mclk_root;
0606     struct clk *mclk_parent;
0607     unsigned int mclk_root_freq;
0608     unsigned int mclk_root_initial_freq;
0609     unsigned int mclk_parent_freq;
0610     unsigned int div, delta;
0611     u64 ppm;
0612     int ret;
0613 
0614     if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
0615         mclk_parent = i2s_tdm->mclk_tx_src;
0616     else
0617         mclk_parent = i2s_tdm->mclk_rx_src;
0618 
0619     switch (lrck_freq) {
0620     case 8000:
0621     case 16000:
0622     case 24000:
0623     case 32000:
0624     case 48000:
0625     case 64000:
0626     case 96000:
0627     case 192000:
0628         mclk_root = i2s_tdm->mclk_root0;
0629         mclk_root_freq = i2s_tdm->mclk_root0_freq;
0630         mclk_root_initial_freq = i2s_tdm->mclk_root0_initial_freq;
0631         mclk_parent_freq = DEFAULT_MCLK_FS * 192000;
0632         break;
0633     case 11025:
0634     case 22050:
0635     case 44100:
0636     case 88200:
0637     case 176400:
0638         mclk_root = i2s_tdm->mclk_root1;
0639         mclk_root_freq = i2s_tdm->mclk_root1_freq;
0640         mclk_root_initial_freq = i2s_tdm->mclk_root1_initial_freq;
0641         mclk_parent_freq = DEFAULT_MCLK_FS * 176400;
0642         break;
0643     default:
0644         dev_err(i2s_tdm->dev, "Invalid LRCK frequency: %u Hz\n",
0645             lrck_freq);
0646         return -EINVAL;
0647     }
0648 
0649     ret = clk_set_parent(mclk_parent, mclk_root);
0650     if (ret)
0651         return ret;
0652 
0653     ret = rockchip_i2s_tdm_clk_set_rate(i2s_tdm, mclk_root,
0654                         mclk_root_freq, 0);
0655     if (ret)
0656         return ret;
0657 
0658     delta = abs(mclk_root_freq % mclk_parent_freq - mclk_parent_freq);
0659     ppm = div64_u64((uint64_t)delta * 1000000, (uint64_t)mclk_root_freq);
0660 
0661     if (ppm) {
0662         div = DIV_ROUND_CLOSEST(mclk_root_initial_freq, mclk_parent_freq);
0663         if (!div)
0664             return -EINVAL;
0665 
0666         mclk_root_freq = mclk_parent_freq * round_up(div, 2);
0667 
0668         ret = clk_set_rate(mclk_root, mclk_root_freq);
0669         if (ret)
0670             return ret;
0671 
0672         i2s_tdm->mclk_root0_freq = clk_get_rate(i2s_tdm->mclk_root0);
0673         i2s_tdm->mclk_root1_freq = clk_get_rate(i2s_tdm->mclk_root1);
0674     }
0675 
0676     return clk_set_rate(mclk_parent, mclk_parent_freq);
0677 }
0678 
0679 static int rockchip_i2s_tdm_set_mclk(struct rk_i2s_tdm_dev *i2s_tdm,
0680                      struct snd_pcm_substream *substream,
0681                      struct clk **mclk)
0682 {
0683     unsigned int mclk_freq;
0684     int ret;
0685 
0686     if (i2s_tdm->clk_trcm) {
0687         if (i2s_tdm->mclk_tx_freq != i2s_tdm->mclk_rx_freq) {
0688             dev_err(i2s_tdm->dev,
0689                 "clk_trcm, tx: %d and rx: %d should be the same\n",
0690                 i2s_tdm->mclk_tx_freq,
0691                 i2s_tdm->mclk_rx_freq);
0692             return -EINVAL;
0693         }
0694 
0695         ret = clk_set_rate(i2s_tdm->mclk_tx, i2s_tdm->mclk_tx_freq);
0696         if (ret)
0697             return ret;
0698 
0699         ret = clk_set_rate(i2s_tdm->mclk_rx, i2s_tdm->mclk_rx_freq);
0700         if (ret)
0701             return ret;
0702 
0703         /* mclk_rx is also ok. */
0704         *mclk = i2s_tdm->mclk_tx;
0705     } else {
0706         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
0707             *mclk = i2s_tdm->mclk_tx;
0708             mclk_freq = i2s_tdm->mclk_tx_freq;
0709         } else {
0710             *mclk = i2s_tdm->mclk_rx;
0711             mclk_freq = i2s_tdm->mclk_rx_freq;
0712         }
0713 
0714         ret = clk_set_rate(*mclk, mclk_freq);
0715         if (ret)
0716             return ret;
0717     }
0718 
0719     return 0;
0720 }
0721 
0722 static int rockchip_i2s_ch_to_io(unsigned int ch, bool substream_capture)
0723 {
0724     if (substream_capture) {
0725         switch (ch) {
0726         case I2S_CHN_4:
0727             return I2S_IO_6CH_OUT_4CH_IN;
0728         case I2S_CHN_6:
0729             return I2S_IO_4CH_OUT_6CH_IN;
0730         case I2S_CHN_8:
0731             return I2S_IO_2CH_OUT_8CH_IN;
0732         default:
0733             return I2S_IO_8CH_OUT_2CH_IN;
0734         }
0735     } else {
0736         switch (ch) {
0737         case I2S_CHN_4:
0738             return I2S_IO_4CH_OUT_6CH_IN;
0739         case I2S_CHN_6:
0740             return I2S_IO_6CH_OUT_4CH_IN;
0741         case I2S_CHN_8:
0742             return I2S_IO_8CH_OUT_2CH_IN;
0743         default:
0744             return I2S_IO_2CH_OUT_8CH_IN;
0745         }
0746     }
0747 }
0748 
0749 static int rockchip_i2s_io_multiplex(struct snd_pcm_substream *substream,
0750                      struct snd_soc_dai *dai)
0751 {
0752     struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
0753     int usable_chs = MULTIPLEX_CH_MAX;
0754     unsigned int val = 0;
0755 
0756     if (!i2s_tdm->io_multiplex)
0757         return 0;
0758 
0759     if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
0760         struct snd_pcm_str *playback_str =
0761             &substream->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK];
0762 
0763         if (playback_str->substream_opened) {
0764             regmap_read(i2s_tdm->regmap, I2S_TXCR, &val);
0765             val &= I2S_TXCR_CSR_MASK;
0766             usable_chs = MULTIPLEX_CH_MAX - to_ch_num(val);
0767         }
0768 
0769         regmap_read(i2s_tdm->regmap, I2S_RXCR, &val);
0770         val &= I2S_RXCR_CSR_MASK;
0771 
0772         if (to_ch_num(val) > usable_chs) {
0773             dev_err(i2s_tdm->dev,
0774                 "Capture channels (%d) > usable channels (%d)\n",
0775                 to_ch_num(val), usable_chs);
0776             return -EINVAL;
0777         }
0778 
0779         rockchip_i2s_ch_to_io(val, true);
0780     } else {
0781         struct snd_pcm_str *capture_str =
0782             &substream->pcm->streams[SNDRV_PCM_STREAM_CAPTURE];
0783 
0784         if (capture_str->substream_opened) {
0785             regmap_read(i2s_tdm->regmap, I2S_RXCR, &val);
0786             val &= I2S_RXCR_CSR_MASK;
0787             usable_chs = MULTIPLEX_CH_MAX - to_ch_num(val);
0788         }
0789 
0790         regmap_read(i2s_tdm->regmap, I2S_TXCR, &val);
0791         val &= I2S_TXCR_CSR_MASK;
0792 
0793         if (to_ch_num(val) > usable_chs) {
0794             dev_err(i2s_tdm->dev,
0795                 "Playback channels (%d) > usable channels (%d)\n",
0796                 to_ch_num(val), usable_chs);
0797             return -EINVAL;
0798         }
0799     }
0800 
0801     val <<= i2s_tdm->soc_data->grf_shift;
0802     val |= (I2S_IO_DIRECTION_MASK << i2s_tdm->soc_data->grf_shift) << 16;
0803     regmap_write(i2s_tdm->grf, i2s_tdm->soc_data->grf_reg_offset, val);
0804 
0805     return 0;
0806 }
0807 
0808 static int rockchip_i2s_trcm_mode(struct snd_pcm_substream *substream,
0809                   struct snd_soc_dai *dai,
0810                   unsigned int div_bclk,
0811                   unsigned int div_lrck,
0812                   unsigned int fmt)
0813 {
0814     struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
0815     unsigned long flags;
0816 
0817     if (!i2s_tdm->clk_trcm)
0818         return 0;
0819 
0820     spin_lock_irqsave(&i2s_tdm->lock, flags);
0821     if (i2s_tdm->refcount)
0822         rockchip_i2s_tdm_xfer_pause(substream, i2s_tdm);
0823 
0824     regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
0825                I2S_CLKDIV_TXM_MASK | I2S_CLKDIV_RXM_MASK,
0826                I2S_CLKDIV_TXM(div_bclk) | I2S_CLKDIV_RXM(div_bclk));
0827     regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
0828                I2S_CKR_TSD_MASK | I2S_CKR_RSD_MASK,
0829                I2S_CKR_TSD(div_lrck) | I2S_CKR_RSD(div_lrck));
0830 
0831     if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
0832         regmap_update_bits(i2s_tdm->regmap, I2S_TXCR,
0833                    I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
0834                    fmt);
0835     else
0836         regmap_update_bits(i2s_tdm->regmap, I2S_RXCR,
0837                    I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
0838                    fmt);
0839 
0840     if (i2s_tdm->refcount)
0841         rockchip_i2s_tdm_xfer_resume(substream, i2s_tdm);
0842     spin_unlock_irqrestore(&i2s_tdm->lock, flags);
0843 
0844     return 0;
0845 }
0846 
0847 static int rockchip_i2s_tdm_hw_params(struct snd_pcm_substream *substream,
0848                       struct snd_pcm_hw_params *params,
0849                       struct snd_soc_dai *dai)
0850 {
0851     struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
0852     struct clk *mclk;
0853     int ret = 0;
0854     unsigned int val = 0;
0855     unsigned int mclk_rate, bclk_rate, div_bclk = 4, div_lrck = 64;
0856 
0857     if (i2s_tdm->is_master_mode) {
0858         if (i2s_tdm->mclk_calibrate)
0859             rockchip_i2s_tdm_calibrate_mclk(i2s_tdm, substream,
0860                             params_rate(params));
0861 
0862         ret = rockchip_i2s_tdm_set_mclk(i2s_tdm, substream, &mclk);
0863         if (ret)
0864             return ret;
0865 
0866         mclk_rate = clk_get_rate(mclk);
0867         bclk_rate = i2s_tdm->frame_width * params_rate(params);
0868         if (!bclk_rate)
0869             return -EINVAL;
0870 
0871         div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate);
0872         div_lrck = bclk_rate / params_rate(params);
0873     }
0874 
0875     switch (params_format(params)) {
0876     case SNDRV_PCM_FORMAT_S8:
0877         val |= I2S_TXCR_VDW(8);
0878         break;
0879     case SNDRV_PCM_FORMAT_S16_LE:
0880         val |= I2S_TXCR_VDW(16);
0881         break;
0882     case SNDRV_PCM_FORMAT_S20_3LE:
0883         val |= I2S_TXCR_VDW(20);
0884         break;
0885     case SNDRV_PCM_FORMAT_S24_LE:
0886         val |= I2S_TXCR_VDW(24);
0887         break;
0888     case SNDRV_PCM_FORMAT_S32_LE:
0889         val |= I2S_TXCR_VDW(32);
0890         break;
0891     default:
0892         return -EINVAL;
0893     }
0894 
0895     switch (params_channels(params)) {
0896     case 8:
0897         val |= I2S_CHN_8;
0898         break;
0899     case 6:
0900         val |= I2S_CHN_6;
0901         break;
0902     case 4:
0903         val |= I2S_CHN_4;
0904         break;
0905     case 2:
0906         val |= I2S_CHN_2;
0907         break;
0908     default:
0909         return -EINVAL;
0910     }
0911 
0912     if (i2s_tdm->clk_trcm) {
0913         rockchip_i2s_trcm_mode(substream, dai, div_bclk, div_lrck, val);
0914     } else if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
0915         regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
0916                    I2S_CLKDIV_TXM_MASK,
0917                    I2S_CLKDIV_TXM(div_bclk));
0918         regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
0919                    I2S_CKR_TSD_MASK,
0920                    I2S_CKR_TSD(div_lrck));
0921         regmap_update_bits(i2s_tdm->regmap, I2S_TXCR,
0922                    I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
0923                    val);
0924     } else {
0925         regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
0926                    I2S_CLKDIV_RXM_MASK,
0927                    I2S_CLKDIV_RXM(div_bclk));
0928         regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
0929                    I2S_CKR_RSD_MASK,
0930                    I2S_CKR_RSD(div_lrck));
0931         regmap_update_bits(i2s_tdm->regmap, I2S_RXCR,
0932                    I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
0933                    val);
0934     }
0935 
0936     return rockchip_i2s_io_multiplex(substream, dai);
0937 }
0938 
0939 static int rockchip_i2s_tdm_trigger(struct snd_pcm_substream *substream,
0940                     int cmd, struct snd_soc_dai *dai)
0941 {
0942     struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
0943 
0944     switch (cmd) {
0945     case SNDRV_PCM_TRIGGER_START:
0946     case SNDRV_PCM_TRIGGER_RESUME:
0947     case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
0948         if (i2s_tdm->clk_trcm)
0949             rockchip_snd_txrxctrl(substream, dai, 1);
0950         else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
0951             rockchip_snd_rxctrl(i2s_tdm, 1);
0952         else
0953             rockchip_snd_txctrl(i2s_tdm, 1);
0954         break;
0955     case SNDRV_PCM_TRIGGER_SUSPEND:
0956     case SNDRV_PCM_TRIGGER_STOP:
0957     case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
0958         if (i2s_tdm->clk_trcm)
0959             rockchip_snd_txrxctrl(substream, dai, 0);
0960         else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
0961             rockchip_snd_rxctrl(i2s_tdm, 0);
0962         else
0963             rockchip_snd_txctrl(i2s_tdm, 0);
0964         break;
0965     default:
0966         return -EINVAL;
0967     }
0968 
0969     return 0;
0970 }
0971 
0972 static int rockchip_i2s_tdm_set_sysclk(struct snd_soc_dai *cpu_dai, int stream,
0973                        unsigned int freq, int dir)
0974 {
0975     struct rk_i2s_tdm_dev *i2s_tdm = to_info(cpu_dai);
0976 
0977     /* Put set mclk rate into rockchip_i2s_tdm_set_mclk() */
0978     if (i2s_tdm->clk_trcm) {
0979         i2s_tdm->mclk_tx_freq = freq;
0980         i2s_tdm->mclk_rx_freq = freq;
0981     } else {
0982         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
0983             i2s_tdm->mclk_tx_freq = freq;
0984         else
0985             i2s_tdm->mclk_rx_freq = freq;
0986     }
0987 
0988     dev_dbg(i2s_tdm->dev, "The target mclk_%s freq is: %d\n",
0989         stream ? "rx" : "tx", freq);
0990 
0991     return 0;
0992 }
0993 
0994 static int rockchip_i2s_tdm_clk_compensation_info(struct snd_kcontrol *kcontrol,
0995                           struct snd_ctl_elem_info *uinfo)
0996 {
0997     uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
0998     uinfo->count = 1;
0999     uinfo->value.integer.min = CLK_PPM_MIN;
1000     uinfo->value.integer.max = CLK_PPM_MAX;
1001     uinfo->value.integer.step = 1;
1002 
1003     return 0;
1004 }
1005 
1006 static int rockchip_i2s_tdm_clk_compensation_get(struct snd_kcontrol *kcontrol,
1007                          struct snd_ctl_elem_value *ucontrol)
1008 {
1009     struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
1010     struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
1011 
1012     ucontrol->value.integer.value[0] = i2s_tdm->clk_ppm;
1013 
1014     return 0;
1015 }
1016 
1017 static int rockchip_i2s_tdm_clk_compensation_put(struct snd_kcontrol *kcontrol,
1018                          struct snd_ctl_elem_value *ucontrol)
1019 {
1020     struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
1021     struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
1022     int ret = 0, ppm = 0;
1023     int changed = 0;
1024     unsigned long old_rate;
1025 
1026     if (ucontrol->value.integer.value[0] < CLK_PPM_MIN ||
1027         ucontrol->value.integer.value[0] > CLK_PPM_MAX)
1028         return -EINVAL;
1029 
1030     ppm = ucontrol->value.integer.value[0];
1031 
1032     old_rate = clk_get_rate(i2s_tdm->mclk_root0);
1033     ret = rockchip_i2s_tdm_clk_set_rate(i2s_tdm, i2s_tdm->mclk_root0,
1034                         i2s_tdm->mclk_root0_freq, ppm);
1035     if (ret)
1036         return ret;
1037     if (old_rate != clk_get_rate(i2s_tdm->mclk_root0))
1038         changed = 1;
1039 
1040     if (clk_is_match(i2s_tdm->mclk_root0, i2s_tdm->mclk_root1))
1041         return changed;
1042 
1043     old_rate = clk_get_rate(i2s_tdm->mclk_root1);
1044     ret = rockchip_i2s_tdm_clk_set_rate(i2s_tdm, i2s_tdm->mclk_root1,
1045                         i2s_tdm->mclk_root1_freq, ppm);
1046     if (ret)
1047         return ret;
1048     if (old_rate != clk_get_rate(i2s_tdm->mclk_root1))
1049         changed = 1;
1050 
1051     return changed;
1052 }
1053 
1054 static struct snd_kcontrol_new rockchip_i2s_tdm_compensation_control = {
1055     .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1056     .name = "PCM Clock Compensation in PPM",
1057     .info = rockchip_i2s_tdm_clk_compensation_info,
1058     .get = rockchip_i2s_tdm_clk_compensation_get,
1059     .put = rockchip_i2s_tdm_clk_compensation_put,
1060 };
1061 
1062 static int rockchip_i2s_tdm_dai_probe(struct snd_soc_dai *dai)
1063 {
1064     struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
1065 
1066     if (i2s_tdm->has_capture)
1067         dai->capture_dma_data = &i2s_tdm->capture_dma_data;
1068     if (i2s_tdm->has_playback)
1069         dai->playback_dma_data = &i2s_tdm->playback_dma_data;
1070 
1071     if (i2s_tdm->mclk_calibrate)
1072         snd_soc_add_dai_controls(dai, &rockchip_i2s_tdm_compensation_control, 1);
1073 
1074     return 0;
1075 }
1076 
1077 static int rockchip_dai_tdm_slot(struct snd_soc_dai *dai,
1078                  unsigned int tx_mask, unsigned int rx_mask,
1079                  int slots, int slot_width)
1080 {
1081     struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
1082     unsigned int mask, val;
1083 
1084     i2s_tdm->tdm_mode = true;
1085     i2s_tdm->frame_width = slots * slot_width;
1086     mask = TDM_SLOT_BIT_WIDTH_MSK | TDM_FRAME_WIDTH_MSK;
1087     val = TDM_SLOT_BIT_WIDTH(slot_width) |
1088           TDM_FRAME_WIDTH(slots * slot_width);
1089     regmap_update_bits(i2s_tdm->regmap, I2S_TDM_TXCR,
1090                mask, val);
1091     regmap_update_bits(i2s_tdm->regmap, I2S_TDM_RXCR,
1092                mask, val);
1093 
1094     return 0;
1095 }
1096 
1097 static int rockchip_i2s_tdm_set_bclk_ratio(struct snd_soc_dai *dai,
1098                        unsigned int ratio)
1099 {
1100     struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
1101 
1102     if (ratio < 32 || ratio > 512 || ratio % 2 == 1)
1103         return -EINVAL;
1104 
1105     i2s_tdm->frame_width = ratio;
1106 
1107     return 0;
1108 }
1109 
1110 static const struct snd_soc_dai_ops rockchip_i2s_tdm_dai_ops = {
1111     .hw_params = rockchip_i2s_tdm_hw_params,
1112     .set_bclk_ratio = rockchip_i2s_tdm_set_bclk_ratio,
1113     .set_sysclk = rockchip_i2s_tdm_set_sysclk,
1114     .set_fmt = rockchip_i2s_tdm_set_fmt,
1115     .set_tdm_slot = rockchip_dai_tdm_slot,
1116     .trigger = rockchip_i2s_tdm_trigger,
1117 };
1118 
1119 static const struct snd_soc_component_driver rockchip_i2s_tdm_component = {
1120     .name = DRV_NAME,
1121     .legacy_dai_naming = 1,
1122 };
1123 
1124 static bool rockchip_i2s_tdm_wr_reg(struct device *dev, unsigned int reg)
1125 {
1126     switch (reg) {
1127     case I2S_TXCR:
1128     case I2S_RXCR:
1129     case I2S_CKR:
1130     case I2S_DMACR:
1131     case I2S_INTCR:
1132     case I2S_XFER:
1133     case I2S_CLR:
1134     case I2S_TXDR:
1135     case I2S_TDM_TXCR:
1136     case I2S_TDM_RXCR:
1137     case I2S_CLKDIV:
1138         return true;
1139     default:
1140         return false;
1141     }
1142 }
1143 
1144 static bool rockchip_i2s_tdm_rd_reg(struct device *dev, unsigned int reg)
1145 {
1146     switch (reg) {
1147     case I2S_TXCR:
1148     case I2S_RXCR:
1149     case I2S_CKR:
1150     case I2S_DMACR:
1151     case I2S_INTCR:
1152     case I2S_XFER:
1153     case I2S_CLR:
1154     case I2S_TXDR:
1155     case I2S_RXDR:
1156     case I2S_TXFIFOLR:
1157     case I2S_INTSR:
1158     case I2S_RXFIFOLR:
1159     case I2S_TDM_TXCR:
1160     case I2S_TDM_RXCR:
1161     case I2S_CLKDIV:
1162         return true;
1163     default:
1164         return false;
1165     }
1166 }
1167 
1168 static bool rockchip_i2s_tdm_volatile_reg(struct device *dev, unsigned int reg)
1169 {
1170     switch (reg) {
1171     case I2S_TXFIFOLR:
1172     case I2S_INTSR:
1173     case I2S_CLR:
1174     case I2S_TXDR:
1175     case I2S_RXDR:
1176     case I2S_RXFIFOLR:
1177         return true;
1178     default:
1179         return false;
1180     }
1181 }
1182 
1183 static bool rockchip_i2s_tdm_precious_reg(struct device *dev, unsigned int reg)
1184 {
1185     if (reg == I2S_RXDR)
1186         return true;
1187     return false;
1188 }
1189 
1190 static const struct reg_default rockchip_i2s_tdm_reg_defaults[] = {
1191     {0x00, 0x7200000f},
1192     {0x04, 0x01c8000f},
1193     {0x08, 0x00001f1f},
1194     {0x10, 0x001f0000},
1195     {0x14, 0x01f00000},
1196     {0x30, 0x00003eff},
1197     {0x34, 0x00003eff},
1198     {0x38, 0x00000707},
1199 };
1200 
1201 static const struct regmap_config rockchip_i2s_tdm_regmap_config = {
1202     .reg_bits = 32,
1203     .reg_stride = 4,
1204     .val_bits = 32,
1205     .max_register = I2S_CLKDIV,
1206     .reg_defaults = rockchip_i2s_tdm_reg_defaults,
1207     .num_reg_defaults = ARRAY_SIZE(rockchip_i2s_tdm_reg_defaults),
1208     .writeable_reg = rockchip_i2s_tdm_wr_reg,
1209     .readable_reg = rockchip_i2s_tdm_rd_reg,
1210     .volatile_reg = rockchip_i2s_tdm_volatile_reg,
1211     .precious_reg = rockchip_i2s_tdm_precious_reg,
1212     .cache_type = REGCACHE_FLAT,
1213 };
1214 
1215 static int common_soc_init(struct device *dev, u32 addr)
1216 {
1217     struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
1218     const struct txrx_config *configs = i2s_tdm->soc_data->configs;
1219     u32 reg = 0, val = 0, trcm = i2s_tdm->clk_trcm;
1220     int i;
1221 
1222     if (trcm == TRCM_TXRX)
1223         return 0;
1224 
1225     for (i = 0; i < i2s_tdm->soc_data->config_count; i++) {
1226         if (addr != configs[i].addr)
1227             continue;
1228         reg = configs[i].reg;
1229         if (trcm == TRCM_TX)
1230             val = configs[i].txonly;
1231         else
1232             val = configs[i].rxonly;
1233 
1234         if (reg)
1235             regmap_write(i2s_tdm->grf, reg, val);
1236     }
1237 
1238     return 0;
1239 }
1240 
1241 static const struct txrx_config px30_txrx_config[] = {
1242     { 0xff060000, 0x184, PX30_I2S0_CLK_TXONLY, PX30_I2S0_CLK_RXONLY },
1243 };
1244 
1245 static const struct txrx_config rk1808_txrx_config[] = {
1246     { 0xff7e0000, 0x190, RK1808_I2S0_CLK_TXONLY, RK1808_I2S0_CLK_RXONLY },
1247 };
1248 
1249 static const struct txrx_config rk3308_txrx_config[] = {
1250     { 0xff300000, 0x308, RK3308_I2S0_CLK_TXONLY, RK3308_I2S0_CLK_RXONLY },
1251     { 0xff310000, 0x308, RK3308_I2S1_CLK_TXONLY, RK3308_I2S1_CLK_RXONLY },
1252 };
1253 
1254 static const struct txrx_config rk3568_txrx_config[] = {
1255     { 0xfe410000, 0x504, RK3568_I2S1_CLK_TXONLY, RK3568_I2S1_CLK_RXONLY },
1256     { 0xfe410000, 0x508, RK3568_I2S1_MCLK_TX_OE, RK3568_I2S1_MCLK_RX_OE },
1257     { 0xfe420000, 0x508, RK3568_I2S2_MCLK_OE, RK3568_I2S2_MCLK_OE },
1258     { 0xfe430000, 0x504, RK3568_I2S3_CLK_TXONLY, RK3568_I2S3_CLK_RXONLY },
1259     { 0xfe430000, 0x508, RK3568_I2S3_MCLK_TXONLY, RK3568_I2S3_MCLK_RXONLY },
1260     { 0xfe430000, 0x508, RK3568_I2S3_MCLK_OE, RK3568_I2S3_MCLK_OE },
1261 };
1262 
1263 static const struct txrx_config rv1126_txrx_config[] = {
1264     { 0xff800000, 0x10260, RV1126_I2S0_CLK_TXONLY, RV1126_I2S0_CLK_RXONLY },
1265 };
1266 
1267 static struct rk_i2s_soc_data px30_i2s_soc_data = {
1268     .softrst_offset = 0x0300,
1269     .configs = px30_txrx_config,
1270     .config_count = ARRAY_SIZE(px30_txrx_config),
1271     .init = common_soc_init,
1272 };
1273 
1274 static struct rk_i2s_soc_data rk1808_i2s_soc_data = {
1275     .softrst_offset = 0x0300,
1276     .configs = rk1808_txrx_config,
1277     .config_count = ARRAY_SIZE(rk1808_txrx_config),
1278     .init = common_soc_init,
1279 };
1280 
1281 static struct rk_i2s_soc_data rk3308_i2s_soc_data = {
1282     .softrst_offset = 0x0400,
1283     .grf_reg_offset = 0x0308,
1284     .grf_shift = 5,
1285     .configs = rk3308_txrx_config,
1286     .config_count = ARRAY_SIZE(rk3308_txrx_config),
1287     .init = common_soc_init,
1288 };
1289 
1290 static struct rk_i2s_soc_data rk3568_i2s_soc_data = {
1291     .softrst_offset = 0x0400,
1292     .configs = rk3568_txrx_config,
1293     .config_count = ARRAY_SIZE(rk3568_txrx_config),
1294     .init = common_soc_init,
1295 };
1296 
1297 static struct rk_i2s_soc_data rv1126_i2s_soc_data = {
1298     .softrst_offset = 0x0300,
1299     .configs = rv1126_txrx_config,
1300     .config_count = ARRAY_SIZE(rv1126_txrx_config),
1301     .init = common_soc_init,
1302 };
1303 
1304 static const struct of_device_id rockchip_i2s_tdm_match[] = {
1305     { .compatible = "rockchip,px30-i2s-tdm", .data = &px30_i2s_soc_data },
1306     { .compatible = "rockchip,rk1808-i2s-tdm", .data = &rk1808_i2s_soc_data },
1307     { .compatible = "rockchip,rk3308-i2s-tdm", .data = &rk3308_i2s_soc_data },
1308     { .compatible = "rockchip,rk3568-i2s-tdm", .data = &rk3568_i2s_soc_data },
1309     { .compatible = "rockchip,rv1126-i2s-tdm", .data = &rv1126_i2s_soc_data },
1310     {},
1311 };
1312 
1313 static const struct snd_soc_dai_driver i2s_tdm_dai = {
1314     .probe = rockchip_i2s_tdm_dai_probe,
1315     .ops = &rockchip_i2s_tdm_dai_ops,
1316 };
1317 
1318 static int rockchip_i2s_tdm_init_dai(struct rk_i2s_tdm_dev *i2s_tdm)
1319 {
1320     struct snd_soc_dai_driver *dai;
1321     struct property *dma_names;
1322     const char *dma_name;
1323     u64 formats = (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |
1324                SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |
1325                SNDRV_PCM_FMTBIT_S32_LE);
1326     struct device_node *node = i2s_tdm->dev->of_node;
1327 
1328     of_property_for_each_string(node, "dma-names", dma_names, dma_name) {
1329         if (!strcmp(dma_name, "tx"))
1330             i2s_tdm->has_playback = true;
1331         if (!strcmp(dma_name, "rx"))
1332             i2s_tdm->has_capture = true;
1333     }
1334 
1335     dai = devm_kmemdup(i2s_tdm->dev, &i2s_tdm_dai,
1336                sizeof(*dai), GFP_KERNEL);
1337     if (!dai)
1338         return -ENOMEM;
1339 
1340     if (i2s_tdm->has_playback) {
1341         dai->playback.stream_name  = "Playback";
1342         dai->playback.channels_min = 2;
1343         dai->playback.channels_max = 8;
1344         dai->playback.rates = SNDRV_PCM_RATE_8000_192000;
1345         dai->playback.formats = formats;
1346     }
1347 
1348     if (i2s_tdm->has_capture) {
1349         dai->capture.stream_name  = "Capture";
1350         dai->capture.channels_min = 2;
1351         dai->capture.channels_max = 8;
1352         dai->capture.rates = SNDRV_PCM_RATE_8000_192000;
1353         dai->capture.formats = formats;
1354     }
1355 
1356     if (i2s_tdm->clk_trcm != TRCM_TXRX)
1357         dai->symmetric_rate = 1;
1358 
1359     i2s_tdm->dai = dai;
1360 
1361     return 0;
1362 }
1363 
1364 static int rockchip_i2s_tdm_path_check(struct rk_i2s_tdm_dev *i2s_tdm,
1365                        int num,
1366                        bool is_rx_path)
1367 {
1368     unsigned int *i2s_data;
1369     int i, j;
1370 
1371     if (is_rx_path)
1372         i2s_data = i2s_tdm->i2s_sdis;
1373     else
1374         i2s_data = i2s_tdm->i2s_sdos;
1375 
1376     for (i = 0; i < num; i++) {
1377         if (i2s_data[i] > CH_GRP_MAX - 1) {
1378             dev_err(i2s_tdm->dev,
1379                 "%s path i2s_data[%d]: %d is too high, max is: %d\n",
1380                 is_rx_path ? "RX" : "TX",
1381                 i, i2s_data[i], CH_GRP_MAX);
1382             return -EINVAL;
1383         }
1384 
1385         for (j = 0; j < num; j++) {
1386             if (i == j)
1387                 continue;
1388 
1389             if (i2s_data[i] == i2s_data[j]) {
1390                 dev_err(i2s_tdm->dev,
1391                     "%s path invalid routed i2s_data: [%d]%d == [%d]%d\n",
1392                     is_rx_path ? "RX" : "TX",
1393                     i, i2s_data[i],
1394                     j, i2s_data[j]);
1395                 return -EINVAL;
1396             }
1397         }
1398     }
1399 
1400     return 0;
1401 }
1402 
1403 static void rockchip_i2s_tdm_tx_path_config(struct rk_i2s_tdm_dev *i2s_tdm,
1404                         int num)
1405 {
1406     int idx;
1407 
1408     for (idx = 0; idx < num; idx++) {
1409         regmap_update_bits(i2s_tdm->regmap, I2S_TXCR,
1410                    I2S_TXCR_PATH_MASK(idx),
1411                    I2S_TXCR_PATH(idx, i2s_tdm->i2s_sdos[idx]));
1412     }
1413 }
1414 
1415 static void rockchip_i2s_tdm_rx_path_config(struct rk_i2s_tdm_dev *i2s_tdm,
1416                         int num)
1417 {
1418     int idx;
1419 
1420     for (idx = 0; idx < num; idx++) {
1421         regmap_update_bits(i2s_tdm->regmap, I2S_RXCR,
1422                    I2S_RXCR_PATH_MASK(idx),
1423                    I2S_RXCR_PATH(idx, i2s_tdm->i2s_sdis[idx]));
1424     }
1425 }
1426 
1427 static void rockchip_i2s_tdm_path_config(struct rk_i2s_tdm_dev *i2s_tdm,
1428                      int num, bool is_rx_path)
1429 {
1430     if (is_rx_path)
1431         rockchip_i2s_tdm_rx_path_config(i2s_tdm, num);
1432     else
1433         rockchip_i2s_tdm_tx_path_config(i2s_tdm, num);
1434 }
1435 
1436 static int rockchip_i2s_tdm_get_calibrate_mclks(struct rk_i2s_tdm_dev *i2s_tdm)
1437 {
1438     int num_mclks = 0;
1439 
1440     i2s_tdm->mclk_tx_src = devm_clk_get(i2s_tdm->dev, "mclk_tx_src");
1441     if (!IS_ERR(i2s_tdm->mclk_tx_src))
1442         num_mclks++;
1443 
1444     i2s_tdm->mclk_rx_src = devm_clk_get(i2s_tdm->dev, "mclk_rx_src");
1445     if (!IS_ERR(i2s_tdm->mclk_rx_src))
1446         num_mclks++;
1447 
1448     i2s_tdm->mclk_root0 = devm_clk_get(i2s_tdm->dev, "mclk_root0");
1449     if (!IS_ERR(i2s_tdm->mclk_root0))
1450         num_mclks++;
1451 
1452     i2s_tdm->mclk_root1 = devm_clk_get(i2s_tdm->dev, "mclk_root1");
1453     if (!IS_ERR(i2s_tdm->mclk_root1))
1454         num_mclks++;
1455 
1456     if (num_mclks < 4 && num_mclks != 0)
1457         return -ENOENT;
1458 
1459     if (num_mclks == 4)
1460         i2s_tdm->mclk_calibrate = 1;
1461 
1462     return 0;
1463 }
1464 
1465 static int rockchip_i2s_tdm_path_prepare(struct rk_i2s_tdm_dev *i2s_tdm,
1466                      struct device_node *np,
1467                      bool is_rx_path)
1468 {
1469     char *i2s_tx_path_prop = "rockchip,i2s-tx-route";
1470     char *i2s_rx_path_prop = "rockchip,i2s-rx-route";
1471     char *i2s_path_prop;
1472     unsigned int *i2s_data;
1473     int num, ret = 0;
1474 
1475     if (is_rx_path) {
1476         i2s_path_prop = i2s_rx_path_prop;
1477         i2s_data = i2s_tdm->i2s_sdis;
1478     } else {
1479         i2s_path_prop = i2s_tx_path_prop;
1480         i2s_data = i2s_tdm->i2s_sdos;
1481     }
1482 
1483     num = of_count_phandle_with_args(np, i2s_path_prop, NULL);
1484     if (num < 0) {
1485         if (num != -ENOENT) {
1486             dev_err(i2s_tdm->dev,
1487                 "Failed to read '%s' num: %d\n",
1488                 i2s_path_prop, num);
1489             ret = num;
1490         }
1491         return ret;
1492     } else if (num != CH_GRP_MAX) {
1493         dev_err(i2s_tdm->dev,
1494             "The num: %d should be: %d\n", num, CH_GRP_MAX);
1495         return -EINVAL;
1496     }
1497 
1498     ret = of_property_read_u32_array(np, i2s_path_prop,
1499                      i2s_data, num);
1500     if (ret < 0) {
1501         dev_err(i2s_tdm->dev,
1502             "Failed to read '%s': %d\n",
1503             i2s_path_prop, ret);
1504         return ret;
1505     }
1506 
1507     ret = rockchip_i2s_tdm_path_check(i2s_tdm, num, is_rx_path);
1508     if (ret < 0) {
1509         dev_err(i2s_tdm->dev,
1510             "Failed to check i2s data bus: %d\n", ret);
1511         return ret;
1512     }
1513 
1514     rockchip_i2s_tdm_path_config(i2s_tdm, num, is_rx_path);
1515 
1516     return 0;
1517 }
1518 
1519 static int rockchip_i2s_tdm_tx_path_prepare(struct rk_i2s_tdm_dev *i2s_tdm,
1520                         struct device_node *np)
1521 {
1522     return rockchip_i2s_tdm_path_prepare(i2s_tdm, np, 0);
1523 }
1524 
1525 static int rockchip_i2s_tdm_rx_path_prepare(struct rk_i2s_tdm_dev *i2s_tdm,
1526                         struct device_node *np)
1527 {
1528     return rockchip_i2s_tdm_path_prepare(i2s_tdm, np, 1);
1529 }
1530 
1531 static int rockchip_i2s_tdm_probe(struct platform_device *pdev)
1532 {
1533     struct device_node *node = pdev->dev.of_node;
1534     const struct of_device_id *of_id;
1535     struct rk_i2s_tdm_dev *i2s_tdm;
1536     struct resource *res;
1537     void __iomem *regs;
1538     int ret;
1539 
1540     i2s_tdm = devm_kzalloc(&pdev->dev, sizeof(*i2s_tdm), GFP_KERNEL);
1541     if (!i2s_tdm)
1542         return -ENOMEM;
1543 
1544     i2s_tdm->dev = &pdev->dev;
1545 
1546     of_id = of_match_device(rockchip_i2s_tdm_match, &pdev->dev);
1547     if (!of_id || !of_id->data)
1548         return -EINVAL;
1549 
1550     spin_lock_init(&i2s_tdm->lock);
1551     i2s_tdm->soc_data = (struct rk_i2s_soc_data *)of_id->data;
1552 
1553     i2s_tdm->frame_width = 64;
1554 
1555     i2s_tdm->clk_trcm = TRCM_TXRX;
1556     if (of_property_read_bool(node, "rockchip,trcm-sync-tx-only"))
1557         i2s_tdm->clk_trcm = TRCM_TX;
1558     if (of_property_read_bool(node, "rockchip,trcm-sync-rx-only")) {
1559         if (i2s_tdm->clk_trcm) {
1560             dev_err(i2s_tdm->dev, "invalid trcm-sync configuration\n");
1561             return -EINVAL;
1562         }
1563         i2s_tdm->clk_trcm = TRCM_RX;
1564     }
1565 
1566     ret = rockchip_i2s_tdm_init_dai(i2s_tdm);
1567     if (ret)
1568         return ret;
1569 
1570     i2s_tdm->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf");
1571     if (IS_ERR(i2s_tdm->grf))
1572         return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->grf),
1573                      "Error in rockchip,grf\n");
1574 
1575     i2s_tdm->tx_reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
1576                                       "tx-m");
1577     if (IS_ERR(i2s_tdm->tx_reset)) {
1578         ret = PTR_ERR(i2s_tdm->tx_reset);
1579         return dev_err_probe(i2s_tdm->dev, ret,
1580                      "Error in tx-m reset control\n");
1581     }
1582 
1583     i2s_tdm->rx_reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
1584                                       "rx-m");
1585     if (IS_ERR(i2s_tdm->rx_reset)) {
1586         ret = PTR_ERR(i2s_tdm->rx_reset);
1587         return dev_err_probe(i2s_tdm->dev, ret,
1588                      "Error in rx-m reset control\n");
1589     }
1590 
1591     i2s_tdm->hclk = devm_clk_get(&pdev->dev, "hclk");
1592     if (IS_ERR(i2s_tdm->hclk)) {
1593         return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->hclk),
1594                      "Failed to get clock hclk\n");
1595     }
1596 
1597     i2s_tdm->mclk_tx = devm_clk_get(&pdev->dev, "mclk_tx");
1598     if (IS_ERR(i2s_tdm->mclk_tx)) {
1599         return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->mclk_tx),
1600                      "Failed to get clock mclk_tx\n");
1601     }
1602 
1603     i2s_tdm->mclk_rx = devm_clk_get(&pdev->dev, "mclk_rx");
1604     if (IS_ERR(i2s_tdm->mclk_rx)) {
1605         return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->mclk_rx),
1606                      "Failed to get clock mclk_rx\n");
1607     }
1608 
1609     i2s_tdm->io_multiplex =
1610         of_property_read_bool(node, "rockchip,io-multiplex");
1611 
1612     ret = rockchip_i2s_tdm_get_calibrate_mclks(i2s_tdm);
1613     if (ret)
1614         return dev_err_probe(i2s_tdm->dev, ret,
1615                      "mclk-calibrate clocks missing");
1616 
1617     regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1618     if (IS_ERR(regs)) {
1619         return dev_err_probe(i2s_tdm->dev, PTR_ERR(regs),
1620                      "Failed to get resource IORESOURCE_MEM\n");
1621     }
1622 
1623     i2s_tdm->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
1624                         &rockchip_i2s_tdm_regmap_config);
1625     if (IS_ERR(i2s_tdm->regmap)) {
1626         return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->regmap),
1627                      "Failed to initialise regmap\n");
1628     }
1629 
1630     if (i2s_tdm->has_playback) {
1631         i2s_tdm->playback_dma_data.addr = res->start + I2S_TXDR;
1632         i2s_tdm->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1633         i2s_tdm->playback_dma_data.maxburst = 8;
1634     }
1635 
1636     if (i2s_tdm->has_capture) {
1637         i2s_tdm->capture_dma_data.addr = res->start + I2S_RXDR;
1638         i2s_tdm->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1639         i2s_tdm->capture_dma_data.maxburst = 8;
1640     }
1641 
1642     ret = rockchip_i2s_tdm_tx_path_prepare(i2s_tdm, node);
1643     if (ret < 0) {
1644         dev_err(&pdev->dev, "I2S TX path prepare failed: %d\n", ret);
1645         return ret;
1646     }
1647 
1648     ret = rockchip_i2s_tdm_rx_path_prepare(i2s_tdm, node);
1649     if (ret < 0) {
1650         dev_err(&pdev->dev, "I2S RX path prepare failed: %d\n", ret);
1651         return ret;
1652     }
1653 
1654     dev_set_drvdata(&pdev->dev, i2s_tdm);
1655 
1656     ret = clk_prepare_enable(i2s_tdm->hclk);
1657     if (ret) {
1658         return dev_err_probe(i2s_tdm->dev, ret,
1659                      "Failed to enable clock hclk\n");
1660     }
1661 
1662     ret = i2s_tdm_prepare_enable_mclk(i2s_tdm);
1663     if (ret) {
1664         ret = dev_err_probe(i2s_tdm->dev, ret,
1665                     "Failed to enable one or more mclks\n");
1666         goto err_disable_hclk;
1667     }
1668 
1669     if (i2s_tdm->mclk_calibrate) {
1670         i2s_tdm->mclk_root0_initial_freq = clk_get_rate(i2s_tdm->mclk_root0);
1671         i2s_tdm->mclk_root1_initial_freq = clk_get_rate(i2s_tdm->mclk_root1);
1672         i2s_tdm->mclk_root0_freq = i2s_tdm->mclk_root0_initial_freq;
1673         i2s_tdm->mclk_root1_freq = i2s_tdm->mclk_root1_initial_freq;
1674     }
1675 
1676     pm_runtime_enable(&pdev->dev);
1677 
1678     regmap_update_bits(i2s_tdm->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
1679                I2S_DMACR_TDL(16));
1680     regmap_update_bits(i2s_tdm->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
1681                I2S_DMACR_RDL(16));
1682     regmap_update_bits(i2s_tdm->regmap, I2S_CKR, I2S_CKR_TRCM_MASK,
1683                i2s_tdm->clk_trcm << I2S_CKR_TRCM_SHIFT);
1684 
1685     if (i2s_tdm->soc_data && i2s_tdm->soc_data->init)
1686         i2s_tdm->soc_data->init(&pdev->dev, res->start);
1687 
1688     ret = devm_snd_soc_register_component(&pdev->dev,
1689                           &rockchip_i2s_tdm_component,
1690                           i2s_tdm->dai, 1);
1691 
1692     if (ret) {
1693         dev_err(&pdev->dev, "Could not register DAI\n");
1694         goto err_suspend;
1695     }
1696 
1697     ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
1698     if (ret) {
1699         dev_err(&pdev->dev, "Could not register PCM\n");
1700         goto err_suspend;
1701     }
1702 
1703     return 0;
1704 
1705 err_suspend:
1706     if (!pm_runtime_status_suspended(&pdev->dev))
1707         i2s_tdm_runtime_suspend(&pdev->dev);
1708     pm_runtime_disable(&pdev->dev);
1709 
1710 err_disable_hclk:
1711     clk_disable_unprepare(i2s_tdm->hclk);
1712 
1713     return ret;
1714 }
1715 
1716 static int rockchip_i2s_tdm_remove(struct platform_device *pdev)
1717 {
1718     if (!pm_runtime_status_suspended(&pdev->dev))
1719         i2s_tdm_runtime_suspend(&pdev->dev);
1720 
1721     pm_runtime_disable(&pdev->dev);
1722 
1723     return 0;
1724 }
1725 
1726 static int __maybe_unused rockchip_i2s_tdm_suspend(struct device *dev)
1727 {
1728     struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
1729 
1730     regcache_mark_dirty(i2s_tdm->regmap);
1731 
1732     return 0;
1733 }
1734 
1735 static int __maybe_unused rockchip_i2s_tdm_resume(struct device *dev)
1736 {
1737     struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
1738     int ret;
1739 
1740     ret = pm_runtime_resume_and_get(dev);
1741     if (ret < 0)
1742         return ret;
1743     ret = regcache_sync(i2s_tdm->regmap);
1744     pm_runtime_put(dev);
1745 
1746     return ret;
1747 }
1748 
1749 static const struct dev_pm_ops rockchip_i2s_tdm_pm_ops = {
1750     SET_RUNTIME_PM_OPS(i2s_tdm_runtime_suspend, i2s_tdm_runtime_resume,
1751                NULL)
1752     SET_SYSTEM_SLEEP_PM_OPS(rockchip_i2s_tdm_suspend,
1753                 rockchip_i2s_tdm_resume)
1754 };
1755 
1756 static struct platform_driver rockchip_i2s_tdm_driver = {
1757     .probe = rockchip_i2s_tdm_probe,
1758     .remove = rockchip_i2s_tdm_remove,
1759     .driver = {
1760         .name = DRV_NAME,
1761         .of_match_table = of_match_ptr(rockchip_i2s_tdm_match),
1762         .pm = &rockchip_i2s_tdm_pm_ops,
1763     },
1764 };
1765 module_platform_driver(rockchip_i2s_tdm_driver);
1766 
1767 MODULE_DESCRIPTION("ROCKCHIP I2S/TDM ASoC Interface");
1768 MODULE_AUTHOR("Sugar Zhang <sugar.zhang@rock-chips.com>");
1769 MODULE_LICENSE("GPL v2");
1770 MODULE_ALIAS("platform:" DRV_NAME);
1771 MODULE_DEVICE_TABLE(of, rockchip_i2s_tdm_match);
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