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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /* sound/soc/rockchip/rockchip_i2s.c
0003  *
0004  * ALSA SoC Audio Layer - Rockchip I2S Controller driver
0005  *
0006  * Copyright (c) 2014 Rockchip Electronics Co. Ltd.
0007  * Author: Jianqun <jay.xu@rock-chips.com>
0008  */
0009 
0010 #include <linux/module.h>
0011 #include <linux/mfd/syscon.h>
0012 #include <linux/delay.h>
0013 #include <linux/of_gpio.h>
0014 #include <linux/of_device.h>
0015 #include <linux/clk.h>
0016 #include <linux/pinctrl/consumer.h>
0017 #include <linux/pm_runtime.h>
0018 #include <linux/regmap.h>
0019 #include <linux/spinlock.h>
0020 #include <sound/pcm_params.h>
0021 #include <sound/dmaengine_pcm.h>
0022 
0023 #include "rockchip_i2s.h"
0024 
0025 #define DRV_NAME "rockchip-i2s"
0026 
0027 struct rk_i2s_pins {
0028     u32 reg_offset;
0029     u32 shift;
0030 };
0031 
0032 struct rk_i2s_dev {
0033     struct device *dev;
0034 
0035     struct clk *hclk;
0036     struct clk *mclk;
0037 
0038     struct snd_dmaengine_dai_dma_data capture_dma_data;
0039     struct snd_dmaengine_dai_dma_data playback_dma_data;
0040 
0041     struct regmap *regmap;
0042     struct regmap *grf;
0043 
0044     bool has_capture;
0045     bool has_playback;
0046 
0047 /*
0048  * Used to indicate the tx/rx status.
0049  * I2S controller hopes to start the tx and rx together,
0050  * also to stop them when they are both try to stop.
0051 */
0052     bool tx_start;
0053     bool rx_start;
0054     bool is_master_mode;
0055     const struct rk_i2s_pins *pins;
0056     unsigned int bclk_ratio;
0057     spinlock_t lock; /* tx/rx lock */
0058     struct pinctrl *pinctrl;
0059     struct pinctrl_state *bclk_on;
0060     struct pinctrl_state *bclk_off;
0061 };
0062 
0063 static int i2s_pinctrl_select_bclk_on(struct rk_i2s_dev *i2s)
0064 {
0065     int ret = 0;
0066 
0067     if (!IS_ERR(i2s->pinctrl) && !IS_ERR_OR_NULL(i2s->bclk_on))
0068         ret = pinctrl_select_state(i2s->pinctrl, i2s->bclk_on);
0069 
0070     if (ret)
0071         dev_err(i2s->dev, "bclk enable failed %d\n", ret);
0072 
0073     return ret;
0074 }
0075 
0076 static int i2s_pinctrl_select_bclk_off(struct rk_i2s_dev *i2s)
0077 {
0078 
0079     int ret = 0;
0080 
0081     if (!IS_ERR(i2s->pinctrl) && !IS_ERR_OR_NULL(i2s->bclk_off))
0082         ret = pinctrl_select_state(i2s->pinctrl, i2s->bclk_off);
0083 
0084     if (ret)
0085         dev_err(i2s->dev, "bclk disable failed %d\n", ret);
0086 
0087     return ret;
0088 }
0089 
0090 static int i2s_runtime_suspend(struct device *dev)
0091 {
0092     struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
0093 
0094     regcache_cache_only(i2s->regmap, true);
0095     clk_disable_unprepare(i2s->mclk);
0096 
0097     return 0;
0098 }
0099 
0100 static int i2s_runtime_resume(struct device *dev)
0101 {
0102     struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
0103     int ret;
0104 
0105     ret = clk_prepare_enable(i2s->mclk);
0106     if (ret) {
0107         dev_err(i2s->dev, "clock enable failed %d\n", ret);
0108         return ret;
0109     }
0110 
0111     regcache_cache_only(i2s->regmap, false);
0112     regcache_mark_dirty(i2s->regmap);
0113 
0114     ret = regcache_sync(i2s->regmap);
0115     if (ret)
0116         clk_disable_unprepare(i2s->mclk);
0117 
0118     return ret;
0119 }
0120 
0121 static inline struct rk_i2s_dev *to_info(struct snd_soc_dai *dai)
0122 {
0123     return snd_soc_dai_get_drvdata(dai);
0124 }
0125 
0126 static int rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
0127 {
0128     unsigned int val = 0;
0129     int retry = 10;
0130     int ret = 0;
0131 
0132     spin_lock(&i2s->lock);
0133     if (on) {
0134         ret = regmap_update_bits(i2s->regmap, I2S_DMACR,
0135                      I2S_DMACR_TDE_ENABLE,
0136                      I2S_DMACR_TDE_ENABLE);
0137         if (ret < 0)
0138             goto end;
0139         ret = regmap_update_bits(i2s->regmap, I2S_XFER,
0140                      I2S_XFER_TXS_START | I2S_XFER_RXS_START,
0141                      I2S_XFER_TXS_START | I2S_XFER_RXS_START);
0142         if (ret < 0)
0143             goto end;
0144         i2s->tx_start = true;
0145     } else {
0146         i2s->tx_start = false;
0147 
0148         ret = regmap_update_bits(i2s->regmap, I2S_DMACR,
0149                      I2S_DMACR_TDE_ENABLE,
0150                      I2S_DMACR_TDE_DISABLE);
0151         if (ret < 0)
0152             goto end;
0153 
0154         if (!i2s->rx_start) {
0155             ret = regmap_update_bits(i2s->regmap, I2S_XFER,
0156                          I2S_XFER_TXS_START | I2S_XFER_RXS_START,
0157                          I2S_XFER_TXS_STOP | I2S_XFER_RXS_STOP);
0158             if (ret < 0)
0159                 goto end;
0160             udelay(150);
0161             ret = regmap_update_bits(i2s->regmap, I2S_CLR,
0162                          I2S_CLR_TXC | I2S_CLR_RXC,
0163                          I2S_CLR_TXC | I2S_CLR_RXC);
0164             if (ret < 0)
0165                 goto end;
0166             regmap_read(i2s->regmap, I2S_CLR, &val);
0167 
0168             /* Should wait for clear operation to finish */
0169             while (val) {
0170                 regmap_read(i2s->regmap, I2S_CLR, &val);
0171                 retry--;
0172                 if (!retry) {
0173                     dev_warn(i2s->dev, "fail to clear\n");
0174                     ret = -EBUSY;
0175                     break;
0176                 }
0177             }
0178         }
0179     }
0180 end:
0181     spin_unlock(&i2s->lock);
0182     if (ret < 0)
0183         dev_err(i2s->dev, "lrclk update failed\n");
0184 
0185     return ret;
0186 }
0187 
0188 static int rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
0189 {
0190     unsigned int val = 0;
0191     int retry = 10;
0192     int ret = 0;
0193 
0194     spin_lock(&i2s->lock);
0195     if (on) {
0196         ret = regmap_update_bits(i2s->regmap, I2S_DMACR,
0197                      I2S_DMACR_RDE_ENABLE,
0198                      I2S_DMACR_RDE_ENABLE);
0199         if (ret < 0)
0200             goto end;
0201 
0202         ret = regmap_update_bits(i2s->regmap, I2S_XFER,
0203                      I2S_XFER_TXS_START | I2S_XFER_RXS_START,
0204                      I2S_XFER_TXS_START | I2S_XFER_RXS_START);
0205         if (ret < 0)
0206             goto end;
0207         i2s->rx_start = true;
0208     } else {
0209         i2s->rx_start = false;
0210 
0211         ret = regmap_update_bits(i2s->regmap, I2S_DMACR,
0212                      I2S_DMACR_RDE_ENABLE,
0213                      I2S_DMACR_RDE_DISABLE);
0214         if (ret < 0)
0215             goto end;
0216 
0217         if (!i2s->tx_start) {
0218             ret = regmap_update_bits(i2s->regmap, I2S_XFER,
0219                          I2S_XFER_TXS_START | I2S_XFER_RXS_START,
0220                          I2S_XFER_TXS_STOP | I2S_XFER_RXS_STOP);
0221             if (ret < 0)
0222                 goto end;
0223             udelay(150);
0224             ret = regmap_update_bits(i2s->regmap, I2S_CLR,
0225                          I2S_CLR_TXC | I2S_CLR_RXC,
0226                          I2S_CLR_TXC | I2S_CLR_RXC);
0227             if (ret < 0)
0228                 goto end;
0229             regmap_read(i2s->regmap, I2S_CLR, &val);
0230             /* Should wait for clear operation to finish */
0231             while (val) {
0232                 regmap_read(i2s->regmap, I2S_CLR, &val);
0233                 retry--;
0234                 if (!retry) {
0235                     dev_warn(i2s->dev, "fail to clear\n");
0236                     ret = -EBUSY;
0237                     break;
0238                 }
0239             }
0240         }
0241     }
0242 end:
0243     spin_unlock(&i2s->lock);
0244     if (ret < 0)
0245         dev_err(i2s->dev, "lrclk update failed\n");
0246 
0247     return ret;
0248 }
0249 
0250 static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
0251                 unsigned int fmt)
0252 {
0253     struct rk_i2s_dev *i2s = to_info(cpu_dai);
0254     unsigned int mask = 0, val = 0;
0255     int ret = 0;
0256 
0257     pm_runtime_get_sync(cpu_dai->dev);
0258     mask = I2S_CKR_MSS_MASK;
0259     switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
0260     case SND_SOC_DAIFMT_BP_FP:
0261         /* Set source clock in Master mode */
0262         val = I2S_CKR_MSS_MASTER;
0263         i2s->is_master_mode = true;
0264         break;
0265     case SND_SOC_DAIFMT_BC_FC:
0266         val = I2S_CKR_MSS_SLAVE;
0267         i2s->is_master_mode = false;
0268         break;
0269     default:
0270         ret = -EINVAL;
0271         goto err_pm_put;
0272     }
0273 
0274     regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
0275 
0276     mask = I2S_CKR_CKP_MASK | I2S_CKR_TLP_MASK | I2S_CKR_RLP_MASK;
0277     switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
0278     case SND_SOC_DAIFMT_NB_NF:
0279         val = I2S_CKR_CKP_NORMAL |
0280               I2S_CKR_TLP_NORMAL |
0281               I2S_CKR_RLP_NORMAL;
0282         break;
0283     case SND_SOC_DAIFMT_NB_IF:
0284         val = I2S_CKR_CKP_NORMAL |
0285               I2S_CKR_TLP_INVERTED |
0286               I2S_CKR_RLP_INVERTED;
0287         break;
0288     case SND_SOC_DAIFMT_IB_NF:
0289         val = I2S_CKR_CKP_INVERTED |
0290               I2S_CKR_TLP_NORMAL |
0291               I2S_CKR_RLP_NORMAL;
0292         break;
0293     case SND_SOC_DAIFMT_IB_IF:
0294         val = I2S_CKR_CKP_INVERTED |
0295               I2S_CKR_TLP_INVERTED |
0296               I2S_CKR_RLP_INVERTED;
0297         break;
0298     default:
0299         ret = -EINVAL;
0300         goto err_pm_put;
0301     }
0302 
0303     regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
0304 
0305     mask = I2S_TXCR_IBM_MASK | I2S_TXCR_TFS_MASK | I2S_TXCR_PBM_MASK;
0306     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0307     case SND_SOC_DAIFMT_RIGHT_J:
0308         val = I2S_TXCR_IBM_RSJM;
0309         break;
0310     case SND_SOC_DAIFMT_LEFT_J:
0311         val = I2S_TXCR_IBM_LSJM;
0312         break;
0313     case SND_SOC_DAIFMT_I2S:
0314         val = I2S_TXCR_IBM_NORMAL;
0315         break;
0316     case SND_SOC_DAIFMT_DSP_A: /* PCM delay 1 bit mode */
0317         val = I2S_TXCR_TFS_PCM | I2S_TXCR_PBM_MODE(1);
0318         break;
0319     case SND_SOC_DAIFMT_DSP_B: /* PCM no delay mode */
0320         val = I2S_TXCR_TFS_PCM;
0321         break;
0322     default:
0323         ret = -EINVAL;
0324         goto err_pm_put;
0325     }
0326 
0327     regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val);
0328 
0329     mask = I2S_RXCR_IBM_MASK | I2S_RXCR_TFS_MASK | I2S_RXCR_PBM_MASK;
0330     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0331     case SND_SOC_DAIFMT_RIGHT_J:
0332         val = I2S_RXCR_IBM_RSJM;
0333         break;
0334     case SND_SOC_DAIFMT_LEFT_J:
0335         val = I2S_RXCR_IBM_LSJM;
0336         break;
0337     case SND_SOC_DAIFMT_I2S:
0338         val = I2S_RXCR_IBM_NORMAL;
0339         break;
0340     case SND_SOC_DAIFMT_DSP_A: /* PCM delay 1 bit mode */
0341         val = I2S_RXCR_TFS_PCM | I2S_RXCR_PBM_MODE(1);
0342         break;
0343     case SND_SOC_DAIFMT_DSP_B: /* PCM no delay mode */
0344         val = I2S_RXCR_TFS_PCM;
0345         break;
0346     default:
0347         ret = -EINVAL;
0348         goto err_pm_put;
0349     }
0350 
0351     regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val);
0352 
0353 err_pm_put:
0354     pm_runtime_put(cpu_dai->dev);
0355 
0356     return ret;
0357 }
0358 
0359 static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
0360                   struct snd_pcm_hw_params *params,
0361                   struct snd_soc_dai *dai)
0362 {
0363     struct rk_i2s_dev *i2s = to_info(dai);
0364     struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
0365     unsigned int val = 0;
0366     unsigned int mclk_rate, bclk_rate, div_bclk, div_lrck;
0367 
0368     if (i2s->is_master_mode) {
0369         mclk_rate = clk_get_rate(i2s->mclk);
0370         bclk_rate = i2s->bclk_ratio * params_rate(params);
0371         if (!bclk_rate)
0372             return -EINVAL;
0373 
0374         div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate);
0375         div_lrck = bclk_rate / params_rate(params);
0376         regmap_update_bits(i2s->regmap, I2S_CKR,
0377                    I2S_CKR_MDIV_MASK,
0378                    I2S_CKR_MDIV(div_bclk));
0379 
0380         regmap_update_bits(i2s->regmap, I2S_CKR,
0381                    I2S_CKR_TSD_MASK |
0382                    I2S_CKR_RSD_MASK,
0383                    I2S_CKR_TSD(div_lrck) |
0384                    I2S_CKR_RSD(div_lrck));
0385     }
0386 
0387     switch (params_format(params)) {
0388     case SNDRV_PCM_FORMAT_S8:
0389         val |= I2S_TXCR_VDW(8);
0390         break;
0391     case SNDRV_PCM_FORMAT_S16_LE:
0392         val |= I2S_TXCR_VDW(16);
0393         break;
0394     case SNDRV_PCM_FORMAT_S20_3LE:
0395         val |= I2S_TXCR_VDW(20);
0396         break;
0397     case SNDRV_PCM_FORMAT_S24_LE:
0398         val |= I2S_TXCR_VDW(24);
0399         break;
0400     case SNDRV_PCM_FORMAT_S32_LE:
0401         val |= I2S_TXCR_VDW(32);
0402         break;
0403     default:
0404         return -EINVAL;
0405     }
0406 
0407     switch (params_channels(params)) {
0408     case 8:
0409         val |= I2S_CHN_8;
0410         break;
0411     case 6:
0412         val |= I2S_CHN_6;
0413         break;
0414     case 4:
0415         val |= I2S_CHN_4;
0416         break;
0417     case 2:
0418         val |= I2S_CHN_2;
0419         break;
0420     default:
0421         dev_err(i2s->dev, "invalid channel: %d\n",
0422             params_channels(params));
0423         return -EINVAL;
0424     }
0425 
0426     if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
0427         regmap_update_bits(i2s->regmap, I2S_RXCR,
0428                    I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
0429                    val);
0430     else
0431         regmap_update_bits(i2s->regmap, I2S_TXCR,
0432                    I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
0433                    val);
0434 
0435     if (!IS_ERR(i2s->grf) && i2s->pins) {
0436         regmap_read(i2s->regmap, I2S_TXCR, &val);
0437         val &= I2S_TXCR_CSR_MASK;
0438 
0439         switch (val) {
0440         case I2S_CHN_4:
0441             val = I2S_IO_4CH_OUT_6CH_IN;
0442             break;
0443         case I2S_CHN_6:
0444             val = I2S_IO_6CH_OUT_4CH_IN;
0445             break;
0446         case I2S_CHN_8:
0447             val = I2S_IO_8CH_OUT_2CH_IN;
0448             break;
0449         default:
0450             val = I2S_IO_2CH_OUT_8CH_IN;
0451             break;
0452         }
0453 
0454         val <<= i2s->pins->shift;
0455         val |= (I2S_IO_DIRECTION_MASK << i2s->pins->shift) << 16;
0456         regmap_write(i2s->grf, i2s->pins->reg_offset, val);
0457     }
0458 
0459     regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
0460                I2S_DMACR_TDL(16));
0461     regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
0462                I2S_DMACR_RDL(16));
0463 
0464     val = I2S_CKR_TRCM_TXRX;
0465     if (dai->driver->symmetric_rate && rtd->dai_link->symmetric_rate)
0466         val = I2S_CKR_TRCM_TXONLY;
0467 
0468     regmap_update_bits(i2s->regmap, I2S_CKR,
0469                I2S_CKR_TRCM_MASK,
0470                val);
0471     return 0;
0472 }
0473 
0474 static int rockchip_i2s_trigger(struct snd_pcm_substream *substream,
0475                 int cmd, struct snd_soc_dai *dai)
0476 {
0477     struct rk_i2s_dev *i2s = to_info(dai);
0478     int ret = 0;
0479 
0480     switch (cmd) {
0481     case SNDRV_PCM_TRIGGER_START:
0482     case SNDRV_PCM_TRIGGER_RESUME:
0483     case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
0484         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
0485             ret = rockchip_snd_rxctrl(i2s, 1);
0486         else
0487             ret = rockchip_snd_txctrl(i2s, 1);
0488         if (ret < 0)
0489             return ret;
0490         i2s_pinctrl_select_bclk_on(i2s);
0491         break;
0492     case SNDRV_PCM_TRIGGER_SUSPEND:
0493     case SNDRV_PCM_TRIGGER_STOP:
0494     case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
0495         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
0496             if (!i2s->tx_start)
0497                 i2s_pinctrl_select_bclk_off(i2s);
0498             ret = rockchip_snd_rxctrl(i2s, 0);
0499         } else {
0500             if (!i2s->rx_start)
0501                 i2s_pinctrl_select_bclk_off(i2s);
0502             ret = rockchip_snd_txctrl(i2s, 0);
0503         }
0504         break;
0505     default:
0506         ret = -EINVAL;
0507         break;
0508     }
0509 
0510     return ret;
0511 }
0512 
0513 static int rockchip_i2s_set_bclk_ratio(struct snd_soc_dai *dai,
0514                        unsigned int ratio)
0515 {
0516     struct rk_i2s_dev *i2s = to_info(dai);
0517 
0518     i2s->bclk_ratio = ratio;
0519 
0520     return 0;
0521 }
0522 
0523 static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
0524                    unsigned int freq, int dir)
0525 {
0526     struct rk_i2s_dev *i2s = to_info(cpu_dai);
0527     int ret;
0528 
0529     if (freq == 0)
0530         return 0;
0531 
0532     ret = clk_set_rate(i2s->mclk, freq);
0533     if (ret)
0534         dev_err(i2s->dev, "Fail to set mclk %d\n", ret);
0535 
0536     return ret;
0537 }
0538 
0539 static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai)
0540 {
0541     struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);
0542 
0543     snd_soc_dai_init_dma_data(dai,
0544         i2s->has_playback ? &i2s->playback_dma_data : NULL,
0545         i2s->has_capture  ? &i2s->capture_dma_data  : NULL);
0546 
0547     return 0;
0548 }
0549 
0550 static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = {
0551     .hw_params = rockchip_i2s_hw_params,
0552     .set_bclk_ratio = rockchip_i2s_set_bclk_ratio,
0553     .set_sysclk = rockchip_i2s_set_sysclk,
0554     .set_fmt = rockchip_i2s_set_fmt,
0555     .trigger = rockchip_i2s_trigger,
0556 };
0557 
0558 static struct snd_soc_dai_driver rockchip_i2s_dai = {
0559     .probe = rockchip_i2s_dai_probe,
0560     .ops = &rockchip_i2s_dai_ops,
0561     .symmetric_rate = 1,
0562 };
0563 
0564 static const struct snd_soc_component_driver rockchip_i2s_component = {
0565     .name = DRV_NAME,
0566     .legacy_dai_naming = 1,
0567 };
0568 
0569 static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg)
0570 {
0571     switch (reg) {
0572     case I2S_TXCR:
0573     case I2S_RXCR:
0574     case I2S_CKR:
0575     case I2S_DMACR:
0576     case I2S_INTCR:
0577     case I2S_XFER:
0578     case I2S_CLR:
0579     case I2S_TXDR:
0580         return true;
0581     default:
0582         return false;
0583     }
0584 }
0585 
0586 static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg)
0587 {
0588     switch (reg) {
0589     case I2S_TXCR:
0590     case I2S_RXCR:
0591     case I2S_CKR:
0592     case I2S_DMACR:
0593     case I2S_INTCR:
0594     case I2S_XFER:
0595     case I2S_CLR:
0596     case I2S_TXDR:
0597     case I2S_RXDR:
0598     case I2S_FIFOLR:
0599     case I2S_INTSR:
0600         return true;
0601     default:
0602         return false;
0603     }
0604 }
0605 
0606 static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg)
0607 {
0608     switch (reg) {
0609     case I2S_INTSR:
0610     case I2S_CLR:
0611     case I2S_FIFOLR:
0612     case I2S_TXDR:
0613     case I2S_RXDR:
0614         return true;
0615     default:
0616         return false;
0617     }
0618 }
0619 
0620 static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg)
0621 {
0622     switch (reg) {
0623     case I2S_RXDR:
0624         return true;
0625     default:
0626         return false;
0627     }
0628 }
0629 
0630 static const struct reg_default rockchip_i2s_reg_defaults[] = {
0631     {0x00, 0x0000000f},
0632     {0x04, 0x0000000f},
0633     {0x08, 0x00071f1f},
0634     {0x10, 0x001f0000},
0635     {0x14, 0x01f00000},
0636 };
0637 
0638 static const struct regmap_config rockchip_i2s_regmap_config = {
0639     .reg_bits = 32,
0640     .reg_stride = 4,
0641     .val_bits = 32,
0642     .max_register = I2S_RXDR,
0643     .reg_defaults = rockchip_i2s_reg_defaults,
0644     .num_reg_defaults = ARRAY_SIZE(rockchip_i2s_reg_defaults),
0645     .writeable_reg = rockchip_i2s_wr_reg,
0646     .readable_reg = rockchip_i2s_rd_reg,
0647     .volatile_reg = rockchip_i2s_volatile_reg,
0648     .precious_reg = rockchip_i2s_precious_reg,
0649     .cache_type = REGCACHE_FLAT,
0650 };
0651 
0652 static const struct rk_i2s_pins rk3399_i2s_pins = {
0653     .reg_offset = 0xe220,
0654     .shift = 11,
0655 };
0656 
0657 static const struct of_device_id rockchip_i2s_match[] __maybe_unused = {
0658     { .compatible = "rockchip,px30-i2s", },
0659     { .compatible = "rockchip,rk1808-i2s", },
0660     { .compatible = "rockchip,rk3036-i2s", },
0661     { .compatible = "rockchip,rk3066-i2s", },
0662     { .compatible = "rockchip,rk3128-i2s", },
0663     { .compatible = "rockchip,rk3188-i2s", },
0664     { .compatible = "rockchip,rk3228-i2s", },
0665     { .compatible = "rockchip,rk3288-i2s", },
0666     { .compatible = "rockchip,rk3308-i2s", },
0667     { .compatible = "rockchip,rk3328-i2s", },
0668     { .compatible = "rockchip,rk3366-i2s", },
0669     { .compatible = "rockchip,rk3368-i2s", },
0670     { .compatible = "rockchip,rk3399-i2s", .data = &rk3399_i2s_pins },
0671     { .compatible = "rockchip,rv1126-i2s", },
0672     {},
0673 };
0674 
0675 static int rockchip_i2s_init_dai(struct rk_i2s_dev *i2s, struct resource *res,
0676                  struct snd_soc_dai_driver **dp)
0677 {
0678     struct device_node *node = i2s->dev->of_node;
0679     struct snd_soc_dai_driver *dai;
0680     struct property *dma_names;
0681     const char *dma_name;
0682     unsigned int val;
0683 
0684     of_property_for_each_string(node, "dma-names", dma_names, dma_name) {
0685         if (!strcmp(dma_name, "tx"))
0686             i2s->has_playback = true;
0687         if (!strcmp(dma_name, "rx"))
0688             i2s->has_capture = true;
0689     }
0690 
0691     dai = devm_kmemdup(i2s->dev, &rockchip_i2s_dai,
0692                sizeof(*dai), GFP_KERNEL);
0693     if (!dai)
0694         return -ENOMEM;
0695 
0696     if (i2s->has_playback) {
0697         dai->playback.stream_name = "Playback";
0698         dai->playback.channels_min = 2;
0699         dai->playback.channels_max = 8;
0700         dai->playback.rates = SNDRV_PCM_RATE_8000_192000;
0701         dai->playback.formats = SNDRV_PCM_FMTBIT_S8 |
0702                     SNDRV_PCM_FMTBIT_S16_LE |
0703                     SNDRV_PCM_FMTBIT_S20_3LE |
0704                     SNDRV_PCM_FMTBIT_S24_LE |
0705                     SNDRV_PCM_FMTBIT_S32_LE;
0706 
0707         i2s->playback_dma_data.addr = res->start + I2S_TXDR;
0708         i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
0709         i2s->playback_dma_data.maxburst = 8;
0710 
0711         if (!of_property_read_u32(node, "rockchip,playback-channels", &val)) {
0712             if (val >= 2 && val <= 8)
0713                 dai->playback.channels_max = val;
0714         }
0715     }
0716 
0717     if (i2s->has_capture) {
0718         dai->capture.stream_name = "Capture";
0719         dai->capture.channels_min = 2;
0720         dai->capture.channels_max = 8;
0721         dai->capture.rates = SNDRV_PCM_RATE_8000_192000;
0722         dai->capture.formats = SNDRV_PCM_FMTBIT_S8 |
0723                        SNDRV_PCM_FMTBIT_S16_LE |
0724                        SNDRV_PCM_FMTBIT_S20_3LE |
0725                        SNDRV_PCM_FMTBIT_S24_LE |
0726                        SNDRV_PCM_FMTBIT_S32_LE;
0727 
0728         i2s->capture_dma_data.addr = res->start + I2S_RXDR;
0729         i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
0730         i2s->capture_dma_data.maxburst = 8;
0731 
0732         if (!of_property_read_u32(node, "rockchip,capture-channels", &val)) {
0733             if (val >= 2 && val <= 8)
0734                 dai->capture.channels_max = val;
0735         }
0736     }
0737 
0738     if (dp)
0739         *dp = dai;
0740 
0741     return 0;
0742 }
0743 
0744 static int rockchip_i2s_probe(struct platform_device *pdev)
0745 {
0746     struct device_node *node = pdev->dev.of_node;
0747     const struct of_device_id *of_id;
0748     struct rk_i2s_dev *i2s;
0749     struct snd_soc_dai_driver *dai;
0750     struct resource *res;
0751     void __iomem *regs;
0752     int ret;
0753 
0754     i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
0755     if (!i2s)
0756         return -ENOMEM;
0757 
0758     spin_lock_init(&i2s->lock);
0759     i2s->dev = &pdev->dev;
0760 
0761     i2s->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf");
0762     if (!IS_ERR(i2s->grf)) {
0763         of_id = of_match_device(rockchip_i2s_match, &pdev->dev);
0764         if (!of_id || !of_id->data)
0765             return -EINVAL;
0766 
0767         i2s->pins = of_id->data;
0768     }
0769 
0770     /* try to prepare related clocks */
0771     i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk");
0772     if (IS_ERR(i2s->hclk)) {
0773         dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n");
0774         return PTR_ERR(i2s->hclk);
0775     }
0776     ret = clk_prepare_enable(i2s->hclk);
0777     if (ret) {
0778         dev_err(i2s->dev, "hclock enable failed %d\n", ret);
0779         return ret;
0780     }
0781 
0782     i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk");
0783     if (IS_ERR(i2s->mclk)) {
0784         dev_err(&pdev->dev, "Can't retrieve i2s master clock\n");
0785         ret = PTR_ERR(i2s->mclk);
0786         goto err_clk;
0787     }
0788 
0789     regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
0790     if (IS_ERR(regs)) {
0791         ret = PTR_ERR(regs);
0792         goto err_clk;
0793     }
0794 
0795     i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
0796                         &rockchip_i2s_regmap_config);
0797     if (IS_ERR(i2s->regmap)) {
0798         dev_err(&pdev->dev,
0799             "Failed to initialise managed register map\n");
0800         ret = PTR_ERR(i2s->regmap);
0801         goto err_clk;
0802     }
0803 
0804     i2s->bclk_ratio = 64;
0805     i2s->pinctrl = devm_pinctrl_get(&pdev->dev);
0806     if (!IS_ERR(i2s->pinctrl)) {
0807         i2s->bclk_on = pinctrl_lookup_state(i2s->pinctrl, "bclk_on");
0808         if (!IS_ERR_OR_NULL(i2s->bclk_on)) {
0809             i2s->bclk_off = pinctrl_lookup_state(i2s->pinctrl, "bclk_off");
0810             if (IS_ERR_OR_NULL(i2s->bclk_off)) {
0811                 dev_err(&pdev->dev, "failed to find i2s bclk_off\n");
0812                 ret = -EINVAL;
0813                 goto err_clk;
0814             }
0815         }
0816     } else {
0817         dev_dbg(&pdev->dev, "failed to find i2s pinctrl\n");
0818     }
0819 
0820     i2s_pinctrl_select_bclk_off(i2s);
0821 
0822     dev_set_drvdata(&pdev->dev, i2s);
0823 
0824     pm_runtime_enable(&pdev->dev);
0825     if (!pm_runtime_enabled(&pdev->dev)) {
0826         ret = i2s_runtime_resume(&pdev->dev);
0827         if (ret)
0828             goto err_pm_disable;
0829     }
0830 
0831     ret = rockchip_i2s_init_dai(i2s, res, &dai);
0832     if (ret)
0833         goto err_pm_disable;
0834 
0835     ret = devm_snd_soc_register_component(&pdev->dev,
0836                           &rockchip_i2s_component,
0837                           dai, 1);
0838 
0839     if (ret) {
0840         dev_err(&pdev->dev, "Could not register DAI\n");
0841         goto err_suspend;
0842     }
0843 
0844     ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
0845     if (ret) {
0846         dev_err(&pdev->dev, "Could not register PCM\n");
0847         goto err_suspend;
0848     }
0849 
0850     return 0;
0851 
0852 err_suspend:
0853     if (!pm_runtime_status_suspended(&pdev->dev))
0854         i2s_runtime_suspend(&pdev->dev);
0855 err_pm_disable:
0856     pm_runtime_disable(&pdev->dev);
0857 err_clk:
0858     clk_disable_unprepare(i2s->hclk);
0859     return ret;
0860 }
0861 
0862 static int rockchip_i2s_remove(struct platform_device *pdev)
0863 {
0864     struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev);
0865 
0866     pm_runtime_disable(&pdev->dev);
0867     if (!pm_runtime_status_suspended(&pdev->dev))
0868         i2s_runtime_suspend(&pdev->dev);
0869 
0870     clk_disable_unprepare(i2s->hclk);
0871 
0872     return 0;
0873 }
0874 
0875 static const struct dev_pm_ops rockchip_i2s_pm_ops = {
0876     SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume,
0877                NULL)
0878 };
0879 
0880 static struct platform_driver rockchip_i2s_driver = {
0881     .probe = rockchip_i2s_probe,
0882     .remove = rockchip_i2s_remove,
0883     .driver = {
0884         .name = DRV_NAME,
0885         .of_match_table = of_match_ptr(rockchip_i2s_match),
0886         .pm = &rockchip_i2s_pm_ops,
0887     },
0888 };
0889 module_platform_driver(rockchip_i2s_driver);
0890 
0891 MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface");
0892 MODULE_AUTHOR("jianqun <jay.xu@rock-chips.com>");
0893 MODULE_LICENSE("GPL v2");
0894 MODULE_ALIAS("platform:" DRV_NAME);
0895 MODULE_DEVICE_TABLE(of, rockchip_i2s_match);
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