qcom/qdsp6/q6prm.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002
0003 #ifndef __Q6PRM_H__
0004 #define __Q6PRM_H__
0005
0006 /* Clock ID for Primary I2S IBIT */
0007 #define Q6PRM_LPASS_CLK_ID_PRI_MI2S_IBIT                          0x100
0008 /* Clock ID for Primary I2S EBIT */
0009 #define Q6PRM_LPASS_CLK_ID_PRI_MI2S_EBIT                          0x101
0010 /* Clock ID for Secondary I2S IBIT */
0011 #define Q6PRM_LPASS_CLK_ID_SEC_MI2S_IBIT                          0x102
0012 /* Clock ID for Secondary I2S EBIT */
0013 #define Q6PRM_LPASS_CLK_ID_SEC_MI2S_EBIT                          0x103
0014 /* Clock ID for Tertiary I2S IBIT */
0015 #define Q6PRM_LPASS_CLK_ID_TER_MI2S_IBIT                          0x104
0016 /* Clock ID for Tertiary I2S EBIT */
0017 #define Q6PRM_LPASS_CLK_ID_TER_MI2S_EBIT                          0x105
0018 /* Clock ID for Quartnery I2S IBIT */
0019 #define Q6PRM_LPASS_CLK_ID_QUAD_MI2S_IBIT                         0x106
0020 /* Clock ID for Quartnery I2S EBIT */
0021 #define Q6PRM_LPASS_CLK_ID_QUAD_MI2S_EBIT                         0x107
0022 /* Clock ID for Speaker I2S IBIT */
0023 #define Q6PRM_LPASS_CLK_ID_SPEAKER_I2S_IBIT                       0x108
0024 /* Clock ID for Speaker I2S EBIT */
0025 #define Q6PRM_LPASS_CLK_ID_SPEAKER_I2S_EBIT                       0x109
0026 /* Clock ID for Speaker I2S OSR */
0027 #define Q6PRM_LPASS_CLK_ID_SPEAKER_I2S_OSR                        0x10A
0028
0029 /* Clock ID for QUINARY  I2S IBIT */
0030 #define Q6PRM_LPASS_CLK_ID_QUI_MI2S_IBIT            0x10B
0031 /* Clock ID for QUINARY  I2S EBIT */
0032 #define Q6PRM_LPASS_CLK_ID_QUI_MI2S_EBIT            0x10C
0033 /* Clock ID for SENARY  I2S IBIT */
0034 #define Q6PRM_LPASS_CLK_ID_SEN_MI2S_IBIT            0x10D
0035 /* Clock ID for SENARY  I2S EBIT */
0036 #define Q6PRM_LPASS_CLK_ID_SEN_MI2S_EBIT            0x10E
0037 /* Clock ID for INT0 I2S IBIT  */
0038 #define Q6PRM_LPASS_CLK_ID_INT0_MI2S_IBIT                       0x10F
0039 /* Clock ID for INT1 I2S IBIT  */
0040 #define Q6PRM_LPASS_CLK_ID_INT1_MI2S_IBIT                       0x110
0041 /* Clock ID for INT2 I2S IBIT  */
0042 #define Q6PRM_LPASS_CLK_ID_INT2_MI2S_IBIT                       0x111
0043 /* Clock ID for INT3 I2S IBIT  */
0044 #define Q6PRM_LPASS_CLK_ID_INT3_MI2S_IBIT                       0x112
0045 /* Clock ID for INT4 I2S IBIT  */
0046 #define Q6PRM_LPASS_CLK_ID_INT4_MI2S_IBIT                       0x113
0047 /* Clock ID for INT5 I2S IBIT  */
0048 #define Q6PRM_LPASS_CLK_ID_INT5_MI2S_IBIT                       0x114
0049 /* Clock ID for INT6 I2S IBIT  */
0050 #define Q6PRM_LPASS_CLK_ID_INT6_MI2S_IBIT                       0x115
0051
0052 /* Clock ID for QUINARY MI2S OSR CLK  */
0053 #define Q6PRM_LPASS_CLK_ID_QUI_MI2S_OSR                         0x116
0054
0055 #define Q6PRM_LPASS_CLK_ID_WSA_CORE_MCLK            0x305
0056 #define Q6PRM_LPASS_CLK_ID_WSA_CORE_NPL_MCLK            0x306
0057
0058 #define Q6PRM_LPASS_CLK_ID_VA_CORE_MCLK             0x307
0059 #define Q6PRM_LPASS_CLK_ID_VA_CORE_2X_MCLK          0x308
0060
0061 #define Q6PRM_LPASS_CLK_ID_TX_CORE_MCLK             0x30c
0062 #define Q6PRM_LPASS_CLK_ID_TX_CORE_NPL_MCLK         0x30d
0063
0064 #define Q6PRM_LPASS_CLK_ID_RX_CORE_MCLK             0x30e
0065 #define Q6PRM_LPASS_CLK_ID_RX_CORE_NPL_MCLK         0x30f
0066
0067 #define Q6PRM_LPASS_CLK_SRC_INTERNAL    1
0068 #define Q6PRM_LPASS_CLK_ROOT_DEFAULT    0
0069 #define Q6PRM_HW_CORE_ID_LPASS      1
0070 #define Q6PRM_HW_CORE_ID_DCODEC     2
0071
0072 int q6prm_set_lpass_clock(struct device *dev, int clk_id, int clk_attr,
0073               int clk_root, unsigned int freq);
0074 int q6prm_vote_lpass_core_hw(struct device *dev, uint32_t hw_block_id,
0075                  const char *client_name, uint32_t *client_handle);
0076 int q6prm_unvote_lpass_core_hw(struct device *dev, uint32_t hw_block_id,
0077                    uint32_t client_handle);
0078 #endif /* __Q6PRM_H__ */