soc/qcom/lpass.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (c) 2010-2011,2013-2015,2020 The Linux Foundation. All rights reserved.
0004  *
0005  * lpass.h - Definitions for the QTi LPASS
0006  */
0007
0008 #ifndef __LPASS_H__
0009 #define __LPASS_H__
0010
0011 #include <linux/clk.h>
0012 #include <linux/compiler.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/regmap.h>
0015 #include <dt-bindings/sound/qcom,lpass.h>
0016 #include "lpass-hdmi.h"
0017
0018 #define LPASS_AHBIX_CLOCK_FREQUENCY     131072000
0019 #define LPASS_MAX_PORTS         (LPASS_CDC_DMA_VA_TX8 + 1)
0020 #define LPASS_MAX_MI2S_PORTS            (8)
0021 #define LPASS_MAX_DMA_CHANNELS          (8)
0022 #define LPASS_MAX_HDMI_DMA_CHANNELS     (4)
0023 #define LPASS_MAX_CDC_DMA_CHANNELS      (8)
0024 #define LPASS_MAX_VA_CDC_DMA_CHANNELS       (8)
0025 #define LPASS_CDC_DMA_INTF_ONE_CHANNEL      (0x01)
0026 #define LPASS_CDC_DMA_INTF_TWO_CHANNEL      (0x03)
0027 #define LPASS_CDC_DMA_INTF_FOUR_CHANNEL     (0x0F)
0028 #define LPASS_CDC_DMA_INTF_SIX_CHANNEL      (0x3F)
0029 #define LPASS_CDC_DMA_INTF_EIGHT_CHANNEL    (0xFF)
0030
0031 #define LPASS_ACTIVE_PDS            (4)
0032 #define LPASS_PROXY_PDS         (8)
0033
0034 #define QCOM_REGMAP_FIELD_ALLOC(d, m, f, mf)    \
0035     do { \
0036         mf = devm_regmap_field_alloc(d, m, f);     \
0037         if (IS_ERR(mf))                \
0038             return -EINVAL;         \
0039     } while (0)
0040
0041 static inline bool is_cdc_dma_port(int dai_id)
0042 {
0043     switch (dai_id) {
0044     case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9:
0045     case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8:
0046     case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX8:
0047         return true;
0048     }
0049     return false;
0050 }
0051
0052 static inline bool is_rxtx_cdc_dma_port(int dai_id)
0053 {
0054     switch (dai_id) {
0055     case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9:
0056     case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8:
0057         return true;
0058     }
0059     return false;
0060 }
0061
0062 struct lpaif_i2sctl {
0063     struct regmap_field *loopback;
0064     struct regmap_field *spken;
0065     struct regmap_field *spkmode;
0066     struct regmap_field *spkmono;
0067     struct regmap_field *micen;
0068     struct regmap_field *micmode;
0069     struct regmap_field *micmono;
0070     struct regmap_field *wssrc;
0071     struct regmap_field *bitwidth;
0072 };
0073
0074
0075 struct lpaif_dmactl {
0076     struct regmap_field *intf;
0077     struct regmap_field *bursten;
0078     struct regmap_field *wpscnt;
0079     struct regmap_field *fifowm;
0080     struct regmap_field *enable;
0081     struct regmap_field *dyncclk;
0082     struct regmap_field *burst8;
0083     struct regmap_field *burst16;
0084     struct regmap_field *dynburst;
0085     struct regmap_field *codec_enable;
0086     struct regmap_field *codec_pack;
0087     struct regmap_field *codec_intf;
0088     struct regmap_field *codec_fs_sel;
0089     struct regmap_field *codec_channel;
0090     struct regmap_field *codec_fs_delay;
0091 };
0092
0093 /* Both the CPU DAI and platform drivers will access this data */
0094 struct lpass_data {
0095
0096     /* AHB-I/X bus clocks inside the low-power audio subsystem (LPASS) */
0097     struct clk *ahbix_clk;
0098
0099     /* MI2S system clock */
0100     struct clk *mi2s_osr_clk[LPASS_MAX_MI2S_PORTS];
0101
0102     /* MI2S bit clock (derived from system clock by a divider */
0103     struct clk *mi2s_bit_clk[LPASS_MAX_MI2S_PORTS];
0104
0105     struct clk *codec_mem0;
0106     struct clk *codec_mem1;
0107     struct clk *codec_mem2;
0108     struct clk *va_mem0;
0109
0110     /* MI2S SD lines to use for playback/capture */
0111     unsigned int mi2s_playback_sd_mode[LPASS_MAX_MI2S_PORTS];
0112     unsigned int mi2s_capture_sd_mode[LPASS_MAX_MI2S_PORTS];
0113
0114     /* The state of MI2S prepare dai_ops was called */
0115     bool mi2s_was_prepared[LPASS_MAX_MI2S_PORTS];
0116
0117     int hdmi_port_enable;
0118     int codec_dma_enable;
0119
0120     /* low-power audio interface (LPAIF) registers */
0121     void __iomem *lpaif;
0122     void __iomem *hdmiif;
0123     void __iomem *rxtx_lpaif;
0124     void __iomem *va_lpaif;
0125
0126     u32 rxtx_cdc_dma_lpm_buf;
0127     u32 va_cdc_dma_lpm_buf;
0128
0129     /* regmap backed by the low-power audio interface (LPAIF) registers */
0130     struct regmap *lpaif_map;
0131     struct regmap *hdmiif_map;
0132     struct regmap *rxtx_lpaif_map;
0133     struct regmap *va_lpaif_map;
0134
0135     /* interrupts from the low-power audio interface (LPAIF) */
0136     int lpaif_irq;
0137     int hdmiif_irq;
0138     int rxtxif_irq;
0139     int vaif_irq;
0140
0141     /* SOC specific variations in the LPASS IP integration */
0142     struct lpass_variant *variant;
0143
0144     /* bit map to keep track of static channel allocations */
0145     unsigned long dma_ch_bit_map;
0146     unsigned long hdmi_dma_ch_bit_map;
0147     unsigned long rxtx_dma_ch_bit_map;
0148     unsigned long va_dma_ch_bit_map;
0149
0150     /* used it for handling interrupt per dma channel */
0151     struct snd_pcm_substream *substream[LPASS_MAX_DMA_CHANNELS];
0152     struct snd_pcm_substream *hdmi_substream[LPASS_MAX_HDMI_DMA_CHANNELS];
0153     struct snd_pcm_substream *rxtx_substream[LPASS_MAX_CDC_DMA_CHANNELS];
0154     struct snd_pcm_substream *va_substream[LPASS_MAX_CDC_DMA_CHANNELS];
0155
0156     /* SOC specific clock list */
0157     struct clk_bulk_data *clks;
0158     int num_clks;
0159
0160     /* Regmap fields of I2SCTL & DMACTL registers bitfields */
0161     struct lpaif_i2sctl *i2sctl;
0162     struct lpaif_dmactl *rd_dmactl;
0163     struct lpaif_dmactl *wr_dmactl;
0164     struct lpaif_dmactl *hdmi_rd_dmactl;
0165
0166     /* Regmap fields of CODEC DMA CTRL registers */
0167     struct lpaif_dmactl *rxtx_rd_dmactl;
0168     struct lpaif_dmactl *rxtx_wr_dmactl;
0169     struct lpaif_dmactl *va_wr_dmactl;
0170
0171     /* Regmap fields of HDMI_CTRL registers*/
0172     struct regmap_field *hdmitx_legacy_en;
0173     struct regmap_field *hdmitx_parity_calc_en;
0174     struct regmap_field *hdmitx_ch_msb[LPASS_MAX_HDMI_DMA_CHANNELS];
0175     struct regmap_field *hdmitx_ch_lsb[LPASS_MAX_HDMI_DMA_CHANNELS];
0176     struct lpass_hdmi_tx_ctl *tx_ctl;
0177     struct lpass_vbit_ctrl *vbit_ctl;
0178     struct lpass_hdmitx_dmactl *hdmi_tx_dmactl[LPASS_MAX_HDMI_DMA_CHANNELS];
0179     struct lpass_dp_metadata_ctl *meta_ctl;
0180     struct lpass_sstream_ctl *sstream_ctl;
0181 };
0182
0183 /* Vairant data per each SOC */
0184 struct lpass_variant {
0185     u32 irq_reg_base;
0186     u32 irq_reg_stride;
0187     u32 irq_ports;
0188     u32 rdma_reg_base;
0189     u32 rdma_reg_stride;
0190     u32 rdma_channels;
0191     u32 hdmi_rdma_reg_base;
0192     u32 hdmi_rdma_reg_stride;
0193     u32 hdmi_rdma_channels;
0194     u32 wrdma_reg_base;
0195     u32 wrdma_reg_stride;
0196     u32 wrdma_channels;
0197     u32 rxtx_irq_reg_base;
0198     u32 rxtx_irq_reg_stride;
0199     u32 rxtx_irq_ports;
0200     u32 rxtx_rdma_reg_base;
0201     u32 rxtx_rdma_reg_stride;
0202     u32 rxtx_rdma_channels;
0203     u32 rxtx_wrdma_reg_base;
0204     u32 rxtx_wrdma_reg_stride;
0205     u32 rxtx_wrdma_channels;
0206     u32 va_irq_reg_base;
0207     u32 va_irq_reg_stride;
0208     u32 va_irq_ports;
0209     u32 va_rdma_reg_base;
0210     u32 va_rdma_reg_stride;
0211     u32 va_rdma_channels;
0212     u32 va_wrdma_reg_base;
0213     u32 va_wrdma_reg_stride;
0214     u32 va_wrdma_channels;
0215     u32 i2sctrl_reg_base;
0216     u32 i2sctrl_reg_stride;
0217     u32 i2s_ports;
0218
0219     /* I2SCTL Register fields */
0220     struct reg_field loopback;
0221     struct reg_field spken;
0222     struct reg_field spkmode;
0223     struct reg_field spkmono;
0224     struct reg_field micen;
0225     struct reg_field micmode;
0226     struct reg_field micmono;
0227     struct reg_field wssrc;
0228     struct reg_field bitwidth;
0229
0230     u32 hdmi_irq_reg_base;
0231     u32 hdmi_irq_reg_stride;
0232     u32 hdmi_irq_ports;
0233
0234     /* HDMI specific controls */
0235     u32 hdmi_tx_ctl_addr;
0236     u32 hdmi_legacy_addr;
0237     u32 hdmi_vbit_addr;
0238     u32 hdmi_ch_lsb_addr;
0239     u32 hdmi_ch_msb_addr;
0240     u32 ch_stride;
0241     u32 hdmi_parity_addr;
0242     u32 hdmi_dmactl_addr;
0243     u32 hdmi_dma_stride;
0244     u32 hdmi_DP_addr;
0245     u32 hdmi_sstream_addr;
0246
0247     /* HDMI SSTREAM CTRL fields  */
0248     struct reg_field sstream_en;
0249     struct reg_field dma_sel;
0250     struct reg_field auto_bbit_en;
0251     struct reg_field layout;
0252     struct reg_field layout_sp;
0253     struct reg_field set_sp_on_en;
0254     struct reg_field dp_audio;
0255     struct reg_field dp_staffing_en;
0256     struct reg_field dp_sp_b_hw_en;
0257
0258     /* HDMI DP METADATA CTL fields */
0259     struct reg_field mute;
0260     struct reg_field as_sdp_cc;
0261     struct reg_field as_sdp_ct;
0262     struct reg_field aif_db4;
0263     struct reg_field frequency;
0264     struct reg_field mst_index;
0265     struct reg_field dptx_index;
0266
0267     /* HDMI TX CTRL fields */
0268     struct reg_field soft_reset;
0269     struct reg_field force_reset;
0270
0271     /* HDMI TX DMA CTRL */
0272     struct reg_field use_hw_chs;
0273     struct reg_field use_hw_usr;
0274     struct reg_field hw_chs_sel;
0275     struct reg_field hw_usr_sel;
0276
0277     /* HDMI VBIT CTRL */
0278     struct reg_field replace_vbit;
0279     struct reg_field vbit_stream;
0280
0281     /* HDMI TX LEGACY */
0282     struct reg_field legacy_en;
0283
0284     /* HDMI TX PARITY */
0285     struct reg_field calc_en;
0286
0287     /* HDMI CH LSB */
0288     struct reg_field lsb_bits;
0289
0290     /* HDMI CH MSB */
0291     struct reg_field msb_bits;
0292
0293     struct reg_field hdmi_rdma_bursten;
0294     struct reg_field hdmi_rdma_wpscnt;
0295     struct reg_field hdmi_rdma_fifowm;
0296     struct reg_field hdmi_rdma_enable;
0297     struct reg_field hdmi_rdma_dyncclk;
0298     struct reg_field hdmi_rdma_burst8;
0299     struct reg_field hdmi_rdma_burst16;
0300     struct reg_field hdmi_rdma_dynburst;
0301
0302     /* RD_DMA Register fields */
0303     struct reg_field rdma_intf;
0304     struct reg_field rdma_bursten;
0305     struct reg_field rdma_wpscnt;
0306     struct reg_field rdma_fifowm;
0307     struct reg_field rdma_enable;
0308     struct reg_field rdma_dyncclk;
0309
0310     /* WR_DMA Register fields */
0311     struct reg_field wrdma_intf;
0312     struct reg_field wrdma_bursten;
0313     struct reg_field wrdma_wpscnt;
0314     struct reg_field wrdma_fifowm;
0315     struct reg_field wrdma_enable;
0316     struct reg_field wrdma_dyncclk;
0317
0318     /* CDC RXTX RD_DMA */
0319     struct reg_field rxtx_rdma_intf;
0320     struct reg_field rxtx_rdma_bursten;
0321     struct reg_field rxtx_rdma_wpscnt;
0322     struct reg_field rxtx_rdma_fifowm;
0323     struct reg_field rxtx_rdma_enable;
0324     struct reg_field rxtx_rdma_dyncclk;
0325     struct reg_field rxtx_rdma_burst8;
0326     struct reg_field rxtx_rdma_burst16;
0327     struct reg_field rxtx_rdma_dynburst;
0328     struct reg_field rxtx_rdma_codec_enable;
0329     struct reg_field rxtx_rdma_codec_pack;
0330     struct reg_field rxtx_rdma_codec_intf;
0331     struct reg_field rxtx_rdma_codec_fs_sel;
0332     struct reg_field rxtx_rdma_codec_ch;
0333     struct reg_field rxtx_rdma_codec_fs_delay;
0334
0335     /* CDC RXTX WR_DMA */
0336     struct reg_field rxtx_wrdma_intf;
0337     struct reg_field rxtx_wrdma_bursten;
0338     struct reg_field rxtx_wrdma_wpscnt;
0339     struct reg_field rxtx_wrdma_fifowm;
0340     struct reg_field rxtx_wrdma_enable;
0341     struct reg_field rxtx_wrdma_dyncclk;
0342     struct reg_field rxtx_wrdma_burst8;
0343     struct reg_field rxtx_wrdma_burst16;
0344     struct reg_field rxtx_wrdma_dynburst;
0345     struct reg_field rxtx_wrdma_codec_enable;
0346     struct reg_field rxtx_wrdma_codec_pack;
0347     struct reg_field rxtx_wrdma_codec_intf;
0348     struct reg_field rxtx_wrdma_codec_fs_sel;
0349     struct reg_field rxtx_wrdma_codec_ch;
0350     struct reg_field rxtx_wrdma_codec_fs_delay;
0351
0352     /* CDC VA WR_DMA */
0353     struct reg_field va_wrdma_intf;
0354     struct reg_field va_wrdma_bursten;
0355     struct reg_field va_wrdma_wpscnt;
0356     struct reg_field va_wrdma_fifowm;
0357     struct reg_field va_wrdma_enable;
0358     struct reg_field va_wrdma_dyncclk;
0359     struct reg_field va_wrdma_burst8;
0360     struct reg_field va_wrdma_burst16;
0361     struct reg_field va_wrdma_dynburst;
0362     struct reg_field va_wrdma_codec_enable;
0363     struct reg_field va_wrdma_codec_pack;
0364     struct reg_field va_wrdma_codec_intf;
0365     struct reg_field va_wrdma_codec_fs_sel;
0366     struct reg_field va_wrdma_codec_ch;
0367     struct reg_field va_wrdma_codec_fs_delay;
0368
0369     /**
0370      * on SOCs like APQ8016 the channel control bits start
0371      * at different offset to ipq806x
0372      **/
0373     u32 dmactl_audif_start;
0374     u32 wrdma_channel_start;
0375     u32 rxtx_wrdma_channel_start;
0376     u32 va_wrdma_channel_start;
0377
0378     /* SOC specific initialization like clocks */
0379     int (*init)(struct platform_device *pdev);
0380     int (*exit)(struct platform_device *pdev);
0381     int (*alloc_dma_channel)(struct lpass_data *data, int direction, unsigned int dai_id);
0382     int (*free_dma_channel)(struct lpass_data *data, int ch, unsigned int dai_id);
0383
0384     /* SOC specific dais */
0385     struct snd_soc_dai_driver *dai_driver;
0386     int num_dai;
0387     const char * const *dai_osr_clk_names;
0388     const char * const *dai_bit_clk_names;
0389
0390     /* SOC specific clocks configuration */
0391     const char **clk_name;
0392     int num_clks;
0393 };
0394
0395 struct lpass_pcm_data {
0396     int dma_ch;
0397     int i2s_port;
0398 };
0399
0400 /* register the platform driver from the CPU DAI driver */
0401 int asoc_qcom_lpass_platform_register(struct platform_device *);
0402 int asoc_qcom_lpass_cpu_platform_remove(struct platform_device *pdev);
0403 void asoc_qcom_lpass_cpu_platform_shutdown(struct platform_device *pdev);
0404 int asoc_qcom_lpass_cpu_platform_probe(struct platform_device *pdev);
0405 int asoc_qcom_lpass_cpu_dai_probe(struct snd_soc_dai *dai);
0406 extern const struct snd_soc_dai_ops asoc_qcom_lpass_cpu_dai_ops;
0407 int lpass_cpu_pcm_new(struct snd_soc_pcm_runtime *rtd,
0408                 struct snd_soc_dai *dai);
0409 extern const struct snd_soc_dai_ops asoc_qcom_lpass_cdc_dma_dai_ops;
0410
0411 #endif /* __LPASS_H__ */