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0008 #include <linux/module.h>
0009 #include <sound/pcm.h>
0010 #include <sound/soc.h>
0011 #include <linux/pm_runtime.h>
0012
0013 #include <dt-bindings/sound/sc7180-lpass.h>
0014
0015 #include "lpass-lpaif-reg.h"
0016 #include "lpass.h"
0017
0018 static struct snd_soc_dai_driver sc7280_lpass_cpu_dai_driver[] = {
0019 {
0020 .id = MI2S_PRIMARY,
0021 .name = "Primary MI2S",
0022 .playback = {
0023 .stream_name = "Primary Playback",
0024 .formats = SNDRV_PCM_FMTBIT_S16,
0025 .rates = SNDRV_PCM_RATE_48000,
0026 .rate_min = 48000,
0027 .rate_max = 48000,
0028 .channels_min = 2,
0029 .channels_max = 2,
0030 },
0031 .capture = {
0032 .stream_name = "Primary Capture",
0033 .formats = SNDRV_PCM_FMTBIT_S16 |
0034 SNDRV_PCM_FMTBIT_S32,
0035 .rates = SNDRV_PCM_RATE_48000,
0036 .rate_min = 48000,
0037 .rate_max = 48000,
0038 .channels_min = 2,
0039 .channels_max = 2,
0040 },
0041 .probe = &asoc_qcom_lpass_cpu_dai_probe,
0042 .ops = &asoc_qcom_lpass_cpu_dai_ops,
0043 }, {
0044 .id = MI2S_SECONDARY,
0045 .name = "Secondary MI2S",
0046 .playback = {
0047 .stream_name = "Secondary MI2S Playback",
0048 .formats = SNDRV_PCM_FMTBIT_S16,
0049 .rates = SNDRV_PCM_RATE_48000,
0050 .rate_min = 48000,
0051 .rate_max = 48000,
0052 .channels_min = 2,
0053 .channels_max = 2,
0054 },
0055 .probe = &asoc_qcom_lpass_cpu_dai_probe,
0056 .ops = &asoc_qcom_lpass_cpu_dai_ops,
0057 }, {
0058 .id = LPASS_DP_RX,
0059 .name = "Hdmi",
0060 .playback = {
0061 .stream_name = "DP Playback",
0062 .formats = SNDRV_PCM_FMTBIT_S24,
0063 .rates = SNDRV_PCM_RATE_48000,
0064 .rate_min = 48000,
0065 .rate_max = 48000,
0066 .channels_min = 2,
0067 .channels_max = 2,
0068 },
0069 .ops = &asoc_qcom_lpass_hdmi_dai_ops,
0070 }, {
0071 .id = LPASS_CDC_DMA_RX0,
0072 .name = "CDC DMA RX",
0073 .playback = {
0074 .stream_name = "WCD Playback",
0075 .formats = SNDRV_PCM_FMTBIT_S16,
0076 .rates = SNDRV_PCM_RATE_48000,
0077 .rate_min = 48000,
0078 .rate_max = 48000,
0079 .channels_min = 2,
0080 .channels_max = 2,
0081 },
0082 .ops = &asoc_qcom_lpass_cdc_dma_dai_ops,
0083 }, {
0084 .id = LPASS_CDC_DMA_TX3,
0085 .name = "CDC DMA TX",
0086 .capture = {
0087 .stream_name = "WCD Capture",
0088 .formats = SNDRV_PCM_FMTBIT_S16,
0089 .rates = SNDRV_PCM_RATE_48000,
0090 .rate_min = 48000,
0091 .rate_max = 48000,
0092 .channels_min = 1,
0093 .channels_max = 1,
0094 },
0095 .ops = &asoc_qcom_lpass_cdc_dma_dai_ops,
0096 }, {
0097 .id = LPASS_CDC_DMA_VA_TX0,
0098 .name = "CDC DMA VA",
0099 .capture = {
0100 .stream_name = "DMIC Capture",
0101 .formats = SNDRV_PCM_FMTBIT_S16,
0102 .rates = SNDRV_PCM_RATE_48000,
0103 .rate_min = 48000,
0104 .rate_max = 48000,
0105 .channels_min = 2,
0106 .channels_max = 4,
0107 },
0108 .ops = &asoc_qcom_lpass_cdc_dma_dai_ops,
0109 },
0110 };
0111
0112 static int sc7280_lpass_alloc_dma_channel(struct lpass_data *drvdata,
0113 int direction, unsigned int dai_id)
0114 {
0115 struct lpass_variant *v = drvdata->variant;
0116 int chan = 0;
0117
0118 switch (dai_id) {
0119 case MI2S_PRIMARY ... MI2S_QUINARY:
0120 if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
0121 chan = find_first_zero_bit(&drvdata->dma_ch_bit_map,
0122 v->rdma_channels);
0123
0124 if (chan >= v->rdma_channels)
0125 return -EBUSY;
0126 } else {
0127 chan = find_next_zero_bit(&drvdata->dma_ch_bit_map,
0128 v->wrdma_channel_start +
0129 v->wrdma_channels,
0130 v->wrdma_channel_start);
0131
0132 if (chan >= v->wrdma_channel_start + v->wrdma_channels)
0133 return -EBUSY;
0134 }
0135 set_bit(chan, &drvdata->dma_ch_bit_map);
0136 break;
0137 case LPASS_DP_RX:
0138 chan = find_first_zero_bit(&drvdata->hdmi_dma_ch_bit_map,
0139 v->hdmi_rdma_channels);
0140 if (chan >= v->hdmi_rdma_channels)
0141 return -EBUSY;
0142 set_bit(chan, &drvdata->hdmi_dma_ch_bit_map);
0143 break;
0144 case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9:
0145 chan = find_first_zero_bit(&drvdata->rxtx_dma_ch_bit_map,
0146 v->rxtx_rdma_channels);
0147 if (chan >= v->rxtx_rdma_channels)
0148 return -EBUSY;
0149 break;
0150 case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8:
0151 chan = find_next_zero_bit(&drvdata->rxtx_dma_ch_bit_map,
0152 v->rxtx_wrdma_channel_start +
0153 v->rxtx_wrdma_channels,
0154 v->rxtx_wrdma_channel_start);
0155 if (chan >= v->rxtx_wrdma_channel_start + v->rxtx_wrdma_channels)
0156 return -EBUSY;
0157 set_bit(chan, &drvdata->rxtx_dma_ch_bit_map);
0158 break;
0159 case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX8:
0160 chan = find_next_zero_bit(&drvdata->va_dma_ch_bit_map,
0161 v->va_wrdma_channel_start +
0162 v->va_wrdma_channels,
0163 v->va_wrdma_channel_start);
0164 if (chan >= v->va_wrdma_channel_start + v->va_wrdma_channels)
0165 return -EBUSY;
0166 set_bit(chan, &drvdata->va_dma_ch_bit_map);
0167 break;
0168 default:
0169 break;
0170 }
0171
0172 return chan;
0173 }
0174
0175 static int sc7280_lpass_free_dma_channel(struct lpass_data *drvdata, int chan, unsigned int dai_id)
0176 {
0177 switch (dai_id) {
0178 case MI2S_PRIMARY ... MI2S_QUINARY:
0179 clear_bit(chan, &drvdata->dma_ch_bit_map);
0180 break;
0181 case LPASS_DP_RX:
0182 clear_bit(chan, &drvdata->hdmi_dma_ch_bit_map);
0183 break;
0184 case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9:
0185 case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8:
0186 clear_bit(chan, &drvdata->rxtx_dma_ch_bit_map);
0187 break;
0188 case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX8:
0189 clear_bit(chan, &drvdata->va_dma_ch_bit_map);
0190 break;
0191 default:
0192 break;
0193 }
0194
0195 return 0;
0196 }
0197
0198 static int sc7280_lpass_init(struct platform_device *pdev)
0199 {
0200 struct lpass_data *drvdata = platform_get_drvdata(pdev);
0201 struct lpass_variant *variant = drvdata->variant;
0202 struct device *dev = &pdev->dev;
0203 int ret, i;
0204
0205 drvdata->clks = devm_kcalloc(dev, variant->num_clks,
0206 sizeof(*drvdata->clks), GFP_KERNEL);
0207 if (!drvdata->clks)
0208 return -ENOMEM;
0209
0210 drvdata->num_clks = variant->num_clks;
0211
0212 for (i = 0; i < drvdata->num_clks; i++)
0213 drvdata->clks[i].id = variant->clk_name[i];
0214
0215 ret = devm_clk_bulk_get(dev, drvdata->num_clks, drvdata->clks);
0216 if (ret) {
0217 dev_err(dev, "Failed to get clocks %d\n", ret);
0218 return ret;
0219 }
0220
0221 ret = clk_bulk_prepare_enable(drvdata->num_clks, drvdata->clks);
0222 if (ret) {
0223 dev_err(dev, "sc7280 clk_enable failed\n");
0224 return ret;
0225 }
0226
0227 return 0;
0228 }
0229
0230 static int sc7280_lpass_exit(struct platform_device *pdev)
0231 {
0232 struct lpass_data *drvdata = platform_get_drvdata(pdev);
0233
0234 clk_bulk_disable_unprepare(drvdata->num_clks, drvdata->clks);
0235
0236 return 0;
0237 }
0238
0239 static struct lpass_variant sc7280_data = {
0240 .i2sctrl_reg_base = 0x1000,
0241 .i2sctrl_reg_stride = 0x1000,
0242 .i2s_ports = 3,
0243 .irq_reg_base = 0x9000,
0244 .irq_reg_stride = 0x1000,
0245 .irq_ports = 3,
0246 .rdma_reg_base = 0xC000,
0247 .rdma_reg_stride = 0x1000,
0248 .rdma_channels = 5,
0249 .rxtx_rdma_reg_base = 0xC000,
0250 .rxtx_rdma_reg_stride = 0x1000,
0251 .rxtx_rdma_channels = 8,
0252 .hdmi_rdma_reg_base = 0x64000,
0253 .hdmi_rdma_reg_stride = 0x1000,
0254 .hdmi_rdma_channels = 4,
0255 .dmactl_audif_start = 1,
0256 .wrdma_reg_base = 0x18000,
0257 .wrdma_reg_stride = 0x1000,
0258 .wrdma_channel_start = 5,
0259 .wrdma_channels = 4,
0260 .rxtx_irq_reg_base = 0x9000,
0261 .rxtx_irq_reg_stride = 0x1000,
0262 .rxtx_irq_ports = 3,
0263 .rxtx_wrdma_reg_base = 0x18000,
0264 .rxtx_wrdma_reg_stride = 0x1000,
0265 .rxtx_wrdma_channel_start = 5,
0266 .rxtx_wrdma_channels = 6,
0267 .va_wrdma_reg_base = 0x18000,
0268 .va_wrdma_reg_stride = 0x1000,
0269 .va_wrdma_channel_start = 5,
0270 .va_wrdma_channels = 3,
0271 .va_irq_reg_base = 0x9000,
0272 .va_irq_reg_stride = 0x1000,
0273 .va_irq_ports = 3,
0274
0275 .loopback = REG_FIELD_ID(0x1000, 17, 17, 3, 0x1000),
0276 .spken = REG_FIELD_ID(0x1000, 16, 16, 3, 0x1000),
0277 .spkmode = REG_FIELD_ID(0x1000, 11, 15, 3, 0x1000),
0278 .spkmono = REG_FIELD_ID(0x1000, 10, 10, 3, 0x1000),
0279 .micen = REG_FIELD_ID(0x1000, 9, 9, 3, 0x1000),
0280 .micmode = REG_FIELD_ID(0x1000, 4, 8, 3, 0x1000),
0281 .micmono = REG_FIELD_ID(0x1000, 3, 3, 3, 0x1000),
0282 .wssrc = REG_FIELD_ID(0x1000, 2, 2, 3, 0x1000),
0283 .bitwidth = REG_FIELD_ID(0x1000, 0, 1, 3, 0x1000),
0284
0285 .rdma_dyncclk = REG_FIELD_ID(0xC000, 21, 21, 5, 0x1000),
0286 .rdma_bursten = REG_FIELD_ID(0xC000, 20, 20, 5, 0x1000),
0287 .rdma_wpscnt = REG_FIELD_ID(0xC000, 16, 19, 5, 0x1000),
0288 .rdma_intf = REG_FIELD_ID(0xC000, 12, 15, 5, 0x1000),
0289 .rdma_fifowm = REG_FIELD_ID(0xC000, 1, 5, 5, 0x1000),
0290 .rdma_enable = REG_FIELD_ID(0xC000, 0, 0, 5, 0x1000),
0291
0292 .wrdma_dyncclk = REG_FIELD_ID(0x18000, 22, 22, 4, 0x1000),
0293 .wrdma_bursten = REG_FIELD_ID(0x18000, 21, 21, 4, 0x1000),
0294 .wrdma_wpscnt = REG_FIELD_ID(0x18000, 17, 20, 4, 0x1000),
0295 .wrdma_intf = REG_FIELD_ID(0x18000, 12, 16, 4, 0x1000),
0296 .wrdma_fifowm = REG_FIELD_ID(0x18000, 1, 5, 4, 0x1000),
0297 .wrdma_enable = REG_FIELD_ID(0x18000, 0, 0, 4, 0x1000),
0298
0299 .rxtx_rdma_enable = REG_FIELD_ID(0xC000, 0, 0, 7, 0x1000),
0300 .rxtx_rdma_fifowm = REG_FIELD_ID(0xC000, 1, 11, 7, 0x1000),
0301 .rxtx_rdma_intf = REG_FIELD_ID(0xC000, 12, 15, 7, 0x1000),
0302 .rxtx_rdma_wpscnt = REG_FIELD_ID(0xC000, 16, 19, 7, 0x1000),
0303 .rxtx_rdma_bursten = REG_FIELD_ID(0xC000, 20, 20, 7, 0x1000),
0304 .rxtx_rdma_dyncclk = REG_FIELD_ID(0xC000, 21, 21, 7, 0x1000),
0305
0306 .rxtx_rdma_codec_ch = REG_FIELD_ID(0xC050, 0, 7, 7, 0x1000),
0307 .rxtx_rdma_codec_intf = REG_FIELD_ID(0xC050, 16, 19, 7, 0x1000),
0308 .rxtx_rdma_codec_fs_delay = REG_FIELD_ID(0xC050, 21, 24, 7, 0x1000),
0309 .rxtx_rdma_codec_fs_sel = REG_FIELD_ID(0xC050, 25, 27, 7, 0x1000),
0310 .rxtx_rdma_codec_pack = REG_FIELD_ID(0xC050, 29, 29, 5, 0x1000),
0311 .rxtx_rdma_codec_enable = REG_FIELD_ID(0xC050, 30, 30, 7, 0x1000),
0312
0313 .rxtx_wrdma_enable = REG_FIELD_ID(0x18000, 0, 0, 5, 0x1000),
0314 .rxtx_wrdma_fifowm = REG_FIELD_ID(0x18000, 1, 11, 5, 0x1000),
0315 .rxtx_wrdma_intf = REG_FIELD_ID(0x18000, 12, 16, 5, 0x1000),
0316 .rxtx_wrdma_wpscnt = REG_FIELD_ID(0x18000, 17, 20, 5, 0x1000),
0317 .rxtx_wrdma_bursten = REG_FIELD_ID(0x18000, 21, 21, 5, 0x1000),
0318 .rxtx_wrdma_dyncclk = REG_FIELD_ID(0x18000, 22, 22, 5, 0x1000),
0319
0320 .rxtx_wrdma_codec_ch = REG_FIELD_ID(0x18050, 0, 7, 5, 0x1000),
0321 .rxtx_wrdma_codec_intf = REG_FIELD_ID(0x18050, 16, 19, 5, 0x1000),
0322 .rxtx_wrdma_codec_fs_delay = REG_FIELD_ID(0x18050, 21, 24, 5, 0x1000),
0323 .rxtx_wrdma_codec_fs_sel = REG_FIELD_ID(0x18050, 25, 27, 5, 0x1000),
0324 .rxtx_wrdma_codec_pack = REG_FIELD_ID(0x18050, 29, 29, 5, 0x1000),
0325 .rxtx_wrdma_codec_enable = REG_FIELD_ID(0x18050, 30, 30, 5, 0x1000),
0326
0327 .va_wrdma_enable = REG_FIELD_ID(0x18000, 0, 0, 5, 0x1000),
0328 .va_wrdma_fifowm = REG_FIELD_ID(0x18000, 1, 11, 5, 0x1000),
0329 .va_wrdma_intf = REG_FIELD_ID(0x18000, 12, 16, 5, 0x1000),
0330 .va_wrdma_wpscnt = REG_FIELD_ID(0x18000, 17, 20, 5, 0x1000),
0331 .va_wrdma_bursten = REG_FIELD_ID(0x18000, 21, 21, 5, 0x1000),
0332 .va_wrdma_dyncclk = REG_FIELD_ID(0x18000, 22, 22, 5, 0x1000),
0333
0334 .va_wrdma_codec_ch = REG_FIELD_ID(0x18050, 0, 7, 5, 0x1000),
0335 .va_wrdma_codec_intf = REG_FIELD_ID(0x18050, 16, 19, 5, 0x1000),
0336 .va_wrdma_codec_fs_delay = REG_FIELD_ID(0x18050, 21, 24, 5, 0x1000),
0337 .va_wrdma_codec_fs_sel = REG_FIELD_ID(0x18050, 25, 27, 5, 0x1000),
0338 .va_wrdma_codec_pack = REG_FIELD_ID(0x18050, 29, 29, 5, 0x1000),
0339 .va_wrdma_codec_enable = REG_FIELD_ID(0x18050, 30, 30, 5, 0x1000),
0340
0341 .hdmi_tx_ctl_addr = 0x1000,
0342 .hdmi_legacy_addr = 0x1008,
0343 .hdmi_vbit_addr = 0x610c0,
0344 .hdmi_ch_lsb_addr = 0x61048,
0345 .hdmi_ch_msb_addr = 0x6104c,
0346 .ch_stride = 0x8,
0347 .hdmi_parity_addr = 0x61034,
0348 .hdmi_dmactl_addr = 0x61038,
0349 .hdmi_dma_stride = 0x4,
0350 .hdmi_DP_addr = 0x610c8,
0351 .hdmi_sstream_addr = 0x6101c,
0352 .hdmi_irq_reg_base = 0x63000,
0353 .hdmi_irq_ports = 1,
0354
0355 .hdmi_rdma_dyncclk = REG_FIELD_ID(0x64000, 14, 14, 4, 0x1000),
0356 .hdmi_rdma_bursten = REG_FIELD_ID(0x64000, 13, 13, 4, 0x1000),
0357 .hdmi_rdma_burst8 = REG_FIELD_ID(0x64000, 15, 15, 4, 0x1000),
0358 .hdmi_rdma_burst16 = REG_FIELD_ID(0x64000, 16, 16, 4, 0x1000),
0359 .hdmi_rdma_dynburst = REG_FIELD_ID(0x64000, 18, 18, 4, 0x1000),
0360 .hdmi_rdma_wpscnt = REG_FIELD_ID(0x64000, 10, 12, 4, 0x1000),
0361 .hdmi_rdma_fifowm = REG_FIELD_ID(0x64000, 1, 5, 4, 0x1000),
0362 .hdmi_rdma_enable = REG_FIELD_ID(0x64000, 0, 0, 4, 0x1000),
0363
0364 .sstream_en = REG_FIELD(0x6101c, 0, 0),
0365 .dma_sel = REG_FIELD(0x6101c, 1, 2),
0366 .auto_bbit_en = REG_FIELD(0x6101c, 3, 3),
0367 .layout = REG_FIELD(0x6101c, 4, 4),
0368 .layout_sp = REG_FIELD(0x6101c, 5, 8),
0369 .set_sp_on_en = REG_FIELD(0x6101c, 10, 10),
0370 .dp_audio = REG_FIELD(0x6101c, 11, 11),
0371 .dp_staffing_en = REG_FIELD(0x6101c, 12, 12),
0372 .dp_sp_b_hw_en = REG_FIELD(0x6101c, 13, 13),
0373
0374 .mute = REG_FIELD(0x610c8, 0, 0),
0375 .as_sdp_cc = REG_FIELD(0x610c8, 1, 3),
0376 .as_sdp_ct = REG_FIELD(0x610c8, 4, 7),
0377 .aif_db4 = REG_FIELD(0x610c8, 8, 15),
0378 .frequency = REG_FIELD(0x610c8, 16, 21),
0379 .mst_index = REG_FIELD(0x610c8, 28, 29),
0380 .dptx_index = REG_FIELD(0x610c8, 30, 31),
0381
0382 .soft_reset = REG_FIELD(0x1000, 31, 31),
0383 .force_reset = REG_FIELD(0x1000, 30, 30),
0384
0385 .use_hw_chs = REG_FIELD(0x61038, 0, 0),
0386 .use_hw_usr = REG_FIELD(0x61038, 1, 1),
0387 .hw_chs_sel = REG_FIELD(0x61038, 2, 4),
0388 .hw_usr_sel = REG_FIELD(0x61038, 5, 6),
0389
0390 .replace_vbit = REG_FIELD(0x610c0, 0, 0),
0391 .vbit_stream = REG_FIELD(0x610c0, 1, 1),
0392
0393 .legacy_en = REG_FIELD(0x1008, 0, 0),
0394 .calc_en = REG_FIELD(0x61034, 0, 0),
0395 .lsb_bits = REG_FIELD(0x61048, 0, 31),
0396 .msb_bits = REG_FIELD(0x6104c, 0, 31),
0397
0398 .clk_name = (const char*[]) {
0399 "core_cc_sysnoc_mport_core"
0400 },
0401 .num_clks = 1,
0402
0403 .dai_driver = sc7280_lpass_cpu_dai_driver,
0404 .num_dai = ARRAY_SIZE(sc7280_lpass_cpu_dai_driver),
0405 .dai_osr_clk_names = (const char *[]) {
0406 "audio_cc_ext_mclk0",
0407 "null"
0408 },
0409 .dai_bit_clk_names = (const char *[]) {
0410 "core_cc_ext_if0_ibit",
0411 "core_cc_ext_if1_ibit"
0412 },
0413 .init = sc7280_lpass_init,
0414 .exit = sc7280_lpass_exit,
0415 .alloc_dma_channel = sc7280_lpass_alloc_dma_channel,
0416 .free_dma_channel = sc7280_lpass_free_dma_channel,
0417 };
0418
0419 static const struct of_device_id sc7280_lpass_cpu_device_id[] = {
0420 {.compatible = "qcom,sc7280-lpass-cpu", .data = &sc7280_data},
0421 {}
0422 };
0423 MODULE_DEVICE_TABLE(of, sc7280_lpass_cpu_device_id);
0424
0425 static struct platform_driver sc7280_lpass_cpu_platform_driver = {
0426 .driver = {
0427 .name = "sc7280-lpass-cpu",
0428 .of_match_table = of_match_ptr(sc7280_lpass_cpu_device_id),
0429 },
0430 .probe = asoc_qcom_lpass_cpu_platform_probe,
0431 .remove = asoc_qcom_lpass_cpu_platform_remove,
0432 .shutdown = asoc_qcom_lpass_cpu_platform_shutdown,
0433 };
0434
0435 module_platform_driver(sc7280_lpass_cpu_platform_driver);
0436
0437 MODULE_DESCRIPTION("SC7280 LPASS CPU DRIVER");
0438 MODULE_LICENSE("GPL");
